diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd index 054683f366273f71355e12717f0044ffb3a627b7..cc4b813b0501aab5a16e2fc3f0d4b966970829ca 100644 --- a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd +++ b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd @@ -314,6 +314,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS -- De and Reinterleaver SIGNAL dp_deinterleave_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0); SIGNAL dp_pipeline_snk_in : t_dp_sosi; + SIGNAL dp_pipeline_src_out : t_dp_sosi; SIGNAL interleaved_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0); SIGNAL deinterleaved_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0); SIGNAL reinterleave_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0); @@ -321,6 +322,9 @@ ARCHITECTURE str OF apertif_unb1_correlator IS --Data buffers SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0); + + -- dp_block_gen + SIGNAL dp_block_gen_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0); -- Filterbank and Correlator SIGNAL wpfb_snk_in_ctrl : t_dp_sosi; @@ -346,10 +350,6 @@ ARCHITECTURE str OF apertif_unb1_correlator IS SIGNAL mesh_rx_src_in_2arr : t_unb1_board_mesh_siso_2arr; SIGNAL mesh_rx_src_out_2arr : t_unb1_board_mesh_sosi_2arr; - -- dp_block_gen - SIGNAL dp_block_gen_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0); - SIGNAL dp_block_gen_src_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0); - BEGIN ----------------------------------------------------------------------------- @@ -771,19 +771,18 @@ BEGIN PORT MAP ( rst => dp_rst, clk => dp_clk, - -- ST sink - snk_in => dp_pipeline_snk_in, --interleaved_arr(0), - -- ST source - src_out => wpfb_snk_in_ctrl + + snk_in => dp_pipeline_snk_in, + src_out => dp_pipeline_src_out ); - p_add_st_ctrl : PROCESS(reinterleave_out_arr, wpfb_snk_in_ctrl) + p_add_st_ctrl : PROCESS(reinterleave_out_arr, dp_pipeline_src_out) BEGIN FOR i IN 0 TO c_nof_input_streams-1 LOOP - wpfb_snk_in_arr(i) <= wpfb_snk_in_ctrl; -- SOSI ctrl - wpfb_snk_in_arr(i).data <= reinterleave_out_arr(i).data; - wpfb_snk_in_arr(i).im <= reinterleave_out_arr(i).im; - wpfb_snk_in_arr(i).re <= reinterleave_out_arr(i).re; + dp_block_gen_snk_in_arr(i) <= dp_pipeline_src_out; -- SOSI ctrl + dp_block_gen_snk_in_arr(i).data <= reinterleave_out_arr(i).data; + dp_block_gen_snk_in_arr(i).im <= reinterleave_out_arr(i).im; + dp_block_gen_snk_in_arr(i).re <= reinterleave_out_arr(i).re; END LOOP; END PROCESS; @@ -903,6 +902,25 @@ BEGIN ); END GENERATE; -- g_use_dumb_mesh_terminals + ----------------------------------------------------------------------------- + -- Re-assign SOP and EOP + -- . WPFB required blocks of 128 words (2*64, interleaved) + ----------------------------------------------------------------------------- + gen_dp_block_gen : FOR i IN 0 TO c_nof_input_streams-1 GENERATE + u_dp_block_gen : ENTITY dp_lib.dp_block_gen + GENERIC MAP( + g_use_src_in => FALSE, + g_nof_data => 128 + ) + PORT MAP( + rst => dp_rst, + clk => dp_clk, + + snk_in => dp_block_gen_snk_in_arr(i), + src_out => wpfb_snk_in_arr(i) + ); + END GENERATE; + ----------------------------------------------------------------------------- -- WPFB ----------------------------------------------------------------------------- @@ -935,7 +953,7 @@ BEGIN -- Workaround for simulation: the first WPFB output block is not usable! --FIXME -- Forward only blocks with BSN 5+ ----------------------------------------------------------------------------- - p_bsn_filter : PROCESS(wpfb_snk_in_arr) + p_bsn_filter : PROCESS(wpfb_src_out_arr) BEGIN correlator_snk_in_arr <= (OTHERS=>c_dp_sosi_rst); IF TO_UINT(wpfb_src_out_arr(0).bsn)>=5 THEN