diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index 31cf5e202561d25d6780c9b1b8d4a7f13d5dc1e4..3cd860ffc89319ad67f6d557262409dbb1da9b6e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -51,6 +51,7 @@ ENTITY lofar2_unb2b_ring IS
     g_design_note            : STRING  := "UNUSED";
     g_technology             : NATURAL := c_tech_arria10_e1sg;
     g_sim                    : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_sync_timeout       : NATURAL := 3*1024;
     g_sim_unb_nr             : NATURAL := 0;
     g_sim_node_nr            : NATURAL := 0;
     g_stamp_date             : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
@@ -129,10 +130,10 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
   CONSTANT c_nof_mac                : NATURAL := 3 * c_nof_even_lanes; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
 
   CONSTANT c_lane_data_w               : NATURAL := 64; 
-  CONSTANT c_lane_packet_length        : NATURAL := 1024; 
+  CONSTANT c_lane_packet_length        : NATURAL := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size; -- = 48 longwords per packet, so the maximum data rate with a packetrate of 195312.5 and all 16 nodes combined = 16 * 48 / 1024 * 64 * 200M = 9.6 Gb/s 
   CONSTANT c_use_dp_layer              : BOOLEAN := TRUE; 
-  CONSTANT c_nof_rx_monitors           : NATURAL := 1; 
-  CONSTANT c_nof_tx_monitors           : NATURAL := 1; 
+  CONSTANT c_nof_rx_monitors           : NATURAL := c_sdp_N_rn_max; 
+  CONSTANT c_nof_tx_monitors           : NATURAL := c_sdp_N_rn_max; 
   CONSTANT c_err_bi                    : NATURAL := 0; 
   CONSTANT c_nof_err_counts            : NATURAL := 8; 
   CONSTANT c_validate_err_fifo_size    : NATURAL := 1536; 
@@ -141,7 +142,7 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
   CONSTANT c_validate_channel_mode     : STRING  := "=";
   CONSTANT c_fifo_tx_fill              : NATURAL := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); --total packet length
   CONSTANT c_fifo_tx_size              : NATURAL := 2 * c_lane_packet_length; 
-
+  CONSTANT c_sync_timeout              : NATURAL := sel_a_b(g_sim, g_sim_sync_timeout, c_lofar2_sample_clk_freq);
   CONSTANT c_addr_w_reg_ring_lane_info                : NATURAL := 1; 
   CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_rx        : NATURAL := ceil_log2(c_nof_rx_monitors) + 3; 
   CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_tx        : NATURAL := ceil_log2(c_nof_tx_monitors) + 3; 
@@ -645,7 +646,7 @@ BEGIN
   u_mmp_dp_xonoff_lane : ENTITY dp_lib.mms_dp_xonoff
   GENERIC MAP (
     g_nof_streams   => c_nof_lanes,
-    g_default_value => '0'
+    g_default_value => '1' --default enabled
   )
   PORT MAP (
     mm_rst => mm_rst,
@@ -674,7 +675,7 @@ BEGIN
   u_mmp_dp_xonoff_local : ENTITY dp_lib.mms_dp_xonoff
   GENERIC MAP (
     g_nof_streams   => c_nof_lanes,
-    g_default_value => '0'
+    g_default_value => '0' -- default disabled
   )
   PORT MAP (
     mm_rst => mm_rst,
@@ -706,7 +707,17 @@ BEGIN
     u_dp_mux : ENTITY dp_lib.dp_mux
     GENERIC MAP (
       g_append_channel_lo => FALSE,
-      g_sel_ctrl_invert   => TRUE
+      g_sel_ctrl_invert   => TRUE,
+      g_use_fifo          => TRUE,
+      g_bsn_w             => c_longword_w,
+      g_data_w            => c_lane_data_w, 
+      g_in_channel_w      => c_byte_w,
+      g_error_w           => c_nof_err_counts,
+      g_use_bsn           => TRUE,
+      g_use_in_channel    => TRUE,
+      g_use_error         => TRUE,
+      g_use_sync          => TRUE,
+      g_fifo_size         => array_init(2*c_lane_packet_length, 2)
     )
     PORT MAP (
       rst => dp_rst,
@@ -736,7 +747,13 @@ BEGIN
 
     ring_info => ring_info
   );
-  this_rn <= TO_UVEC(TO_UINT(ID) - TO_UINT(ring_info.O_rn), c_byte_w);
+
+  gen_sim_this_rn: IF g_sim GENERATE
+    this_rn <= TO_UVEC(g_sim_node_nr, c_byte_w);
+  END GENERATE;
+  gen_no_sim_this_rn: IF NOT g_sim GENERATE
+    this_rn <= TO_UVEC(TO_UINT(ID) - TO_UINT(ring_info.O_rn), c_byte_w);
+  END GENERATE;
 
   -----------------------------------------------------------------------------
   -- Ring lane even indices.
@@ -755,7 +772,8 @@ BEGIN
       g_validate_err_fifo_size    => c_validate_err_fifo_size,
       g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
       g_validate_channel          => c_validate_channel,
-      g_validate_channel_mode     => c_validate_channel_mode    
+      g_validate_channel_mode     => c_validate_channel_mode,
+      g_sync_timeout              => c_sync_timeout    
     )
     PORT MAP (
       mm_rst => mm_rst,
@@ -806,7 +824,8 @@ BEGIN
       g_validate_err_fifo_size    => c_validate_err_fifo_size,
       g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
       g_validate_channel          => c_validate_channel,
-      g_validate_channel_mode     => c_validate_channel_mode    
+      g_validate_channel_mode     => c_validate_channel_mode,
+      g_sync_timeout              => c_sync_timeout    
     )
     PORT MAP (
       mm_rst => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index 93ac9db79e3f1c1e2d99536b408fc06886a75ec7..349a444c0fca8b442ebebd80404b7bfa4a9c54e8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -78,14 +78,14 @@ PACKAGE qsys_lofar2_unb2b_ring_pkg IS
             ram_scrap_reset_export                             : out std_logic;                                        -- export
             ram_scrap_write_export                             : out std_logic;                                        -- export
             ram_scrap_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_ring_rx_address_export          : out std_logic_vector(6 downto 0);                     -- export
+            reg_bsn_monitor_v2_ring_rx_address_export          : out std_logic_vector(9 downto 0);                     -- export
             reg_bsn_monitor_v2_ring_rx_clk_export              : out std_logic;                                        -- export
             reg_bsn_monitor_v2_ring_rx_read_export             : out std_logic;                                        -- export
             reg_bsn_monitor_v2_ring_rx_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reg_bsn_monitor_v2_ring_rx_reset_export            : out std_logic;                                        -- export
             reg_bsn_monitor_v2_ring_rx_write_export            : out std_logic;                                        -- export
             reg_bsn_monitor_v2_ring_rx_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_ring_tx_address_export          : out std_logic_vector(6 downto 0);                     -- export
+            reg_bsn_monitor_v2_ring_tx_address_export          : out std_logic_vector(9 downto 0);                     -- export
             reg_bsn_monitor_v2_ring_tx_clk_export              : out std_logic;                                        -- export
             reg_bsn_monitor_v2_ring_tx_read_export             : out std_logic;                                        -- export
             reg_bsn_monitor_v2_ring_tx_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index 95018ff1988735e3e9fc847fb6bac975b65ded57..bd89f0eefa58ee9b65ae3ca01834792fb16bccf0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -48,7 +48,7 @@
 --   > run -a  
 --
 -------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, ring_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE IEEE.MATH_REAL.ALL;
@@ -63,8 +63,15 @@ USE diag_lib.diag_pkg.ALL;
 USE wpfb_lib.wpfb_pkg.ALL;
 USE lofar2_sdp_lib.sdp_pkg.ALL;
 USE tech_pll_lib.tech_pll_component_pkg.ALL;
+USE ring_lib.ring_pkg.ALL;
+USE work.lofar2_unb2b_ring_pkg.ALL;
 
 ENTITY tb_lofar2_unb2b_ring IS
+  GENERIC (
+    g_design_name    : STRING               := "lofar2_unb2b_ring_one";
+    g_nof_rn         : NATURAL              := 3;
+    g_access_scheme  : INTEGER RANGE 1 TO 3 := 3
+  );
 END tb_lofar2_unb2b_ring;
 
 ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
@@ -75,8 +82,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
   CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
   CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
   CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
-  CONSTANT c_nof_rn          : NATURAL := 3; -- nodes 0,1,2.
-
+  
   CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
   CONSTANT c_ext_clk_period      : TIME := 5 ns;
   CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
@@ -86,18 +92,26 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
   CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
   CONSTANT c_cable_delay         : TIME := 12 ns;
 
-  CONSTANT c_percentage          : REAL := 0.05;  -- percentage that actual value may differ from expected value
-  CONSTANT c_lo_factor           : REAL := 1.0 - c_percentage;  -- lower boundary  
-  CONSTANT c_hi_factor           : REAL := 1.0 + c_percentage;  -- higher boundary
+  CONSTANT c_revision_select     : t_lofar2_unb2b_ring_config := func_sel_revision_rec(g_design_name);
+  CONSTANT c_nof_lanes           : NATURAL := c_revision_select.N_ring_lanes;
 
-   
+  CONSTANT c_block_period        : NATURAL := 1024;
+  CONSTANT c_blocksize           : NATURAL := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
+  CONSTANT c_gapsize             : NATURAL := c_block_period - c_blocksize;
+  CONSTANT c_nof_block_per_sync  : NATURAL := 3;
+  CONSTANT c_sync_timeout        : NATURAL := c_block_period * c_nof_block_per_sync + 1;
+  CONSTANT c_exp_bsn_at_sync     : NATURAL := c_nof_block_per_sync;
+  CONSTANT c_exp_nof_sop         : NATURAL := c_nof_block_per_sync;
+  CONSTANT c_exp_nof_valid       : NATURAL := c_nof_block_per_sync * c_blocksize;
+
+ 
   -- MM  
   CONSTANT c_mm_file_reg_ring_info               : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RING_INFO";
   CONSTANT c_mm_file_reg_ring_lane_info          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RING_LANE_INFO";
   CONSTANT c_mm_file_reg_diag_bg                 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DIAG_BG";
   CONSTANT c_mm_file_ram_diag_bg                 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_DIAG_BG";
-  CONSTANT c_mm_file_reg_ring_input_select       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RING_INPUT_SELECT";
-  CONSTANT c_mm_file_reg_dp_xonoff_ring          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_RING";
+  CONSTANT c_mm_file_reg_dp_xonoff_lane          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_LANE";
+  CONSTANT c_mm_file_reg_dp_xonoff_local         : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_LOCAL";
   CONSTANT c_mm_file_reg_bsn_monitor_v2_ring_rx  : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RING_RX";
   CONSTANT c_mm_file_reg_bsn_monitor_v2_ring_tx  : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RING_TX";
 
@@ -107,12 +121,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
   SIGNAL tb_clk              : STD_LOGIC := '0';  
   SIGNAL rd_data             : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
 
-  SIGNAL i_QSFP_0_TX         : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
-  SIGNAL i_QSFP_0_RX         : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
-  SIGNAL i_RING_0_TX         : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
-  SIGNAL i_RING_0_RX         : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
-  SIGNAL i_RING_1_TX         : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
-  SIGNAL i_RING_1_RX         : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+  SIGNAL i_QSFP_0_TX         : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+  SIGNAL i_QSFP_0_RX         : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+  SIGNAL i_RING_0_TX         : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+  SIGNAL i_RING_0_RX         : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+  SIGNAL i_RING_1_TX         : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+  SIGNAL i_RING_1_RX         : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
 
   -- DUT
   SIGNAL ext_clk             : STD_LOGIC := '0';
@@ -163,14 +177,15 @@ BEGIN
   ------------------------------------------------------------------------------
   -- DUTs
   ------------------------------------------------------------------------------
-  gen_dut : FOR I IN 0 TO c_nof_rn -1 GENERATE
+  gen_dut : FOR I IN 0 TO g_nof_rn -1 GENERATE
     u_lofar_unb2b_ring : ENTITY work.lofar2_unb2b_ring
     GENERIC MAP (
-      g_design_name            => "lofar2_unb2b_ring_one",
+      g_design_name            => g_design_name,
       g_design_note            => "",
       g_sim                    => c_sim,
       g_sim_unb_nr             => c_unb_nr,
-      g_sim_node_nr            => I
+      g_sim_node_nr            => I,
+      g_sim_sync_timeout       => c_sync_timeout
     )
     PORT MAP (
       -- GENERAL
@@ -216,14 +231,14 @@ BEGIN
   END GENERATE;
 
   -- Ring connections
-  gen_ring : FOR I IN 0 TO c_nof_rn -2 GENERATE
+  gen_ring : FOR I IN 0 TO g_nof_rn -2 GENERATE
     -- Connect consecutive nodes with RING interfaces (PCB)
     i_RING_0_RX(I+1) <= i_RING_1_TX(I);
     i_RING_1_RX(I)   <= i_RING_0_TX(I+1);
   END GENERATE;
   -- Connect first and last nodes with QSFP interface. 
-  i_QSFP_0_RX(0)          <= i_QSFP_0_TX(c_nof_rn-1);
-  i_QSFP_0_RX(c_nof_rn-1) <= i_QSFP_0_TX(0);
+  i_QSFP_0_RX(0)          <= i_QSFP_0_TX(g_nof_rn-1);
+  i_QSFP_0_RX(g_nof_rn-1) <= i_QSFP_0_TX(0);
   
 
 
@@ -233,11 +248,6 @@ BEGIN
   tb_clk  <= NOT tb_clk AFTER c_tb_clk_period/2;    -- Testbench MM clock
   
   p_mm_stimuli : PROCESS
-    VARIABLE v_bsn                   : NATURAL;
-    VARIABLE v_sp_power_sum_0        : REAL;
-    VARIABLE v_sp_beamlet_power      : REAL;
-    VARIABLE v_sp_subband_power      : REAL;
-    VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL;  -- array indicies
   BEGIN
     -- Wait for DUT power up after reset
     WAIT FOR 1 us;
@@ -245,9 +255,9 @@ BEGIN
     proc_common_wait_until_hi_lo(ext_clk, ext_pps);
 
     -- Write ring configuration to all nodes.
-    FOR I IN 0 TO c_nof_rn-1 LOOP
-      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, I) & "REG_RING_INFO", 2, c_nof_rn, tb_clk); -- N_rn
-      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, I) & "REG_RING_INFO", 3, 0,        tb_clk); -- O_rn
+    FOR RN IN 0 TO g_nof_rn-1 LOOP
+      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
+      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_RING_INFO", 3, 0,        tb_clk); -- O_rn
     END LOOP;
 
     -- Start node specific settings
@@ -255,31 +265,122 @@ BEGIN
     mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- tx_select = 0
   
     -- End node specific settings
-    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, c_nof_rn-1) & "REG_RING_INFO", 0, 0, tb_clk); -- rx_select = 0
-    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, c_nof_rn-1) & "REG_RING_INFO", 1, 1, tb_clk); -- tx_select = 1
-  
-    -- Select local input (= 1) on  start node
-    mmf_mm_bus_wr(c_mm_file_reg_ring_input_select, 0, 1, tb_clk); 
-    
-    -- Set transport_nof_hops to N_rn on start node for one full transfer around the ring.
-    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_LANE_INFO", 1, c_nof_rn, tb_clk);
-   
-
+    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 0, 0, tb_clk); -- rx_select = 0
+    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 1, 1, tb_clk); -- tx_select = 1
+     
+    ----------------------------------------------------------------------------
+    -- Access scheme 1. A source RN creates the packets and sends them along the ring.
+    ----------------------------------------------------------------------------
+    IF g_access_scheme = 1 THEN
+      FOR I IN 0 TO c_nof_lanes-1 LOOP
+        -- Select local input (= 1) on  start node on all lanes.
+        mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_lane,  I*2, 0, tb_clk); -- Disable input from lane
+        mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_local, I*2, 1, tb_clk); -- Enable local input
+        
+        -- Set transport_nof_hops to N_rn on start node for a full transfer around the ring.
+        mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn, tb_clk);
+      END LOOP;
+     
+    ----------------------------------------------------------------------------
+    -- Access scheme 2, 3. Each RN creates packets and sends them along the ring.
+    ----------------------------------------------------------------------------
+    ELSE  
+      FOR RN IN 0 TO g_nof_rn-1 LOOP
+        FOR I IN 0 TO c_nof_lanes-1 LOOP
+          -- Select both local and remote input on all nodes on all lanes.
+          mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_DP_XONOFF_LANE",  I*2, 1, tb_clk); -- Enable input from lane
+          mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_DP_XONOFF_LOCAL", I*2, 1, tb_clk); -- Enable local input
+          
+          -- Set transport_nof_hops to N_rn-1 on all nodes.
+          mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn-1, tb_clk);
+        END LOOP;
+      END LOOP;
+    END IF;
     ----------------------------------------------------------------------------
     -- Enable BG on all nodes (for bs_sosi)
     ----------------------------------------------------------------------------
-    FOR I IN 0 TO c_nof_rn-1 LOOP
-      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, I) & "REG_DIAG_BG", 1, 1024 , tb_clk); -- samples per packet
-      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, I) & "REG_DIAG_BG", 2,    3 , tb_clk); -- blocks per sync
-      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, I) & "REG_DIAG_BG", 3,  512 , tb_clk); -- gapsize
-      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, I) & "REG_DIAG_BG", 0,    3 , tb_clk); -- enable at sync
+    FOR RN IN 0 TO g_nof_rn-1 LOOP
+      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_DIAG_BG", 1,          c_blocksize, tb_clk); -- samples per packet
+      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_DIAG_BG", 2, c_nof_block_per_sync, tb_clk); -- blocks per sync
+      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_DIAG_BG", 3,            c_gapsize, tb_clk); -- gapsize
+      mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_DIAG_BG", 0,                    3, tb_clk); -- enable at sync
     END LOOP;
+    ----------------------------------------------------------------------------
+    -- Verify Access scheme 1 by reading rx / tx monitors on source RN
+    ----------------------------------------------------------------------------
+    IF g_access_scheme = 1 THEN
+      -- Wait for bsn monitor to have received a sync period.
+      mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4, -- read nof valid
+                              "UNSIGNED", rd_data, ">", 0,             -- this is the wait until condition
+                              1 us, tb_clk);                           -- read every 1 us
+
+      FOR I IN 0 TO c_nof_lanes-1 LOOP
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_rn_max*8+1, rd_data, tb_clk); --bsn at sync
+        ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1." SEVERITY ERROR;
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_rn_max*8+3, rd_data, tb_clk); --nof_sop
+        ASSERT TO_UINT(rd_data) = c_exp_nof_sop     REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1."     SEVERITY ERROR;
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_rn_max*8+4, rd_data, tb_clk); --nof_valid
+        ASSERT TO_UINT(rd_data) = c_exp_nof_valid   REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1."   SEVERITY ERROR;
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_rn_max*8+5, rd_data, tb_clk); --nof_err
+        ASSERT TO_UINT(rd_data) = 0                 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1."     SEVERITY ERROR;
 
-    -- Wait for bsn monitor
-    WAIT FOR 20 us;
-    mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4, -- read nof valid
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_rn_max*8+1, rd_data, tb_clk); --bsn at sync
+        ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1." SEVERITY ERROR;
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_rn_max*8+3, rd_data, tb_clk); --nof_sop
+        ASSERT TO_UINT(rd_data) = c_exp_nof_sop     REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1."     SEVERITY ERROR;
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_rn_max*8+4, rd_data, tb_clk); --nof_valid
+        ASSERT TO_UINT(rd_data) = c_exp_nof_valid   REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1."   SEVERITY ERROR;
+        mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_rn_max*8+5, rd_data, tb_clk); --nof_err
+        ASSERT TO_UINT(rd_data) = 0                 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1."     SEVERITY ERROR;
+      END LOOP;
+
+    ----------------------------------------------------------------------------
+    -- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
+    ----------------------------------------------------------------------------
+    ELSE
+    -- Wait for bsn monitor to have received a sync period.
+    mmf_mm_wait_until_value(mmf_unb_file_prefix(c_unb_nr, g_nof_rn-1) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
                             "UNSIGNED", rd_data, ">", 0,             -- this is the wait until condition
-                            1 us, tb_clk);                           -- read every 1 us 
+                            1 us, tb_clk);                           -- read every 1 us
+
+      FOR RN IN 0 TO g_nof_rn-1 LOOP
+        FOR I IN 0 TO c_nof_lanes-1 LOOP -- lane index
+          FOR J IN 0 TO g_nof_rn-1 LOOP  -- bsn_monitor index
+            -- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
+            IF (I MOD 2 = 0 AND (RN + 1) MOD g_nof_rn = J) OR (I MOD 2 = 1 AND (RN + g_nof_rn-1) MOD g_nof_rn = J) THEN 
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_rn_max + J) * 8+0, rd_data, tb_clk); --status bits
+              ASSERT rd_data(2) = '1'                     REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;          
+            ELSE
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_rn_max + J) * 8+0, rd_data, tb_clk); --status bits
+              ASSERT rd_data(2) = '0'                     REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;  
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_rn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
+              ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_rn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
+              ASSERT TO_UINT(rd_data) = c_exp_nof_sop     REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_"     & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_rn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
+              ASSERT TO_UINT(rd_data) = c_exp_nof_valid   REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_"   & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_rn_max + J) * 8+5, rd_data, tb_clk); --nof_err
+              ASSERT TO_UINT(rd_data) = 0                 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_"     & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+            END IF; 
+            IF RN = J THEN -- No packets received from itself as the previous RN should have removed it from the ring.
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_rn_max + J) * 8+0, rd_data, tb_clk); --status bits
+              ASSERT rd_data(2) = '1'                     REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;          
+            ELSE
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_rn_max + J) * 8+0, rd_data, tb_clk); --status bits
+              ASSERT rd_data(2) = '0'                     REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;  
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_rn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
+              ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_rn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
+              ASSERT TO_UINT(rd_data) = c_exp_nof_sop     REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_"     & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_rn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
+              ASSERT TO_UINT(rd_data) = c_exp_nof_valid   REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_"   & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+              mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_rn_max + J) * 8+5, rd_data, tb_clk); --nof_err
+              ASSERT TO_UINT(rd_data) = 0                 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_"     & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+            END IF;
+          END LOOP;
+        END LOOP;
+      END LOOP;
+    END IF;
 
     ---------------------------------------------------------------------------
     -- End Simulation 
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index aeaa4b503ef02754561922705d2f9803c9444a18..3790611d4d8da7db9b926d9eb491400ce22eae1a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -67,34 +67,36 @@ PACKAGE sdp_pkg is
   -------------------------------------------------
   -- SDP specific parameters as defined in:
   --  L3 SDP Decision: SDP Parameter definitions 
-  CONSTANT c_sdp_f_adc_MHz       : NATURAL := 200;
-  CONSTANT c_sdp_N_beamsets      : NATURAL := 2;
-  CONSTANT c_sdp_N_crosslets_max : NATURAL := 7;
-  CONSTANT c_sdp_N_fft           : NATURAL := 1024;
-  CONSTANT c_sdp_N_pn_lb         : NATURAL := 16;
-  CONSTANT c_sdp_N_pol           : NATURAL := 2;
-  CONSTANT c_sdp_N_pol_bf        : NATURAL := 2;
-  CONSTANT c_sdp_N_ring_lanes_max: NATURAL := 8;
-  CONSTANT c_sdp_N_sub           : NATURAL := 512;
-  CONSTANT c_sdp_N_taps          : NATURAL := 16;
-  CONSTANT c_sdp_P_sq            : NATURAL := 9;
-  CONSTANT c_sdp_Q_fft           : NATURAL := 2;
-  CONSTANT c_sdp_S_pn            : NATURAL := 12;
-  CONSTANT c_sdp_S_rcu           : NATURAL := 3;
-  CONSTANT c_sdp_S_sub_bf        : NATURAL := 488;
-  CONSTANT c_sdp_V_sample_delay  : NATURAL := 4096;
-  CONSTANT c_sdp_V_si_db         : NATURAL := 1024;
-  CONSTANT c_sdp_V_si_db_large   : NATURAL := 131072;
-  CONSTANT c_sdp_V_si_histogram  : NATURAL := 512;
-  CONSTANT c_sdp_W_adc           : NATURAL := 14;
-  CONSTANT c_sdp_W_adc_jesd      : NATURAL := 16;
-  CONSTANT c_sdp_W_fir_coef      : NATURAL := 16;
-  CONSTANT c_sdp_W_subband       : NATURAL := 18;
-  CONSTANT c_sdp_W_crosslet      : NATURAL := 16;
-  CONSTANT c_sdp_W_beamlet_sum   : NATURAL := 18;
-  CONSTANT c_sdp_W_beamlet       : NATURAL := 8;
-  CONSTANT c_sdp_W_gn_id         : NATURAL := 5;
-  CONSTANT c_sdp_W_statistic     : NATURAL := 64;
+  CONSTANT c_sdp_f_adc_MHz          : NATURAL := 200;
+  CONSTANT c_sdp_N_beamsets         : NATURAL := 2;
+  CONSTANT c_sdp_N_crosslets_max    : NATURAL := 7;
+  CONSTANT c_sdp_N_fft              : NATURAL := 1024;
+  CONSTANT c_sdp_N_pn_lb            : NATURAL := 16;
+  CONSTANT c_sdp_N_pol              : NATURAL := 2;
+  CONSTANT c_sdp_N_pol_bf           : NATURAL := 2;
+  CONSTANT c_sdp_N_ring_lanes_max   : NATURAL := 8;
+  CONSTANT c_sdp_N_rn_max           : NATURAL := 16;
+  CONSTANT c_sdp_N_sub              : NATURAL := 512;
+  CONSTANT c_sdp_N_taps             : NATURAL := 16;
+  CONSTANT c_sdp_P_sq               : NATURAL := 9;
+  CONSTANT c_sdp_Q_fft              : NATURAL := 2;
+  CONSTANT c_sdp_S_pn               : NATURAL := 12;
+  CONSTANT c_sdp_S_rcu              : NATURAL := 3;
+  CONSTANT c_sdp_S_sub_bf           : NATURAL := 488;
+  CONSTANT c_sdp_V_ring_pkt_len_max : NATURAL := 48; -- for 16 nodes
+  CONSTANT c_sdp_V_sample_delay     : NATURAL := 4096;
+  CONSTANT c_sdp_V_si_db            : NATURAL := 1024;
+  CONSTANT c_sdp_V_si_db_large      : NATURAL := 131072;
+  CONSTANT c_sdp_V_si_histogram     : NATURAL := 512;
+  CONSTANT c_sdp_W_adc              : NATURAL := 14;
+  CONSTANT c_sdp_W_adc_jesd         : NATURAL := 16;
+  CONSTANT c_sdp_W_fir_coef         : NATURAL := 16;
+  CONSTANT c_sdp_W_subband          : NATURAL := 18;
+  CONSTANT c_sdp_W_crosslet         : NATURAL := 16;
+  CONSTANT c_sdp_W_beamlet_sum      : NATURAL := 18;
+  CONSTANT c_sdp_W_beamlet          : NATURAL := 8;
+  CONSTANT c_sdp_W_gn_id            : NATURAL := 5;
+  CONSTANT c_sdp_W_statistic        : NATURAL := 64;
   CONSTANT c_sdp_W_sub_weight              : NATURAL := 16;  -- = w in s(w, p), s = signed
   CONSTANT c_sdp_W_sub_weight_fraction     : NATURAL := 13;  -- = p in s(w, p)
   CONSTANT c_sdp_W_sub_weight_magnitude    : NATURAL := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1;  -- = 2
@@ -346,8 +348,8 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_ram_st_xsq_addr_w                  : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
 
   -- RING MM address widths
-  CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w        : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4; 
-  CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w        : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4; 
+  CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w        : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_rn_max) + ceil_Log2(7); 
+  CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w        : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_rn_max) + ceil_Log2(7); 
   CONSTANT c_sdp_reg_ring_lane_info_addr_w                : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1; 
   CONSTANT c_sdp_reg_dp_xonoff_lane_addr_w                : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1; 
   CONSTANT c_sdp_reg_dp_xonoff_local_addr_w               : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1; 
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index fb11b08d928086630b22b7f35b1fd95b9644a950..ead0038c65910aa3c063387457d08300ec968cde 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -163,9 +163,9 @@ BEGIN
   nxt_mon_nof_valid    <= nof_valid    WHEN sync='1' ELSE i_mon_nof_valid;
   nxt_mon_latency      <= latency      WHEN sync='1' ELSE i_mon_latency;
 
-  nof_sop   <= INCR_UVEC(cnt_sop, 1);    -- +1 because the sop at the sync also counts
+  nof_sop   <= cnt_sop;   
   nof_err   <= cnt_err;
-  nof_valid <= INCR_UVEC(cnt_valid, 1);  -- +1 because the valid at the sync also counts
+  nof_valid <= cnt_valid; 
   latency   <= cnt_latency;
   
   u_sync_timeout_cnt : ENTITY common_lib.common_counter
@@ -285,8 +285,9 @@ BEGIN
   PORT MAP (
     rst     => rst,
     clk     => clk,
-    cnt_clr => sync,
+    cnt_ld  => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
     cnt_en  => sop,
+    load    => TO_SVEC(1, c_cnt_sop_w),
     count   => cnt_sop
   );
   
@@ -309,8 +310,9 @@ BEGIN
   PORT MAP (
     rst     => rst,
     clk     => clk,
-    cnt_clr => sync,
+    cnt_ld  => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
     cnt_en  => valid,
+    load    => TO_SVEC(1, c_cnt_valid_w),
     count   => cnt_valid
   );
   
diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd
index 3295e70d67e60cd721360dd7402b8c8048cb602e..6d85a207e44a3c1b9a1d8928991d0c9a98972ab7 100644
--- a/libraries/base/ring/src/vhdl/ring_lane.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane.vhd
@@ -53,7 +53,8 @@ ENTITY ring_lane IS
     g_validate_err_fifo_size    : NATURAL := 1536; -- should be >= g_lane_packet_length
     g_bsn_at_sync_check_channel : NATURAL := 1; -- on which channel should the bsn be checked
     g_validate_channel          : BOOLEAN := TRUE;
-    g_validate_channel_mode     : STRING := ">"
+    g_validate_channel_mode     : STRING := ">";
+    g_sync_timeout              : NATURAL := 200*10**6 
   );
   PORT (
     -- Clocks and reset
@@ -122,7 +123,8 @@ BEGIN
     g_block_size      => g_lane_packet_length, 
     g_nof_err_counts  => g_nof_err_counts, 
     g_fifo_size       => g_validate_err_fifo_size, 
-    g_check_channel   => g_bsn_at_sync_check_channel 
+    g_check_channel   => g_bsn_at_sync_check_channel, 
+    g_sync_timeout    => g_sync_timeout
   )
   PORT MAP (
     mm_rst => mm_rst,                 
@@ -155,7 +157,8 @@ BEGIN
     g_data_w          => g_lane_data_w, 
     g_nof_tx_monitors => g_nof_tx_monitors, 
     g_validate_channel=> g_validate_channel,
-    g_mode            => g_validate_channel_mode
+    g_mode            => g_validate_channel_mode,
+    g_sync_timeout    => g_sync_timeout
   )
   PORT MAP (
     mm_rst =>  mm_rst,                 
diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd
index 79c02f64a076370e03aa005353ddb4fd2e73d31b..25448eb84e5b08b1299ab0b477e3cd5e75de525a 100644
--- a/libraries/base/ring/src/vhdl/ring_pkg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd
@@ -140,9 +140,9 @@ PACKAGE BODY ring_pkg IS
     VARIABLE v_source_rn_nat : NATURAL;
   BEGIN
 
-    IF lane_dir > 0 THEN
+    IF lane_dir > 0 THEN --transport in positive direction (even lanes)
       v_source_rn := this_rn - hops;
-    ELSE
+    ELSE                 --transport in negative direction (odd lanes)
       v_source_rn := this_rn + hops;
     END IF;
 
@@ -150,7 +150,7 @@ PACKAGE BODY ring_pkg IS
       v_source_rn := v_source_rn + N_rn;
     END IF;
 
-    IF v_source_rn > N_rn THEN
+    IF v_source_rn >= N_rn THEN
       v_source_rn := v_source_rn - N_rn;
     END IF;
 
@@ -160,7 +160,7 @@ PACKAGE BODY ring_pkg IS
 
   FUNCTION func_nof_hops_to_source_rn(hops, this_rn, N_rn : STD_LOGIC_VECTOR; lane_dir : NATURAL) RETURN STD_LOGIC_VECTOR IS
   BEGIN
-    RETURN TO_UVEC(func_nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(N_rn), TO_UINT(N_rn), lane_dir),hops'LENGTH);
+    RETURN TO_UVEC(func_nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(this_rn), TO_UINT(N_rn), lane_dir),hops'LENGTH);
   END;
   
 END ring_pkg;
diff --git a/libraries/base/ring/src/vhdl/ring_rx.vhd b/libraries/base/ring/src/vhdl/ring_rx.vhd
index e2828149b684312810ccd47f5620ac3c72765780..05e8e11c03d10fda318e58ab0ba6f7c1484ea867 100644
--- a/libraries/base/ring/src/vhdl/ring_rx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_rx.vhd
@@ -50,7 +50,8 @@ ENTITY ring_rx IS
     g_block_size       : NATURAL := 1024; 
     g_nof_err_counts   : NATURAL := 1; 
     g_fifo_size        : NATURAL := 1536; 
-    g_check_channel    : NATURAL := 1 
+    g_check_channel    : NATURAL := 1;
+    g_sync_timeout     : NATURAL := 200*10**6 
   );
   PORT (
     -- Clocks and reset
@@ -85,15 +86,18 @@ ARCHITECTURE str OF ring_rx IS
   CONSTANT c_hdr_field_arr  : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_arr, c_ring_eth_hdr_field_arr);
   CONSTANT c_hdr_field_size : NATURAL := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); 
   CONSTANT c_packet_size    : NATURAL := g_block_size + c_hdr_field_size;
+
   SIGNAL lane_rx_sosi     : t_dp_sosi;
   SIGNAL packet_sosi      : t_dp_sosi;
   SIGNAL validated_sosi   : t_dp_sosi;
   SIGNAL offload_rx_sosi  : t_dp_sosi;
   SIGNAL decoded_sosi     : t_dp_sosi;
   SIGNAL monitor_sosi     : t_dp_sosi;
-  SIGNAL monitor_sosi_arr : t_dp_sosi_arr(g_nof_rx_monitors-1 DOWNTO 0);
+  SIGNAL demux_sosi_arr   : t_dp_sosi_arr(0 TO g_nof_rx_monitors-1); -- using 0 TO ... as that is the output of the demux
+  SIGNAL monitor_sosi_arr : t_dp_sosi_arr(g_nof_rx_monitors-1 DOWNTO 0); 
 
   SIGNAL hdr_fields_out   : STD_LOGIC_VECTOR(1023 DOWNTO 0);
+  SIGNAL hdr_fields_raw   : STD_LOGIC_VECTOR(1023 DOWNTO 0);
 
 BEGIN
 
@@ -154,17 +158,18 @@ BEGIN
     snk_in_arr(0)  => validated_sosi,
     src_out_arr(0) => offload_rx_sosi,
 
-    hdr_fields_out_arr(0)  => hdr_fields_out
+    hdr_fields_out_arr(0)  => hdr_fields_out,
+    hdr_fields_raw_arr(0)  => hdr_fields_raw
   );
 
   -- Use dp layer
   gen_dp_layer : IF g_use_dp_layer GENERATE
-    p_set_meta: PROCESS(offload_rx_sosi, hdr_fields_out)
+    p_set_meta: PROCESS(offload_rx_sosi, hdr_fields_out, hdr_fields_raw)
     BEGIN
       decoded_sosi         <= offload_rx_sosi;
       decoded_sosi.sync    <=                sl(hdr_fields_out(field_hi(c_hdr_field_arr, "dp_sync"    ) DOWNTO field_lo(c_hdr_field_arr, "dp_sync"     )));
-      decoded_sosi.channel <= RESIZE_DP_CHANNEL(hdr_fields_out(field_hi(c_hdr_field_arr, "dp_channel" ) DOWNTO field_lo(c_hdr_field_arr, "dp_channel"  )));
-      decoded_sosi.bsn     <= RESIZE_DP_BSN(    hdr_fields_out(field_hi(c_hdr_field_arr, "dp_bsn"     ) DOWNTO field_lo(c_hdr_field_arr, "dp_bsn"      )));
+      decoded_sosi.bsn     <= RESIZE_DP_BSN(    hdr_fields_raw(field_hi(c_hdr_field_arr, "dp_bsn"     ) DOWNTO field_lo(c_hdr_field_arr, "dp_bsn"      )));
+      decoded_sosi.channel <= RESIZE_DP_CHANNEL(hdr_fields_raw(field_hi(c_hdr_field_arr, "dp_channel" ) DOWNTO field_lo(c_hdr_field_arr, "dp_channel"  )));
     END PROCESS;
 
     -- Validate bsn at sync 
@@ -196,20 +201,21 @@ BEGIN
 
     u_dp_demux : ENTITY dp_lib.dp_demux
     GENERIC MAP (
-      g_nof_output => g_nof_rx_monitors,
-      g_sel_ctrl_invert => TRUE
+      g_nof_output => g_nof_rx_monitors
     )
     PORT MAP (
       rst         => dp_rst,
       clk         => dp_clk,
       snk_in      => monitor_sosi,
-      src_out_arr => monitor_sosi_arr 
+      src_out_arr => demux_sosi_arr
     );
+    monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
 
     -- BSN Monitors
     u_mms_dp_bsn_monitor_v2 : ENTITY dp_lib.mms_dp_bsn_monitor_v2
     GENERIC MAP (
-      g_nof_streams => g_nof_rx_monitors
+      g_nof_streams => g_nof_rx_monitors,
+      g_sync_timeout => g_sync_timeout
     )
     PORT MAP (
       mm_rst      => mm_rst,
diff --git a/libraries/base/ring/src/vhdl/ring_tx.vhd b/libraries/base/ring/src/vhdl/ring_tx.vhd
index 659ba404b836b8bbea2b773ce55d1d5f298375e9..5a6d0d4510ee42fd025da27b013eeda256106dc1 100644
--- a/libraries/base/ring/src/vhdl/ring_tx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_tx.vhd
@@ -45,7 +45,8 @@ ENTITY ring_tx IS
     g_ring_pkt_type    : STD_LOGIC_VECTOR(c_halfword_w-1 DOWNTO 0) := c_ring_pkt_type_bf;
     g_validate_channel : BOOLEAN := TRUE;
     g_mode             : STRING  := ">";
-    g_nof_tx_monitors  : NATURAL := 1
+    g_nof_tx_monitors  : NATURAL := 1;
+    g_sync_timeout     : NATURAL := 200*10**6 
   );
   PORT (
     -- Clocks and reset
@@ -84,6 +85,7 @@ ARCHITECTURE str OF ring_tx IS
   SIGNAL tx_fifo_siso     : t_dp_siso;
   SIGNAL lane_tx_sosi     : t_dp_sosi;
   SIGNAL monitor_sosi     : t_dp_sosi;
+  SIGNAL demux_sosi_arr   : t_dp_sosi_arr(0 TO g_nof_tx_monitors-1); -- using 0 TO ... as that is the output of the demux
   SIGNAL monitor_sosi_arr : t_dp_sosi_arr(g_nof_tx_monitors-1 DOWNTO 0);
 
   SIGNAL hdr_fields_in     : STD_LOGIC_VECTOR(1023 DOWNTO 0);
@@ -206,12 +208,14 @@ BEGIN
       rst         => dp_rst,
       clk         => dp_clk,
       snk_in      => monitor_sosi,
-      src_out_arr => monitor_sosi_arr 
+      src_out_arr => demux_sosi_arr 
     );
+    monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
 
     u_mms_dp_bsn_monitor_v2 : ENTITY dp_lib.mms_dp_bsn_monitor_v2
     GENERIC MAP (
-      g_nof_streams => g_nof_tx_monitors
+      g_nof_streams => g_nof_tx_monitors,
+      g_sync_timeout => g_sync_timeout
     )
     PORT MAP (
       mm_rst      => mm_rst,