diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
index 56e232cc5220e64d7f5fb1c211e5db3c89ea8d5e..48f19d8f0da8b25abe9f0f1f63591777534c35c5 100755
--- a/libraries/technology/ip_arria10/fifo/README.txt
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -6,6 +6,7 @@ Contents:
2) Arria10 IP
3) Implementation options (LUTs or block RAM)
4) Synthesis trials
+5) Issues
1) FIFO components:
@@ -40,13 +41,11 @@ Contents:
The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
-
3) Implementation options (LUTs or block RAM)
- The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K), however this is not supported yet. This would imply
- adding a generic to set the appropriate parameter in the altera_mf.
+ The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K) via g_use_eab.
4) Synthesis trials
@@ -56,6 +55,7 @@ Contents:
in the file tab of the Quartus project navigator window.
Then check the resource usage in the synthesis and fitter reports.
+
5) Issues
No issues.
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/fifo/generate_ip.sh b/libraries/technology/ip_arria10/fifo/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7b86d6fd9cd1a61465e508f5ad3a24d98caff086
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/generate_ip.sh
@@ -0,0 +1,49 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Remark:
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+# The IP only needs to be generated if it need to be modified, because the ip_arria10_fifo_*.vhd directly instantiates
+# the FIFO altera_mf component.
+# The instantiation is copied manually from the generated/ip_arria10_ram_*/fifo_140/sim/ip_arria10_fifo_*.vhd.
+# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
+# it is not necessary to use the generated qip file.
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+qsys-generate ip_arria10_fifo_sc.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_fifo_dc.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_fifo_dc_mixed_widths.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
index b1afae234e983d30c3204d5a64a747905c9e9de7..eb026ef04f7b0b13e253be4c00d164a38b70ab44 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
@@ -1,224 +1,122 @@
--- megafunction wizard: %FIFO%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: dcfifo
-
--- ============================================================
--- File Name: ip_arria10_fifo_dc.vhd
--- Megafunction Name(s):
--- dcfifo
+-------------------------------------------------------------------------------
--
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_fifo_dc_fifo_140_c4o7vda.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-LIBRARY common_lib;
-USE common_lib.common_pkg.ALL;
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ip_arria10_fifo_dc IS
GENERIC (
- g_dat_w : NATURAL;
- g_nof_words : NATURAL
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
- PORT
- (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
END ip_arria10_fifo_dc;
ARCHITECTURE SYN OF ip_arria10_fifo_dc IS
- SIGNAL sub_wire0 : STD_LOGIC ;
- SIGNAL sub_wire1 : STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- SIGNAL sub_wire4 : STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
-
-
-
- COMPONENT dcfifo
- GENERIC (
- intended_device_family : STRING;
- lpm_numwords : NATURAL;
- lpm_showahead : STRING;
- lpm_type : STRING;
- lpm_width : NATURAL;
- lpm_widthu : NATURAL;
- overflow_checking : STRING;
- rdsync_delaypipe : NATURAL;
- underflow_checking : STRING;
- use_eab : STRING;
- write_aclr_synch : STRING;
- wrsync_delaypipe : NATURAL
- );
- PORT (
- wrclk : IN STD_LOGIC ;
- rdempty : OUT STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
- aclr : IN STD_LOGIC ;
- wrfull : OUT STD_LOGIC ;
- rdclk : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wrreq : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
+ COMPONENT dcfifo
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ read_aclr_synch : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC;
+ rdreq : IN STD_LOGIC;
+ wrclk : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
BEGIN
- rdempty <= sub_wire0;
- wrusedw <= sub_wire1(ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull <= sub_wire2;
- q <= sub_wire3(g_dat_w-1 DOWNTO 0);
- rdusedw <= sub_wire4(ceil_log2(g_nof_words)-1 DOWNTO 0);
-
- dcfifo_component : dcfifo
- GENERIC MAP (
- intended_device_family => "Stratix IV",
- lpm_numwords => g_nof_words,
- lpm_showahead => "OFF",
- lpm_type => "dcfifo",
- lpm_width => g_dat_w,
- lpm_widthu => ceil_log2(g_nof_words),
- overflow_checking => "ON",
- rdsync_delaypipe => 5,
- underflow_checking => "ON",
- use_eab => "ON",
- write_aclr_synch => "ON",
- wrsync_delaypipe => 5
- )
- PORT MAP (
- wrclk => wrclk,
- rdreq => rdreq,
- aclr => aclr,
- rdclk => rdclk,
- wrreq => wrreq,
- data => data,
- rdempty => sub_wire0,
- wrusedw => sub_wire1,
- wrfull => sub_wire2,
- q => sub_wire3,
- rdusedw => sub_wire4
- );
-
+ u_dcfifo : dcfifo
+ GENERIC MAP (
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => g_use_eab,
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
--- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "4"
--- Retrieval info: PRIVATE: Depth NUMERIC "256"
--- Retrieval info: PRIVATE: Empty NUMERIC "1"
--- Retrieval info: PRIVATE: Full NUMERIC "1"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
--- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
--- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: Optimize NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: UsedW NUMERIC "1"
--- Retrieval info: PRIVATE: Width NUMERIC "8"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
--- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
--- Retrieval info: PRIVATE: output_width NUMERIC "8"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
--- Retrieval info: PRIVATE: rsFull NUMERIC "0"
--- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
--- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
--- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
--- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "1"
--- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
--- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: USE_EAB STRING "ON"
--- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
--- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
--- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
--- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
--- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
--- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
--- Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
--- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
--- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
--- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
--- Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
--- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
--- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
--- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
--- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
--- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
--- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
--- Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
--- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
--- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
index 738cc51dd3a869281e305b3747f6ba0aae6273ff..d0fe04a7df04568435bc638c3023019e4326af80 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
@@ -1,231 +1,126 @@
--- megafunction wizard: %FIFO%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: dcfifo_mixed_widths
-
--- ============================================================
--- File Name: ip_arria10_fifo_dc_mixed_widths.vhd
--- Megafunction Name(s):
--- dcfifo_mixed_widths
+-------------------------------------------------------------------------------
--
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- 10.0 Build 218 06/27/2010 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_fifo_dc_mixed_widths_fifo_140_5csdcfa.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-LIBRARY common_lib;
-USE common_lib.common_pkg.ALL;
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ip_arria10_fifo_dc_mixed_widths IS
GENERIC (
- g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL;
- g_rddat_w : NATURAL
+ g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL := 20;
+ g_rddat_w : NATURAL := 10
);
- PORT
- (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
-END ip_arria10_ip_arria10_fifo_dc_mixed_widths;
-
-
-ARCHITECTURE SYN OF ip_arria10_ip_arria10_fifo_dc_mixed_widths IS
-
- SIGNAL sub_wire0 : STD_LOGIC ;
- SIGNAL sub_wire1 : STD_LOGIC_VECTOR (q'RANGE);
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC_VECTOR (wrusedw'RANGE);
- SIGNAL sub_wire4 : STD_LOGIC_VECTOR (rdusedw'RANGE);
-
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_fifo_dc_mixed_widths;
- COMPONENT dcfifo_mixed_widths
- GENERIC (
- intended_device_family : STRING;
- lpm_numwords : NATURAL;
- lpm_showahead : STRING;
- lpm_type : STRING;
- lpm_width : NATURAL;
- lpm_widthu : NATURAL;
- lpm_widthu_r : NATURAL;
- lpm_width_r : NATURAL;
- overflow_checking : STRING;
- rdsync_delaypipe : NATURAL;
- underflow_checking : STRING;
- use_eab : STRING;
- write_aclr_synch : STRING;
- wrsync_delaypipe : NATURAL
- );
- PORT (
- rdclk : IN STD_LOGIC ;
- wrfull : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (q'RANGE);
- rdempty : OUT STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (wrusedw'RANGE);
- aclr : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (data'RANGE);
- rdreq : IN STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (rdusedw'RANGE)
- );
- END COMPONENT;
+ARCHITECTURE SYN OF ip_arria10_fifo_dc_mixed_widths IS
+ COMPONENT dcfifo_mixed_widths
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ lpm_widthu_r : NATURAL;
+ lpm_width_r : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ read_aclr_synch : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (data'RANGE);
+ rdclk : IN STD_LOGIC;
+ rdreq : IN STD_LOGIC;
+ wrclk : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (q'RANGE);
+ rdempty : OUT STD_LOGIC;
+ rdusedw : OUT STD_LOGIC_VECTOR (rdusedw'RANGE);
+ wrfull : OUT STD_LOGIC;
+ wrusedw : OUT STD_LOGIC_VECTOR (wrusedw'RANGE)
+ );
+ END COMPONENT;
+
BEGIN
- wrfull <= sub_wire0;
- q <= sub_wire1(q'RANGE);
- rdempty <= sub_wire2;
- wrusedw <= sub_wire3(wrusedw'RANGE);
- rdusedw <= sub_wire4(rdusedw'RANGE);
-
- dcfifo_mixed_widths_component : dcfifo_mixed_widths
- GENERIC MAP (
- intended_device_family => "Stratix IV",
- lpm_numwords => g_nof_words,
- lpm_showahead => "OFF",
- lpm_type => "dcfifo",
- lpm_width => g_wrdat_w,
- lpm_widthu => ceil_log2(g_nof_words),
- lpm_widthu_r => ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),
- lpm_width_r => g_rddat_w,
- overflow_checking => "ON",
- rdsync_delaypipe => 5,
- underflow_checking => "ON",
- use_eab => "ON",
- write_aclr_synch => "ON",
- wrsync_delaypipe => 5
- )
- PORT MAP (
- rdclk => rdclk,
- wrclk => wrclk,
- wrreq => wrreq,
- aclr => aclr,
- data => data,
- rdreq => rdreq,
- wrfull => sub_wire0,
- q => sub_wire1,
- rdempty => sub_wire2,
- wrusedw => sub_wire3,
- rdusedw => sub_wire4
- );
-
+ dcfifo_mixed_widths_component : dcfifo_mixed_widths
+ GENERIC MAP (
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo_mixed_widths",
+ lpm_width => g_wrdat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ lpm_widthu_r => tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),
+ lpm_width_r => g_rddat_w,
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => "ON",
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
--- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "4"
--- Retrieval info: PRIVATE: Depth NUMERIC "256"
--- Retrieval info: PRIVATE: Empty NUMERIC "1"
--- Retrieval info: PRIVATE: Full NUMERIC "1"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
--- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
--- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: Optimize NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: UsedW NUMERIC "1"
--- Retrieval info: PRIVATE: Width NUMERIC "8"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
--- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
--- Retrieval info: PRIVATE: output_width NUMERIC "16"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
--- Retrieval info: PRIVATE: rsFull NUMERIC "0"
--- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
--- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
--- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
--- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "1"
--- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "7"
--- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
--- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: USE_EAB STRING "ON"
--- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
--- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
--- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
--- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
--- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
--- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
--- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
--- Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL "rdusedw[6..0]"
--- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
--- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
--- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
--- Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
--- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
--- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
--- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
--- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
--- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
--- Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
--- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
--- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths_waveforms.html FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
index 24ab13fa7f631e8e0245445ac5fc8c2c9bf8d28e..3e0fa117d153290575779017e5a465ec8a4be1a2 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
@@ -1,43 +1,33 @@
--- megafunction wizard: %FIFO%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: scfifo
-
--- ============================================================
--- File Name: ip_arria10_fifo_sc.vhd
--- Megafunction Name(s):
--- scfifo
+-------------------------------------------------------------------------------
--
--- Simulation Library Files(s):
---
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2011 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_fifo_sc_fifo_140_pkqwcbi.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-LIBRARY common_lib;
-USE common_lib.common_pkg.ALL;
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
@@ -45,162 +35,76 @@ USE altera_mf.all;
ENTITY ip_arria10_fifo_sc IS
GENERIC (
g_use_eab : STRING := "ON";
- g_dat_w : NATURAL;
- g_nof_words : NATURAL
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
- PORT
- (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
- usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
END ip_arria10_fifo_sc;
ARCHITECTURE SYN OF ip_arria10_fifo_sc IS
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (usedw'RANGE);
- SIGNAL sub_wire1 : STD_LOGIC ;
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC_VECTOR (data'RANGE);
-
-
-
- COMPONENT scfifo
- GENERIC (
- add_ram_output_register : STRING;
- intended_device_family : STRING;
- lpm_numwords : NATURAL;
- lpm_showahead : STRING;
- lpm_type : STRING;
- lpm_width : NATURAL;
- lpm_widthu : NATURAL;
- overflow_checking : STRING;
- underflow_checking : STRING;
- use_eab : STRING
- );
- PORT (
- clock : IN STD_LOGIC ;
- usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wrreq : IN STD_LOGIC ;
- aclr : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC
- );
- END COMPONENT;
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ clock : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ empty : OUT STD_LOGIC;
+ full : OUT STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
BEGIN
- usedw <= sub_wire0;
- empty <= sub_wire1;
- full <= sub_wire2;
- q <= sub_wire3;
-
- scfifo_component : scfifo
- GENERIC MAP (
- add_ram_output_register => "ON",
- intended_device_family => "Stratix IV",
- lpm_numwords => g_nof_words,
- lpm_showahead => "OFF",
- lpm_type => "scfifo",
- lpm_width => g_dat_w,
- lpm_widthu => ceil_log2(g_nof_words),
- overflow_checking => "ON",
- underflow_checking => "ON",
- use_eab => g_use_eab
- )
- PORT MAP (
- clock => clock,
- wrreq => wrreq,
- aclr => aclr,
- data => data,
- rdreq => rdreq,
- usedw => sub_wire0,
- empty => sub_wire1,
- full => sub_wire2,
- q => sub_wire3
- );
-
+ u_scfifo : scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "scfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => g_use_eab
+ )
+ PORT MAP (
+ aclr => aclr,
+ clock => clock,
+ data => data,
+ rdreq => rdreq,
+ wrreq => wrreq,
+ empty => empty,
+ full => full,
+ q => q,
+ usedw => usedw
+ );
END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
--- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
--- Retrieval info: PRIVATE: Clock NUMERIC "0"
--- Retrieval info: PRIVATE: Depth NUMERIC "256"
--- Retrieval info: PRIVATE: Empty NUMERIC "1"
--- Retrieval info: PRIVATE: Full NUMERIC "1"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
--- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
--- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: Optimize NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: UsedW NUMERIC "1"
--- Retrieval info: PRIVATE: Width NUMERIC "8"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
--- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
--- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
--- Retrieval info: PRIVATE: output_width NUMERIC "8"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
--- Retrieval info: PRIVATE: rsFull NUMERIC "0"
--- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
--- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
--- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "1"
--- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
--- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: USE_EAB STRING "ON"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
--- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
--- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
--- Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
--- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
--- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
--- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
--- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
--- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
--- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc_wave*.jpg FALSE
diff --git a/libraries/technology/ip_arria10/fifo/quartus/fifo.qpf b/libraries/technology/ip_arria10/fifo/quartus/fifo.qpf
new file mode 100644
index 0000000000000000000000000000000000000000..5d771ab1b47c6dd5ebad50fc38872d3264e8b336
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/quartus/fifo.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0a10.1 Build 374 09/02/2014 SJ Full Version
+# Date created = 16:40:16 October 27, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "16:40:16 October 27, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "fifo"
diff --git a/libraries/technology/ip_arria10/fifo/quartus/fifo.qsf b/libraries/technology/ip_arria10/fifo/quartus/fifo.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..bfd88322ddd787ec2429bc4029532a49f400b16f
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/quartus/fifo.qsf
@@ -0,0 +1,57 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0a10.1 Build 374 09/02/2014 SJ Full Version
+# Date created = 16:40:16 October 27, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# fifo_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115R2F40I2LG
+set_global_assignment -name TOP_LEVEL_ENTITY ip_arria10_fifo_sc
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:16 OCTOBER 27, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name VHDL_FILE ../../../technology_pkg.vhd
+set_global_assignment -name VHDL_FILE ../ip_arria10_fifo_sc.vhd
+set_global_assignment -name VHDL_FILE ../ip_arria10_fifo_dc_mixed_widths.vhd
+set_global_assignment -name VHDL_FILE ../ip_arria10_fifo_dc.vhd
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file