diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
index 90c46979d6602c61b389a579faee4f2df82e8ff2..577051cd04ca496483104ac833348cdca94c10c4 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
@@ -88,22 +88,7 @@ set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
 # - hover over the ATX PLL block (left side or right side)
 # - Right click and click "Copy tooltip"
 # - Paste text in here and edit
-#
-#set_location_assignment HSSIPMALCPLL_X0_Y88_N29 -to |unb2_test_10GbE|unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g
-#set_location_assignment FPLL_X0_Y120_N26 -to |unb2_test_10GbE|unb2_test:u_revision|ctrl_unb2_board:u_ctrl|unb2_board_clk200_pll:\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|tech_fractional_pll_clk200:\gen_st_fractional_pll:u_st_fractional_pll|ip_arria10_fractional_pll_clk200:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
-#set_location_assignment FPLL_X0_Y143_N26 -to |unb2_test_10GbE|unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tech_pll_xgmii_mac_clocks:u_unb2_board_clk644_pll|ip_arria10_pll_xgmii_mac_clocks:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
-
-#set_location_assignment HSSIPMALCPLL_X0_Y88_N29 -to \\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g
-#wrong set_location_assignment HSSIPMALCPLL_X0_Y65_N29 -to \\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g
-#set_location_assignment FPLL_X0_Y120_N26 -to \\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|tech_fractional_pll_clk200:\gen_st_fractional_pll:u_st_fractional_pll|ip_arria10_fractional_pll_clk200:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
-#set_location_assignment FPLL_X0_Y143_N26 -to \\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tech_pll_xgmii_mac_clocks:u_unb2_board_clk644_pll|ip_arria10_pll_xgmii_mac_clocks:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
-#
-#set_location_assignment HSSIPMALCPLL_X0_Y65_N29 -to "\|unb2_test_10GbE|unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g"
-
-
-#set_location_assignment LCPLL_X0_Y33_N57 -to "test_phy:phy|altera_xcvr_native_sv:test_phy_inst|sv_xcvr_plls:gen_native_inst.xcvr_native_insts[0].gen_bonded_group_plls.gen_tx_plls.tx_plls|pll[0].pll.atx_pll.tx_pll"
-
-set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"
+#set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"