diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd index 21e3d6b6bea8082e8a62c8def74b0e6feb418ac4..39cd81d6ccdabd6b821cfce7af4618b5b8aa6809 100644 --- a/libraries/base/diag/src/vhdl/diag_pkg.vhd +++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd @@ -163,7 +163,7 @@ PACKAGE diag_pkg IS -- CNTR / PSRG sequence test data ----------------------------------------------------------------------------- - CONSTANT c_diag_seq_tx_reg_nof_dat : NATURAL := 3; + CONSTANT c_diag_seq_tx_reg_nof_dat : NATURAL := 4; CONSTANT c_diag_seq_tx_reg_adr_w : NATURAL := ceil_log2(c_diag_seq_tx_reg_nof_dat); CONSTANT c_diag_seq_rx_reg_nof_steps_wi : NATURAL := 4; CONSTANT c_diag_seq_rx_reg_nof_steps : NATURAL := 4; @@ -172,11 +172,14 @@ PACKAGE diag_pkg IS -- Record with all diag seq MM register fields TYPE t_diag_seq_mm_reg IS RECORD - tx_init : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); -- readback ctrl + -- readback control + tx_init : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); + tx_mod : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); tx_ctrl : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); rx_ctrl : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); rx_steps : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0); - tx_cnt : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); -- read cnt and stat + -- read only status + tx_cnt : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); rx_cnt : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); rx_stat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); rx_sample : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0); diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd index 42c193ec90fe81b7cde66ffa4787a91185afb0a7..cc1793271e534869edf9353cc67c8d5479cac2ad 100644 --- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd +++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd @@ -54,6 +54,7 @@ PACKAGE tb_diag_pkg IS PROCEDURE proc_diag_seq_tx_enable(CONSTANT c_stream : IN NATURAL; CONSTANT c_pattern : IN STRING; -- "PSRG", "CNTR" CONSTANT c_tx_init : IN NATURAL; + CONSTANT c_tx_mod : IN NATURAL; SIGNAL mm_clk : IN STD_LOGIC; SIGNAL dp_clk : IN STD_LOGIC; SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl @@ -130,6 +131,10 @@ PACKAGE BODY tb_diag_pkg IS proc_mem_mm_bus_rd(c_tx_offset + 1, mm_clk, tx_miso, tx_mosi); proc_mem_mm_bus_rd_latency(1, mm_clk); rd_reg.tx_init <= tx_miso.rddata(c_word_w-1 DOWNTO 0); + -- . read back Tx data modulo + proc_mem_mm_bus_rd(c_tx_offset + 3, mm_clk, tx_miso, tx_mosi); + proc_mem_mm_bus_rd_latency(1, mm_clk); + rd_reg.tx_mod <= tx_miso.rddata(c_word_w-1 DOWNTO 0); -- . read back Tx control proc_mem_mm_bus_rd(c_tx_offset + 0, mm_clk, tx_miso, tx_mosi); proc_mem_mm_bus_rd_latency(1, mm_clk); @@ -172,6 +177,7 @@ PACKAGE BODY tb_diag_pkg IS PROCEDURE proc_diag_seq_tx_enable(CONSTANT c_stream : IN NATURAL; CONSTANT c_pattern : IN STRING; -- "PSRG", "CNTR" CONSTANT c_tx_init : IN NATURAL; + CONSTANT c_tx_mod : IN NATURAL; SIGNAL mm_clk : IN STD_LOGIC; SIGNAL dp_clk : IN STD_LOGIC; SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl @@ -193,6 +199,7 @@ PACKAGE BODY tb_diag_pkg IS -- Enable Tx proc_mem_mm_bus_wr(c_tx_offset + 0, v_ctlr, mm_clk, tx_miso, tx_mosi); proc_mem_mm_bus_wr(c_tx_offset + 1, c_tx_init, mm_clk, tx_miso, tx_mosi); + proc_mem_mm_bus_wr(c_tx_offset + 3, c_tx_mod, mm_clk, tx_miso, tx_mosi); proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg); END proc_diag_seq_tx_enable;