diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index 0c5cfb57f97114126f356222a32abd9d9f34f2ba..0c4ce6f94ca7807fb3e5ce862cdc3210ba3efa8d 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -35,12 +35,13 @@ test_bench_files =
tb/vhdl/tb_tb_reorder_col.vhd
tb/vhdl/tb_reorder_col_wide.vhd
tb/vhdl/tb_reorder_col_wide_row_select.vhd
+ tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
tb/vhdl/tb_mmf_reorder_matrix.vhd
tb/vhdl/tb_mmf_reorder_row.vhd
tb/vhdl/tb_mms_reorder_rewire.vhd
regression_test_vhdl =
- tb/vhdl/tb_reorder_col_wide_row_select.vhd
+ tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
# tb/vhdl/tb_tb_reorder_col.vhd -- fails in unb2c
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
index 0c473d217b9614df7d6588373c4445fc363e6387..d8ee5f2dae9b9014c7af442272322ea5f49bf2e8 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
-- Author : R vd Walle
--- Purpose: Reorder packet
+-- Purpose: Reorder block of data in time
-- Description:
-- Select g_nof_ch_sel complex samples from an input block of g_nof_ch_in
-- complex samples. The subband select map is arbitrary (any order and also
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
index 53accf74f748070b8bffbe24cf61f596432a92ac..ff0cdce5cab6ef2cb9056e611c3b4063eb00621c 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
@@ -23,9 +23,7 @@
-- Purpose: Select and/or reorder data on multiple streams.
--
-- Description:
--- Reorder-col unit that handles a stream that consists of
--- multiple (g_nof_inputs) input streams.
---
+-- Array of reorder_col_select instances
--
-- Remarks:
--
@@ -74,8 +72,8 @@ BEGIN
---------------------------------------------------------------
-- INSTANTIATE MULTIPLE SINGLE CHANNEL SUBBAND SELECT UNITS
---------------------------------------------------------------
- gen_ss_singles : FOR I IN 0 TO g_nof_inputs-1 GENERATE
- u_single_ss : ENTITY work.reorder_col_select
+ gen_nof_input : FOR I IN 0 TO g_nof_inputs-1 GENERATE
+ u_reorder_col_select : ENTITY work.reorder_col_select
GENERIC MAP (
g_technology => g_technology,
g_dsp_data_w => g_dsp_data_w,
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index 478eb96db607a8eeaa5627264d6886ad1c83dee2..b2c8ebf64687c8f32e4c1e4b7267bd5939e7b4b6 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -29,7 +29,7 @@
-- for a single clock cylce.
--
-- Remarks:
--- in_select has to be defined 1 clock cycle after the in_sosi data.
+-- in_select always has to be defined on the same clock cycle as the in_sosi data.
LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -62,7 +62,7 @@ END reorder_row_select;
ARCHITECTURE str OF reorder_row_select IS
- CONSTANT c_tot_pipeline : NATURAL := g_pipeline_in + g_pipeline_in_m + g_pipeline_out + 1; --+1 for regs process
+ CONSTANT c_tot_pipeline : NATURAL := g_pipeline_in + g_pipeline_in_m + g_pipeline_out;
CONSTANT c_data_w : NATURAL := g_dsp_data_w*c_nof_complex;
TYPE t_dp_sosi_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
@@ -87,8 +87,8 @@ BEGIN
-- selection buffer.
---------------------------------------------------------------
gen_input : FOR I IN g_nof_inputs-1 DOWNTO 0 GENERATE
- reorder_in_dat((I+1)*c_data_w-1 DOWNTO I*c_data_w) <= r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w-1 DOWNTO 0) &
- r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w-1 DOWNTO 0);
+ reorder_in_dat((I+1)*c_data_w-1 DOWNTO I*c_data_w) <= input_sosi_arr(I).im(g_dsp_data_w-1 DOWNTO 0) &
+ input_sosi_arr(I).re(g_dsp_data_w-1 DOWNTO 0);
END GENERATE;
---------------------------------------------------------------
@@ -123,7 +123,7 @@ BEGIN
-- Also the data-output of the select_m_symbols block is merged
-- here with the rest of the pipelined SOSI signals.
---------------------------------------------------------------
- comb : PROCESS(r, input_sosi_arr, reorder_out_dat)
+ comb : PROCESS(r, input_sosi_arr, reorder_out_dat)
VARIABLE v : reg_type;
BEGIN
v := r;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
index 847aea42e6d1ad4d7d992abf2d0acf18c35b9bb9..db63122e71dbd21b911c3b2d160fb819505d1629 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
@@ -20,12 +20,46 @@
-------------------------------------------------------------------------------
-- Author : R vd Walle
+-- Purpose: Verify reorder_col_wide select and reorder_row_select.
-- Usage:
-- > as 10
-- > run -all
--- . Observe in_sosi_arr and out_sosi_arr in the Wave window
+-- * The tb is self stopping and self checking,tb_end will stop the simulation by
+-- stopping the clk and thus all toggling.
--
--- Description:
+-- Description: The tb generates counter data for all g_nof_inputs packetized according
+-- to g_nof_sync, g_nof_block_per_sync and g_nof_ch_in. Each input stream then passes through
+-- reorder_col_wide_select where each stream is reordered according to g_nof_ch_sel_col,
+-- g_ch_sel_offsets and g_ch_sel_step. Those streams then enter reorder_row_select. Each output
+-- is created by selecting one input at the time based on in_select, this tb always selects the next input (row)
+-- in ascending order after g_nof_ch_sel_col elements. Each output has the same selection in this tb.
+-- The tb verifies the functionality by generating an expected sosi array and comparing it with the output.
+-- The signals verified are sop, eop, valid, sync, re, and im.
+-- The example below shows what the expected outputs are based on the default TB generics and the following input.
+-- The 6 rows in the table represent the c_nof_inputs = 6 input streams. (A,B), (C,D), etc. represent the
+-- g_nof_ch_sel_col = 2 nof sequential collums to select per row.
+--
+-- Input:
+-- | 0| 1| 2| 3| ...| 32| 33| ...|1022|1023|
+-- -+-----------------------------------------
+-- 0|A0|B0|A1|B1| ...|A16|B16| ...|A511|B511|
+-- -|--+--+--+--+----+---+---+----+----+----+
+-- 1|C0|D0|C1|D1| ...|C16|D16| ...|C511|D511|
+-- -|--+--+--+--+----+---+---+----+----+----+
+-- 2|E0|F0|E1|F1| ...|E16|F16| ...|E511|F511|
+-- -|--+--+--+--+----+---+---+----+----+----+
+-- 3|G0|H0|G1|H1| ...|G16|H16| ...|G511|H511|
+-- -|--+--+--+--+----+---+---+----+----+----+
+-- 4|I0|J0|I1|J1| ...|I16|J16| ...|I511|J511|
+-- -|--+--+--+--+----+---+---+----+----+----+
+-- 5|K0|L0|K1|L1| ...|K16|L16| ...|K511|L511|
+--
+-- Expected output for each of the g_nof_outputs = 2 output streams in the first sync intercal. You can see that
+-- all "0" and all "16" elements are selected from the inputs which is configured by g_ch_sel_offset = (0, 16).
+-- The next sync intervals, the offset selection will be (0+i*k, 16+i*k) where i is the sync interval and k is
+-- g_ch_sel_step = 3.
+-- |A0 B0 C0 D0 E0 F0 G0 H0 I0 J0 K0 L0 A16 B16 C16 D16 E16 F16 G16 H16 I16 J16 K16 L16|
+
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
@@ -37,32 +71,36 @@ USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
ENTITY tb_reorder_col_wide_row_select IS
+ GENERIC(
+ g_nof_inputs : NATURAL := 6; -- also nof rows
+ g_nof_outputs : NATURAL := 2;
+ g_dsp_data_w : NATURAL := 16;
+ g_nof_sync : NATURAL := 5;
+ g_nof_block_per_sync : NATURAL := 4;
+ g_nof_ch_in : NATURAL := 1024; -- nof input words per block, identical for all input streams.
+ g_nof_ch_sel_col : NATURAL := 2; -- nof of sequential collums to select per row.
+ g_nof_ch_sel_offset : NATURAL := 2; -- nof offsets defined
+ g_ch_sel_offsets : t_natural_arr := (0, 16);
+ g_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval
+ g_reorder_row_select_pipe_in : NATURAL := 1;
+ g_reorder_row_select_pipe_in_m : NATURAL := 1;
+ g_reorder_row_select_pipe_out : NATURAL := 1
+ );
END tb_reorder_col_wide_row_select;
ARCHITECTURE tb OF tb_reorder_col_wide_row_select IS
- CONSTANT c_clk_period : TIME := 10 ns;
+ CONSTANT c_clk_period : TIME := 10 ns;
CONSTANT c_rl : NATURAL := 1;
- CONSTANT c_dsp_data_w : NATURAL := 16;
-
- CONSTANT c_nof_sync : NATURAL := 5;
-
- CONSTANT c_nof_inputs : NATURAL := 6;
- CONSTANT c_nof_outputs : NATURAL := 2;
- CONSTANT c_nof_ch_in : NATURAL := 1024;
- CONSTANT c_nof_ch_sel_row : NATURAL := c_nof_inputs;
- CONSTANT c_nof_ch_sel_col : NATURAL := 2;
- CONSTANT c_nof_ch_sel_offset : NATURAL := 2;
- CONSTANT c_ch_sel_offsets : t_natural_arr(0 TO c_nof_ch_sel_offset-1) := (0, 16);
- CONSTANT c_ch_sel_step : NATURAL := 3;
- CONSTANT c_nof_ch_sel : NATURAL := c_nof_ch_sel_offset*c_nof_ch_sel_col*c_nof_ch_sel_row;
- CONSTANT c_nof_block_per_sync : NATURAL := 4;
- CONSTANT c_nof_inputs_w : NATURAL := ceil_log2(c_nof_inputs);
- CONSTANT c_in_select_w : NATURAL := c_nof_outputs*c_nof_inputs_w;
- CONSTANT c_in_select_dly : NATURAL := 2;
-
+ CONSTANT c_nof_ch_sel_row : NATURAL := g_nof_inputs;
+ CONSTANT c_nof_ch_sel : NATURAL := g_nof_ch_sel_offset*g_nof_ch_sel_col*c_nof_ch_sel_row;
+ CONSTANT c_nof_inputs_w : NATURAL := ceil_log2(g_nof_inputs);
+ CONSTANT c_in_select_w : NATURAL := g_nof_outputs*c_nof_inputs_w;
+ CONSTANT c_in_select_dly : NATURAL := 1;
+ CONSTANT c_ch_sel_offsets : t_natural_arr(0 TO g_nof_ch_sel_offset-1) := g_ch_sel_offsets;
+
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL tb_end : STD_LOGIC;
@@ -71,19 +109,19 @@ ARCHITECTURE tb OF tb_reorder_col_wide_row_select IS
SIGNAL mm_miso : t_mem_miso;
SIGNAL st_en : STD_LOGIC := '1';
- SIGNAL st_siso_arr : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- SIGNAL st_sosi_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL exp_sosi_arr : t_dp_sosi_arr(c_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL exp_siso_arr : t_dp_siso_arr(c_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL st_siso_arr : t_dp_siso_arr(g_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL st_sosi_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL exp_sosi_arr : t_dp_sosi_arr(g_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL exp_siso_arr : t_dp_siso_arr(g_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL bsn : NATURAL := 10;
- SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- SIGNAL col_wide_select_sosi_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
- SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_outputs-1 DOWNTO 0);
- SIGNAL dly_out_sosi_arr : t_dp_sosi_arr(c_nof_outputs-1 DOWNTO 0);
+ SIGNAL out_siso_arr : t_dp_siso_arr(g_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL col_wide_select_sosi_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(g_nof_outputs-1 DOWNTO 0);
+ SIGNAL dly_out_sosi_arr : t_dp_sosi_arr(g_nof_outputs-1 DOWNTO 0);
SIGNAL reorder_row_in_select : STD_LOGIC_VECTOR(c_in_select_w-1 DOWNTO 0);
SIGNAL in_select : STD_LOGIC_VECTOR(c_in_select_w-1 DOWNTO 0);
@@ -93,18 +131,17 @@ BEGIN
clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
rst <= '1', '0' AFTER c_clk_period*7;
- -- MM domain
- p_mm_stimuli : PROCESS
+ p_select_stimuli : PROCESS
VARIABLE k : NATURAL;
BEGIN
- FOR rep IN 0 TO c_nof_sync*c_nof_block_per_sync-1 LOOP
- k := c_nof_ch_sel_col * (rep/c_nof_block_per_sync) * c_ch_sel_step;
+ FOR rep IN 0 TO g_nof_sync*g_nof_block_per_sync-1 LOOP
+ k := g_nof_ch_sel_col * (rep/g_nof_block_per_sync) * g_ch_sel_step;
mm_mosi <= c_mem_mosi_rst;
proc_common_wait_until_low(clk, mm_miso.waitrequest);
- FOR I IN 0 TO c_nof_ch_sel_offset-1 LOOP
+ FOR I IN 0 TO g_nof_ch_sel_offset-1 LOOP
FOR row IN 0 TO c_nof_ch_sel_row-1 LOOP
- FOR col IN 0 TO c_nof_ch_sel_col-1 LOOP
- FOR i_out IN 0 TO c_nof_outputs-1 LOOP
+ FOR col IN 0 TO g_nof_ch_sel_col-1 LOOP
+ FOR i_out IN 0 TO g_nof_outputs-1 LOOP
reorder_row_in_select((i_out+1)* c_nof_inputs_w -1 DOWNTO i_out * c_nof_inputs_w) <= TO_UVEC(row, c_nof_inputs_w);
END LOOP;
proc_mem_mm_bus_rd(c_ch_sel_offsets(I)+col+k, clk, mm_mosi);
@@ -130,7 +167,7 @@ BEGIN
------------------------------------------------------------------------------
-- Data blocks
------------------------------------------------------------------------------
- gen_stimuli : FOR K IN 0 TO c_nof_inputs-1 GENERATE
+ gen_stimuli : FOR K IN 0 TO g_nof_inputs-1 GENERATE
p_st_stimuli : PROCESS
VARIABLE v_re : NATURAL := 0+k*2**5;
VARIABLE v_im : NATURAL := 1+k*2**5;
@@ -141,17 +178,18 @@ BEGIN
-- Run some sync intervals with DSP counter data for the real and imag fields
WAIT UNTIL rising_edge(clk);
- FOR I IN 0 TO c_nof_sync-1 LOOP
- proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
- v_re := v_re + c_nof_ch_in;
- v_im := v_im + c_nof_ch_in;
- FOR J IN 0 TO c_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
- v_re := v_re + c_nof_ch_in;
- v_im := v_im + c_nof_ch_in;
+ FOR I IN 0 TO g_nof_sync-1 LOOP
+ proc_dp_gen_block_data(c_rl, FALSE, g_dsp_data_w, g_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
+ v_re := v_re + g_nof_ch_in;
+ v_im := v_im + g_nof_ch_in;
+ FOR J IN 0 TO g_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference
+ proc_dp_gen_block_data(c_rl, FALSE, g_dsp_data_w, g_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
+ v_re := v_re + g_nof_ch_in;
+ v_im := v_im + g_nof_ch_in;
END LOOP;
END LOOP;
st_sosi_arr(K) <= c_dp_sosi_rst;
+ proc_common_wait_some_cycles(clk, g_nof_ch_in);
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
WAIT;
@@ -164,7 +202,7 @@ BEGIN
-- Add BSN to the ST data
p_in_sosi : PROCESS(st_sosi_arr, bsn)
BEGIN
- FOR I IN 0 TO c_nof_inputs-1 LOOP
+ FOR I IN 0 TO g_nof_inputs-1 LOOP
in_sosi_arr(I) <= st_sosi_arr(I);
in_sosi_arr(I).bsn <= TO_DP_BSN(bsn);
END LOOP;
@@ -173,10 +211,9 @@ BEGIN
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
-
u_pipeline_arr : ENTITY dp_lib.dp_pipeline_arr
GENERIC MAP (
- g_nof_streams => c_nof_outputs
+ g_nof_streams => g_nof_outputs
)
PORT MAP (
rst => rst,
@@ -186,7 +223,7 @@ BEGIN
src_out_arr => dly_out_sosi_arr
);
- gen_verify : FOR O IN 0 TO c_nof_outputs-1 GENERATE
+ gen_verify : FOR O IN 0 TO g_nof_outputs-1 GENERATE
p_generate_exp_data : PROCESS
VARIABLE v_col : NATURAL := 0;
VARIABLE v_row : NATURAL := 0;
@@ -194,31 +231,32 @@ BEGIN
VARIABLE v_sync_ix : NATURAL := 0;
VARIABLE v_k : NATURAL := 0;
BEGIN
- FOR I IN 0 TO c_nof_sync*c_nof_block_per_sync-1 LOOP
+ FOR I IN 0 TO g_nof_sync*g_nof_block_per_sync-1 LOOP
exp_sosi_arr(O) <= c_dp_sosi_rst;
proc_common_wait_until_high(clk, out_sosi_arr(0).sop);
FOR J IN 0 TO c_nof_ch_sel-1 LOOP
- v_sync_ix := I / c_nof_block_per_sync;
- v_offset := J / (c_nof_ch_sel_col*c_nof_ch_sel_row);
- v_col := J MOD c_nof_ch_sel_col;
- v_row := (J/c_nof_ch_sel_col) MOD c_nof_ch_sel_row;
- v_k := c_nof_ch_sel_col * v_sync_ix * c_ch_sel_step;
+ v_sync_ix := I / g_nof_block_per_sync;
+ v_offset := J / (g_nof_ch_sel_col*c_nof_ch_sel_row);
+ v_col := J MOD g_nof_ch_sel_col;
+ v_row := (J/g_nof_ch_sel_col) MOD c_nof_ch_sel_row;
+ v_k := g_nof_ch_sel_col * v_sync_ix * g_ch_sel_step;
exp_sosi_arr(O) <= c_dp_sosi_rst;
exp_sosi_arr(O).valid <= '1';
IF J = 0 THEN
exp_sosi_arr(O).sop <= '1';
- IF I MOD c_nof_block_per_sync = 0 THEN
+ IF I MOD g_nof_block_per_sync = 0 THEN
exp_sosi_arr(O).sync <= '1';
END IF;
ELSIF j = c_nof_ch_sel-1 THEN
exp_sosi_arr(O).eop <= '1';
END IF;
- exp_sosi_arr(O).re <= TO_DP_DSP_DATA( I * c_nof_ch_in + v_k + c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
- exp_sosi_arr(O).im <= TO_DP_DSP_DATA(1+ I * c_nof_ch_in + v_k + c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ exp_sosi_arr(O).re <= TO_DP_DSP_DATA( I * g_nof_ch_in + v_k + c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ exp_sosi_arr(O).im <= TO_DP_DSP_DATA(1+ I * g_nof_ch_in + v_k + c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
proc_common_wait_some_cycles(clk, 1);
END LOOP;
+ exp_sosi_arr(O) <= c_dp_sosi_rst;
END LOOP;
WAIT;
END PROCESS;
@@ -241,9 +279,9 @@ BEGIN
u_dut_col : ENTITY work.reorder_col_wide_select
GENERIC MAP (
- g_nof_inputs => c_nof_inputs,
- g_dsp_data_w => c_dsp_data_w,
- g_nof_ch_in => c_nof_ch_in,
+ g_nof_inputs => g_nof_inputs,
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_ch_in => g_nof_ch_in,
g_nof_ch_sel => c_nof_ch_sel
)
PORT MAP (
@@ -262,9 +300,12 @@ BEGIN
u_dut_row : ENTITY work.reorder_row_select
GENERIC MAP (
- g_dsp_data_w => c_dsp_data_w,
- g_nof_inputs => c_nof_inputs,
- g_nof_outputs => c_nof_outputs
+ g_dsp_data_w => g_dsp_data_w,
+ g_nof_inputs => g_nof_inputs,
+ g_nof_outputs => g_nof_outputs,
+ g_pipeline_in => g_reorder_row_select_pipe_in,
+ g_pipeline_in_m => g_reorder_row_select_pipe_in_m,
+ g_pipeline_out => g_reorder_row_select_pipe_out
)
PORT MAP (
dp_rst => rst,
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4e499c8e96678ff5ada789594f588ac1ffb2cd43
--- /dev/null
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
@@ -0,0 +1,63 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Test multiple instances of tb_reorder_col_wide_row_select
+-- Usage:
+-- > as 10
+-- > run -all
+--
+-- Description: See tb_reorder_col_wide_row_select
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_reorder_col_wide_row_select IS
+END tb_tb_reorder_col_wide_row_select;
+
+ARCHITECTURE tb OF tb_tb_reorder_col_wide_row_select IS
+
+ CONSTANT c_nof_sync : NATURAL := 3;
+ CONSTANT c_dsp_data_w : NATURAL := 16;
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
+BEGIN
+
+ -- Generics:
+ -- g_nof_inputs : NATURAL := 6; -- also nof rows
+ -- g_nof_outputs : NATURAL := 2;
+ -- g_dsp_data_w : NATURAL := 16;
+ -- g_nof_sync : NATURAL := 5;
+ -- g_nof_block_per_sync : NATURAL := 4;
+ -- g_nof_ch_in : NATURAL := 1024; -- nof input words per block, identical for all input streams.
+ -- g_nof_ch_sel_col : NATURAL := 2; -- nof of sequential collums to select per row.
+ -- g_nof_ch_sel_offset : NATURAL := 2; -- nof offsets defined
+ -- g_ch_sel_offsets : t_natural_arr := (0, 16);
+ -- g_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval
+ -- g_reorder_row_select_pipe_in : NATURAL := 1;
+ -- g_reorder_row_select_pipe_in_m : NATURAL := 1;
+ -- g_reorder_row_select_pipe_out : NATURAL := 1
+
+ u_sdp : ENTITY work.tb_reorder_col_wide_row_select GENERIC MAP (6, 1, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
+ u_max_out : ENTITY work.tb_reorder_col_wide_row_select GENERIC MAP (8, 1, c_dsp_data_w, c_nof_sync, 1, 512, 8, 8, (0 ,64, 128, 192, 256, 320, 384, 448), 0, 0, 1, 1); -- rows * cols * offsets = 8*8*8 = 512
+ u_multiple_out : ENTITY work.tb_reorder_col_wide_row_select GENERIC MAP (2, 5, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
+
+END tb;