diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index 06f6836d6792ddd01a48feaa9607f51346dcfa22..cd704a27386792c8c272453232a1d58e996f5ce3 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -57,9 +57,10 @@ ENTITY common_requantize IS
g_lsb_w : INTEGER := 4; -- when > 0, number of LSbits to remove from in_dat
-- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
-- when 0 then no effect
- g_lsb_round : BOOLEAN := TRUE; -- when true ROUND else TRUNCATE the input LSbits
- g_lsb_round_clip : BOOLEAN := FALSE; -- when true round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
- g_msb_clip : BOOLEAN := TRUE; -- when true CLIP else WRAP the input MSbits
+ g_lsb_round : BOOLEAN := TRUE; -- when TRUE round else truncate the input LSbits
+ g_lsb_round_clip : BOOLEAN := FALSE; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
+ g_lsb_round_even : BOOLEAN := FALSE; -- when TRUE round to even, else round away from zero
+ g_msb_clip : BOOLEAN := TRUE; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : BOOLEAN := FALSE; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : NATURAL := 0; -- do not use, must be 0, use negative g_lsb_w instead
@@ -101,6 +102,7 @@ BEGIN
g_representation => g_representation,
g_round => g_lsb_round,
g_round_clip => g_lsb_round_clip,
+ g_round_even => g_lsb_round_even,
g_pipeline_input => 0,
g_pipeline_output => g_pipeline_remove_lsb,
g_in_dat_w => g_in_dat_w,
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index 588ecaa3855af842133feb4992baedac0ea896f7..65ccff8133905b359036ed56b3a98c50060579c1 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -43,7 +43,7 @@ ENTITY common_round IS
g_representation : STRING := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_round : BOOLEAN := TRUE; -- when TRUE round the input, else truncate the input
g_round_clip : BOOLEAN := FALSE; -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_round_even : BOOLEAN := FALSE; -- when TRUE round even
+ g_round_even : BOOLEAN := FALSE; -- when TRUE round to even, else round away from zero
g_pipeline_input : NATURAL := 0; -- >= 0
g_pipeline_output : NATURAL := 1; -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
g_in_dat_w : NATURAL := 36;
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index 1ae2ca974821c6bc4319b9e74a5d6ff3fc5b3fc9..31d63241e128df435401ce5e9a9bba5a41adf732 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -34,14 +34,15 @@ USE common_lib.common_pkg.ALL;
ENTITY dp_requantize IS
GENERIC (
- g_complex : BOOLEAN := TRUE; -- when true, the re and im field are processed, when false, the data field is processed
+ g_complex : BOOLEAN := TRUE; -- when TRUE, the re and im field are processed, when false, the data field is processed
g_representation : STRING := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_lsb_w : INTEGER := 4; -- when > 0, number of LSbits to remove from in_dat
-- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
-- when 0 then no effect
- g_lsb_round : BOOLEAN := TRUE; -- when true ROUND else TRUNCATE the input LSbits
- g_lsb_round_clip : BOOLEAN := FALSE; -- when true round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
- g_msb_clip : BOOLEAN := TRUE; -- when true CLIP else WRAP the input MSbits
+ g_lsb_round : BOOLEAN := TRUE; -- when TRUE round else truncate the input LSbits
+ g_lsb_round_clip : BOOLEAN := FALSE; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
+ g_lsb_round_even : BOOLEAN := FALSE; -- when TRUE round to even, else round away from zero
+ g_msb_clip : BOOLEAN := TRUE; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : BOOLEAN := FALSE; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : NATURAL := 0; -- do not use, must be 0, use negative g_lsb_w instead
@@ -88,7 +89,8 @@ BEGIN
g_representation => g_representation,
g_lsb_w => g_lsb_w,
g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
g_msb_clip => g_msb_clip,
g_msb_clip_symmetric => g_msb_clip_symmetric,
g_pipeline_remove_lsb => g_pipeline_remove_lsb,
@@ -113,7 +115,8 @@ BEGIN
g_representation => g_representation,
g_lsb_w => g_lsb_w,
g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
g_msb_clip => g_msb_clip,
g_msb_clip_symmetric => g_msb_clip_symmetric,
g_pipeline_remove_lsb => g_pipeline_remove_lsb,
@@ -133,7 +136,8 @@ BEGIN
g_representation => g_representation,
g_lsb_w => g_lsb_w,
g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
g_msb_clip => g_msb_clip,
g_msb_clip_symmetric => g_msb_clip_symmetric,
g_pipeline_remove_lsb => g_pipeline_remove_lsb,