diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 4c06119e922ea4374aeea3fa67badba963c148c3..c6dc1c195a371886a2c5d737e3058de81f351325 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -142,6 +142,8 @@ synth_files =
src/vhdl/dp_counter_func_single.vhd
src/vhdl/dp_counter_func.vhd
src/vhdl/dp_counter.vhd
+ src/vhdl/dp_complex_mult.vhd
+ src/vhdl/dp_complex_add.vhd
tb/vhdl/dp_stream_player.vhd
tb/vhdl/dp_sosi_recorder.vhd
tb/vhdl/dp_stream_rec_play.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_complex_add.vhd b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0544a30a3c3837c6ebd1ff953055c0aeab2a7171
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
@@ -0,0 +1,124 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2017
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- . Provide a complex adder tree with streaming array I/O types
+-- Description:
+
+
+ENTITY dp_complex_add IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_inputs : NATURAL;
+ g_data_w : NATURAL --Complex input data width
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
+ src_out : OUT t_dp_sosi
+ );
+END dp_complex_add;
+
+ARCHITECTURE str OF dp_complex_add IS
+
+ CONSTANT c_pipeline : NATURAL := 1;
+ CONSTANT c_common_adder_tree_sum_w : NATURAL := g_data_w + ceil_log2(g_nof_inputs);
+
+ SIGNAL common_adder_tree_re_in_dat : STD_LOGIC_VECTOR(g_nof_inputs*g_data_w-1 DOWNTO 0);
+ SIGNAL common_adder_tree_im_in_dat : STD_LOGIC_VECTOR(g_nof_inputs*g_data_w-1 DOWNTO 0);
+
+ SIGNAL common_adder_tree_re_sum : STD_LOGIC_VECTOR(c_common_adder_tree_sum_w-1 DOWNTO 0);
+ SIGNAL common_adder_tree_im_sum : STD_LOGIC_VECTOR(c_common_adder_tree_sum_w-1 DOWNTO 0);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- Complex Adder Trees
+ -----------------------------------------------------------------------------
+ gen_common_complex_mult : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+
+ -- DP SOSI array to flat STD_LOGIC_VECTORs
+ common_adder_tree_re_in_dat((i+1)*g_data_w-1 DOWNTO i*g_data_w) <= snk_in_arr(i).re(g_data_w-1 DOWNTO 0);
+ common_adder_tree_im_in_dat((i+1)*g_data_w-1 DOWNTO i*g_data_w) <= snk_in_arr(i).im(g_data_w-1 DOWNTO 0);
+
+ -- One adder tree for the real part
+ u_adder_tree_re : ENTITY common_lib.common_adder_tree(str)
+ GENERIC MAP (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ PORT MAP (
+ clk => clk,
+ in_dat => common_adder_tree_re_in_dat,
+ sum => common_adder_tree_re_sum
+ );
+
+ -- One adder tree for the imaginary part
+ u_adder_tree_im : ENTITY common_lib.common_adder_tree(str)
+ GENERIC MAP (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ PORT MAP (
+ clk => clk,
+ in_dat => common_adder_tree_im_in_dat,
+ sum => common_adder_tree_im_sum
+ );
+
+ END GENERATE;
+
+ src_out.re <= RESIZE_DP_DSP_DATA(common_adder_tree_re_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
+ src_out.im <= RESIZE_DP_DSP_DATA(common_adder_tree_im_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
+
+ -----------------------------------------------------------------------------
+ -- Forward the input valid with the correct latency
+ -----------------------------------------------------------------------------
+ u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
+ GENERIC MAP (
+ g_pipeline => c_pipeline
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+
+ in_dat => snk_in_arr(0).valid,
+ out_dat => src_out.valid
+ );
+
+END str;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
index 6a8791edfb9cf050976a0ae9d9a4ae02028add41..80b0c46c2fa6f7fedccfaa009339e3e255259b3f 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
@@ -41,7 +41,7 @@ ENTITY dp_complex_mult IS
g_technology : NATURAL := c_tech_select_default;
g_nof_multipliers : NATURAL;
g_conjugate_b : BOOLEAN := FALSE; -- Conjugate input 1 of snk_in_2arr2(i)(1 DOWNTO 0)
- g_data_w : NATURAL; -- Input data width. Output data width = 2*input data width.
+ g_data_w : NATURAL -- Input data width. Output data width = 2*input data width.
);
PORT (
rst : IN STD_LOGIC;