diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 2c1c88c6447b0b1b01516ffec8e4f0e0c57544bf..c38ea595e3e6775f694d6eff6d135540cbc93661 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -49,7 +49,8 @@ ENTITY ctrl_unb2_board IS
g_stamp_time : NATURAL := 0;
g_stamp_svn : NATURAL := 0;
g_design_note : STRING := "UNUSED";
- g_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_125M; -- default use same MM clock as for TSE clock
+ g_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_125M;
+ g_eth_clk_freq : NATURAL := c_unb2_board_eth_clk_freq_125M;
----------------------------------------------------------------------------
-- External CLK
@@ -115,12 +116,11 @@ ENTITY ctrl_unb2_board IS
--
-- System
cs_sim : OUT STD_LOGIC;
- xo_clk25 : OUT STD_LOGIC; -- 25 MHz ETH_clk
- xo_rst25 : OUT STD_LOGIC;
- xo_rst25_n : OUT STD_LOGIC;
+ xo_ethclk : OUT STD_LOGIC; -- 25 MHz ETH_clk
+ xo_rst : OUT STD_LOGIC;
+ xo_rst_n : OUT STD_LOGIC;
- mm_clk : OUT STD_LOGIC; -- 50 MHz from xo_clk25 PLL in QSYS system
- mm_locked : OUT STD_LOGIC;
+ mm_clk : OUT STD_LOGIC; -- 50 MHz from xo_ethclk PLL
mm_rst : OUT STD_LOGIC;
dp_rst : OUT STD_LOGIC;
@@ -149,9 +149,6 @@ ENTITY ctrl_unb2_board IS
reg_remu_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_remu_miso : OUT t_mem_miso;
- -- EPCS
- epcs_clk : OUT STD_LOGIC;
-
-- EPCS read
reg_dpmm_data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_dpmm_data_miso : OUT t_mem_miso;
@@ -228,9 +225,9 @@ END ctrl_unb2_board;
ARCHITECTURE str OF ctrl_unb2_board IS
-- Clock and reset
- SIGNAL i_xo_clk25 : STD_LOGIC;
- SIGNAL i_xo_rst25 : STD_LOGIC;
- SIGNAL i_xo_rst25_n : STD_LOGIC;
+ SIGNAL i_xo_ethclk : STD_LOGIC;
+ SIGNAL i_xo_rst : STD_LOGIC;
+ SIGNAL i_xo_rst_n : STD_LOGIC;
SIGNAL i_mm_rst : STD_LOGIC;
SIGNAL i_mm_clk : STD_LOGIC;
SIGNAL i_mm_locked : STD_LOGIC;
@@ -272,19 +269,17 @@ ARCHITECTURE str OF ctrl_unb2_board IS
BEGIN
- xo_clk25 <= i_xo_clk25;
- xo_rst25 <= i_xo_rst25;
- xo_rst25_n <= i_xo_rst25_n;
- mm_clk <= i_mm_clk;
- mm_rst <= i_mm_rst;
- mm_locked <= i_mm_locked;
- epcs_clk <= i_epcs_clk;
+ xo_ethclk <= i_xo_ethclk;
+ xo_rst <= i_xo_rst;
+ xo_rst_n <= i_xo_rst_n;
+ mm_clk <= i_mm_clk;
+ mm_rst <= i_mm_rst;
-----------------------------------------------------------------------------
-- Node set up
-----------------------------------------------------------------------------
- i_xo_rst25 <= NOT i_xo_rst25_n;
+ i_xo_rst <= NOT i_xo_rst_n;
-- Default leave unused INOUT tri-state
INTA <= 'Z';
@@ -293,9 +288,9 @@ BEGIN
TESTIO <= (OTHERS=>'Z'); -- Leave unused INOUT tri-state
-- Clock and reset
- i_xo_clk25 <= ETH_clk; -- use the 25 MHz from the ETH_clk pin as xo_clk
- ext_clk200 <= CLK; -- use the external 200 MHz CLK as ext_clk
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+ i_xo_ethclk <= ETH_clk; -- use the ETH_clk pin as xo_clk
+ ext_clk200 <= CLK; -- use the external 200 MHz CLK as ext_clk
+ ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
dp_dis <= i_mm_rst; -- could use software control for this instead
@@ -319,19 +314,38 @@ BEGIN
END GENERATE;
- u_unb2_board_clk25_pll : ENTITY work.unb2_board_clk25_pll
- GENERIC MAP (
- g_technology => g_technology
- )
- PORT MAP (
- arst => i_xo_rst25,
- clk25 => i_xo_clk25,
- c0_clk20 => i_epcs_clk,
- c1_clk50 => i_mm_clk,
- c2_clk100 => OPEN,
- c3_clk125 => i_tse_clk,
- pll_locked => i_mm_locked
- );
+ gen_eth_clk_25: IF g_eth_clk_freq = c_unb2_board_eth_clk_freq_25M GENERATE
+ u_unb2_board_clk25_pll : ENTITY work.unb2_board_clk25_pll
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ arst => i_xo_rst,
+ clk25 => i_xo_ethclk,
+ c0_clk20 => i_epcs_clk,
+ c1_clk50 => i_mm_clk,
+ c2_clk100 => OPEN,
+ c3_clk125 => i_tse_clk,
+ pll_locked => i_mm_locked
+ );
+ END GENERATE;
+
+ gen_eth_clk_125: IF g_eth_clk_freq = c_unb2_board_eth_clk_freq_125M GENERATE
+ u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => i_epcs_clk,
+ c1_clk50 => i_mm_clk,
+ c2_clk100 => OPEN,
+ c3_clk125 => OPEN,
+ pll_locked => i_mm_locked
+ );
+ i_tse_clk <= i_xo_ethclk;
+ END GENERATE;
u_unb2_board_node_ctrl : ENTITY work.unb2_board_node_ctrl
@@ -339,8 +353,8 @@ BEGIN
g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
PORT MAP (
- xo_clk => i_xo_clk25,
- xo_rst_n => i_xo_rst25_n,
+ xo_clk => i_xo_ethclk,
+ xo_rst_n => i_xo_rst_n,
sys_clk => i_mm_clk,
sys_locked => i_mm_locked,
sys_rst => i_mm_rst,
@@ -604,7 +618,7 @@ BEGIN
-- Clocks and reset
mm_rst => i_mm_rst,
mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
+ eth_clk => i_tse_clk, -- 125 MHz clock
st_rst => eth1g_st_rst,
st_clk => eth1g_st_clk,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..52ad1fa2196ca6637b431963b6a0007c8ad2f651
--- /dev/null
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -0,0 +1,69 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib, tech_pll_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
+-- Description:
+-- c0 = 20 MHz
+-- c1 = 50 MHz
+-- c2 = 100 MHz
+-- c3 = 125 MHz
+--
+
+ENTITY unb2_board_clk125_pll IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_arria10
+ );
+ PORT (
+ arst : IN STD_LOGIC := '0';
+ clk125 : IN STD_LOGIC := '0'; -- connect to UniBoard ETH_clk pin (125 MHz)
+
+ c0_clk20 : OUT STD_LOGIC; -- PLL c0
+ c1_clk50 : OUT STD_LOGIC; -- PLL c1
+ c2_clk100 : OUT STD_LOGIC; -- PLL c2
+ c3_clk125 : OUT STD_LOGIC; -- PLL c3
+ pll_locked : OUT STD_LOGIC
+ );
+END unb2_board_clk125_pll;
+
+
+ARCHITECTURE arria10 OF unb2_board_clk125_pll IS
+BEGIN
+
+ u_pll : ENTITY tech_pll_lib.tech_pll_clk125
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk125,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
+END arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index ef1ec11fd955b209fe5cd0e86569f93c9c223a90..adc18e48bb357962c9a12fa684b164c7f6c7842a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -41,12 +41,13 @@ PACKAGE unb2_board_pkg IS
-- Clock frequencies
CONSTANT c_unb2_board_ext_clk_freq_200M : NATURAL := 200 * 10**6; -- external clock, SMA clock
- CONSTANT c_unb2_board_eth_clk_freq : NATURAL := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL in QSYS
- CONSTANT c_unb2_board_tse_clk_freq : NATURAL := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL in QSYS
- CONSTANT c_unb2_board_cal_clk_freq : NATURAL := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL in QSYS
- CONSTANT c_unb2_board_mm_clk_freq_50M : NATURAL := 50 * 10**6; -- QSYS memory mapped bus clock derived from ETH_clk by PLL in QSYS
- CONSTANT c_unb2_board_mm_clk_freq_100M : NATURAL := 100 * 10**6; -- QSYS memory mapped bus clock derived from ETH_clk by PLL in QSYS
- CONSTANT c_unb2_board_mm_clk_freq_125M : NATURAL := 125 * 10**6; -- QSYS memory mapped bus clock derived from ETH_clk by PLL in QSYS
+ CONSTANT c_unb2_board_eth_clk_freq_25M : NATURAL := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ CONSTANT c_unb2_board_eth_clk_freq_125M : NATURAL := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ CONSTANT c_unb2_board_tse_clk_freq : NATURAL := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_cal_clk_freq : NATURAL := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_mm_clk_freq_50M : NATURAL := 50 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_mm_clk_freq_100M : NATURAL := 100 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_mm_clk_freq_125M : NATURAL := 125 * 10**6; -- clock derived from ETH_clk by PLL
-- I2C
CONSTANT c_unb2_board_reg_sens_adr_w : NATURAL := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd