From aaec1ead3626ea172d1f08b629ba922337dfb6d9 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 2 May 2023 16:26:49 +0200
Subject: [PATCH] typo fix
---
.../technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
index e6cf53acef..ab2d7c1649 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
@@ -134,7 +134,7 @@ BEGIN
sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
- wea(0) => wren, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+ wea(0) => wren -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
--
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