From aa967f59fb6a2377f1d0dd90ae0a51a5ad381c98 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 6 Jan 2015 14:44:22 +0000
Subject: [PATCH] Rename dvr_start_addr into dvr_start_address.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 74 +++++++++----------
.../io/ddr/src/vhdl/io_ddr_cross_domain.vhd | 22 +++---
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd | 12 +--
3 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 30f4213129..f5efb874cb 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -30,9 +30,9 @@
--
-- The DDR access starts after a dvr_en pulse. The access can be write or
-- read as defined by dvr_wr_not_rd. The size of the access depends the
--- address range given by dvr_start_addr and dvr_end_addr. The dvr_done goes
--- high when the access has finished and it goes low when a new access
--- starts.
+-- address range given by dvr_start_address and dvr_end_address. The
+-- dvr_done goes high when the access has finished and it goes low when a
+-- new access starts.
--
-- The dvr_wr_flush_en pulse is recognized only between DDR accesses so when
-- the dvr_done is active, otherwise the dvr_wr_flush_en is ignored. The
@@ -62,11 +62,11 @@
-- /---->|ctrl |<--\ | |<----| |<--> phy_io
-- |/--->|______| | | | . | |
-- || | | | . | |
--- dvr_en ----*---------+|---------------|->| | . | |
--- dvr_wr_not_rd ----*----------+---------------|->| | . | |
--- dvr_done <---*--------------------------+--| | . | |
--- dvr_start_addr ----*---------------------------->| | . | |
--- dvr_end_addr ----*---------------------------->| | . | |
+-- dvr_en --*---------+|---------------|->| | . | |
+-- dvr_wr_not_rd --*----------+---------------|->| | . | |
+-- dvr_done <-*--------------------------+--| | . | |
+-- dvr_start_address --*---------------------------->| | . | |
+-- dvr_end_address --*---------------------------->| | . | |
-- ________ | | . | |
-- rd_clk --------->|dp_fifo | | | . | |
-- rd_sosi <---------|dc_mixed|<---------------------| | . | |
@@ -84,7 +84,7 @@
-- . If the dvr_clk=ctlr_clk then the clock domain crossing logic defaults
-- to wires. However dvr_clk could also be the dp_clk or the mm_clk and then
-- the clock domain crossing logic is needed.
--- No need to cross dvr_start_addr, because the address is stable when the
+-- No need to cross dvr_start_address, because the address is stable when the
-- dvr_en is stable.
-- . Externally connect ctlr_clk = ctlr_clk_in = ctlr_clk_out
-- . Typically wr_clk = rd_clk = dp_clk.
@@ -131,8 +131,8 @@ ENTITY io_ddr IS
dvr_en : IN STD_LOGIC;
dvr_done : OUT STD_LOGIC;
dvr_wr_not_rd : IN STD_LOGIC;
- dvr_start_addr : IN STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0);
- dvr_end_addr : IN STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0);
+ dvr_start_address : IN STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0);
+ dvr_end_address : IN STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0);
dvr_wr_flush_en : IN STD_LOGIC := '0';
-- Write FIFO clock domain
@@ -172,12 +172,12 @@ ARCHITECTURE str OF io_ddr IS
CONSTANT c_wr_fifo_af_margin : NATURAL := 4 + 1; -- use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
CONSTANT c_rd_fifo_af_margin : NATURAL := 4 + g_tech_ddr.maxburstsize; -- use ctlr_rd_src_in.ready to only start new rd access when there is sufficient space in the read FIFO
- SIGNAL ctlr_dvr_en : STD_LOGIC;
- SIGNAL ctlr_dvr_done : STD_LOGIC;
- SIGNAL ctlr_dvr_wr_not_rd : STD_LOGIC;
- SIGNAL ctlr_dvr_start_addr : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
- SIGNAL ctlr_dvr_end_addr : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
- SIGNAL ctlr_dvr_wr_flush_en : STD_LOGIC := '0';
+ SIGNAL ctlr_dvr_en : STD_LOGIC;
+ SIGNAL ctlr_dvr_done : STD_LOGIC;
+ SIGNAL ctlr_dvr_wr_not_rd : STD_LOGIC;
+ SIGNAL ctlr_dvr_start_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL ctlr_dvr_end_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL ctlr_dvr_wr_flush_en : STD_LOGIC := '0';
SIGNAL ctlr_init_done : STD_LOGIC;
@@ -215,8 +215,8 @@ BEGIN
dvr_en => dvr_en,
dvr_done => dvr_done,
dvr_wr_not_rd => dvr_wr_not_rd,
- dvr_start_addr => dvr_start_addr,
- dvr_end_addr => dvr_end_addr,
+ dvr_start_address => dvr_start_address,
+ dvr_end_address => dvr_end_address,
dvr_wr_flush_en => dvr_wr_flush_en,
-- DDR controller clock domain
@@ -226,8 +226,8 @@ BEGIN
ctlr_dvr_en => ctlr_dvr_en,
ctlr_dvr_done => ctlr_dvr_done,
ctlr_dvr_wr_not_rd => ctlr_dvr_wr_not_rd,
- ctlr_dvr_start_addr => ctlr_dvr_start_addr,
- ctlr_dvr_end_addr => ctlr_dvr_end_addr,
+ ctlr_dvr_start_address => ctlr_dvr_start_address,
+ ctlr_dvr_end_address => ctlr_dvr_end_address,
ctlr_dvr_wr_flush_en => ctlr_dvr_wr_flush_en
);
@@ -345,28 +345,28 @@ BEGIN
u_io_ddr_driver : ENTITY work.io_ddr_driver
GENERIC MAP (
- g_tech_ddr => g_tech_ddr
+ g_tech_ddr => g_tech_ddr
)
PORT MAP (
- rst => ctlr_rst_in,
- clk => ctlr_clk_in,
+ rst => ctlr_rst_in,
+ clk => ctlr_clk_in,
- dvr_en => ctlr_dvr_en,
- dvr_wr_not_rd => ctlr_dvr_wr_not_rd,
- dvr_start_address => ctlr_dvr_start_addr,
- dvr_end_address => ctlr_dvr_end_addr,
- dvr_done => ctlr_dvr_done,
+ dvr_en => ctlr_dvr_en,
+ dvr_wr_not_rd => ctlr_dvr_wr_not_rd,
+ dvr_start_address => ctlr_dvr_start_address,
+ dvr_end_address => ctlr_dvr_end_address,
+ dvr_done => ctlr_dvr_done,
- wr_fifo_usedw => ctlr_wr_fifo_usedw,
- wr_snk_in => ctlr_wr_snk_in,
- wr_snk_out => ctlr_wr_snk_out,
+ wr_fifo_usedw => ctlr_wr_fifo_usedw,
+ wr_snk_in => ctlr_wr_snk_in,
+ wr_snk_out => ctlr_wr_snk_out,
- rd_src_out => ctlr_rd_src_out,
- rd_src_in => ctlr_rd_src_in,
+ rd_src_out => ctlr_rd_src_out,
+ rd_src_in => ctlr_rd_src_in,
- ctlr_init_done => ctlr_init_done,
- ctlr_miso => ctlr_miso,
- ctlr_mosi => ctlr_mosi
+ ctlr_init_done => ctlr_init_done,
+ ctlr_miso => ctlr_miso,
+ ctlr_mosi => ctlr_mosi
);
u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd b/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd
index 765125c5e9..a366680740 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd
@@ -27,8 +27,8 @@
-- . If the dvr_clk=ctlr_clk then the clock domain crossing logic defaults
-- to wires. However dvr_clk could also be the dp_clk or the mm_clk and then
-- the clock domain crossing logic is needed.
--- No need to cross dvr_start_addr, because the address is stable when the
--- dvr_en is stable.
+-- No need to cross dvr_start_address and dvr_end_address, because these
+-- are stable when the dvr_en is stable.
LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -50,8 +50,8 @@ ENTITY io_ddr_cross_domain IS
dvr_en : IN STD_LOGIC;
dvr_done : OUT STD_LOGIC;
dvr_wr_not_rd : IN STD_LOGIC;
- dvr_start_addr : IN STD_LOGIC_VECTOR;
- dvr_end_addr : IN STD_LOGIC_VECTOR;
+ dvr_start_address : IN STD_LOGIC_VECTOR;
+ dvr_end_address : IN STD_LOGIC_VECTOR;
dvr_wr_flush_en : IN STD_LOGIC := '0';
-- DDR controller clock domain
@@ -61,8 +61,8 @@ ENTITY io_ddr_cross_domain IS
ctlr_dvr_en : OUT STD_LOGIC;
ctlr_dvr_done : IN STD_LOGIC;
ctlr_dvr_wr_not_rd : OUT STD_LOGIC;
- ctlr_dvr_start_addr : OUT STD_LOGIC_VECTOR;
- ctlr_dvr_end_addr : OUT STD_LOGIC_VECTOR;
+ ctlr_dvr_start_address : OUT STD_LOGIC_VECTOR;
+ ctlr_dvr_end_address : OUT STD_LOGIC_VECTOR;
ctlr_dvr_wr_flush_en : OUT STD_LOGIC := '0'
);
END io_ddr_cross_domain;
@@ -79,8 +79,8 @@ BEGIN
-- dvr_clk --> ctlr_clk
ctlr_dvr_en <= dvr_en;
ctlr_dvr_wr_not_rd <= dvr_wr_not_rd;
- ctlr_dvr_start_addr <= dvr_start_addr;
- ctlr_dvr_end_addr <= dvr_end_addr;
+ ctlr_dvr_start_address <= dvr_start_address;
+ ctlr_dvr_end_address <= dvr_end_address;
ctlr_dvr_wr_flush_en <= dvr_wr_flush_en;
-- ctlr_clk --> dvr_clk
@@ -104,9 +104,9 @@ BEGIN
);
-- Only register into the other clock domain
- ctlr_dvr_wr_not_rd <= dvr_wr_not_rd WHEN rising_edge(ctlr_clk);
- ctlr_dvr_start_addr <= dvr_start_addr WHEN rising_edge(ctlr_clk);
- ctlr_dvr_end_addr <= dvr_end_addr WHEN rising_edge(ctlr_clk);
+ ctlr_dvr_wr_not_rd <= dvr_wr_not_rd WHEN rising_edge(ctlr_clk);
+ ctlr_dvr_start_address <= dvr_start_address WHEN rising_edge(ctlr_clk);
+ ctlr_dvr_end_address <= dvr_end_address WHEN rising_edge(ctlr_clk);
u_common_spulse_ctlr_dvr_wr_flush_en : ENTITY common_lib.common_spulse
GENERIC MAP (
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index df392db34c..e11294fc4f 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -90,8 +90,8 @@ ARCHITECTURE str of tb_io_ddr IS
SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
- SIGNAL dvr_start_addr : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
- SIGNAL dvr_end_addr : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL dvr_start_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL dvr_end_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
SIGNAL dvr_en : STD_LOGIC;
SIGNAL dvr_done : STD_LOGIC;
@@ -154,8 +154,8 @@ BEGIN
FOR R IN 0 TO g_nof_repeat-1 LOOP
FOR I IN c_ctlr_address_lo_arr'RANGE LOOP
- dvr_start_addr <= TO_UVEC(c_ctlr_address_lo_arr(I) , c_ctlr_address_w);
- dvr_end_addr <= TO_UVEC(c_ctlr_address_lo_arr(I)+c_ctlr_nof_address_arr(I)-1, c_ctlr_address_w);
+ dvr_start_address <= TO_UVEC(c_ctlr_address_lo_arr(I) , c_ctlr_address_w);
+ dvr_end_address <= TO_UVEC(c_ctlr_address_lo_arr(I)+c_ctlr_nof_address_arr(I)-1, c_ctlr_address_w);
-- START ACCESS
dvr_wr_not_rd <= c_ctlr_wr_not_rd_arr(I);
@@ -281,8 +281,8 @@ BEGIN
dvr_en => dvr_en,
dvr_wr_not_rd => dvr_wr_not_rd,
dvr_done => dvr_done,
- dvr_start_addr => dvr_start_addr,
- dvr_end_addr => dvr_end_addr,
+ dvr_start_address => dvr_start_address,
+ dvr_end_address => dvr_end_address,
dvr_wr_flush_en => dvr_wr_flush_en,
-- Write FIFO clock domain
--
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