From aa76980db3b3712f428be94778ca1411a3c298fa Mon Sep 17 00:00:00 2001 From: Zanting <zanting> Date: Thu, 1 Oct 2015 10:20:51 +0000 Subject: [PATCH] fixed DDR3 IP for 16GB SO-Dimms --- .../technology/ddr/tech_ddr_stratixiv.vhd | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/libraries/technology/ddr/tech_ddr_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd index 796e7bf12a..4e2bb7ddcc 100644 --- a/libraries/technology/ddr/tech_ddr_stratixiv.vhd +++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd @@ -35,6 +35,7 @@ LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib; LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib; LIBRARY ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_lib; LIBRARY ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_lib; +LIBRARY ip_stratixiv_ddr3_uphy_16g_dual_rank_800_lib; LIBRARY IEEE, technology_lib, common_lib; USE IEEE.STD_LOGIC_1164.ALL; @@ -306,6 +307,59 @@ BEGIN phy_ou.cs_n(0) <= i_mem_cs_n; phy_ou.odt(0) <= i_mem_odt; + END GENERATE; + + gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : IF g_tech_ddr.name="DDR3" AND c_gigabytes=16 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE AND g_tech_ddr.rank="DUAL " GENERATE + u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : ip_stratixiv_ddr3_uphy_16g_dual_rank_800 + PORT MAP ( + pll_ref_clk => ref_clk, -- pll_ref_clk.clk + global_reset_n => ref_rst_n, -- global_reset.reset_n + soft_reset_n => '1', -- soft_reset.reset_n + afi_clk => ctlr_gen_clk, -- afi_clk.clk + afi_half_clk => OPEN, -- afi_half_clk.clk + afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n + mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a + mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba + mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck + mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n + mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke + mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n + mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm + mem_ras_n => phy_ou.ras_n, -- .mem_ras_n + mem_cas_n => phy_ou.cas_n, -- .mem_cas_n + mem_we_n => phy_ou.we_n, -- .mem_we_n + mem_reset_n => phy_ou.reset_n, -- .mem_reset_n + mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq + mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs + mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n + mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt + avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n + avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer + avl_addr => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address + avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid + avl_rdata => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata + avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata + avl_be => (OTHERS=>'1'), -- .byteenable + avl_read_req => ctlr_mosi.rd, -- .read + avl_write_req => ctlr_mosi.wr, -- .write + avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount + local_init_done => ctlr_miso.done, -- status.local_init_done + local_cal_success => ctlr_miso.cal_ok, -- .local_cal_success + local_cal_fail => ctlr_miso.cal_fail, -- .local_cal_fail + oct_rdn => phy_in.oct_rdn, -- oct.rdn + oct_rup => phy_in.oct_rup, -- .rup + pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk + pll_write_clk => OPEN, -- .pll_write_clk + pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk + pll_locked => OPEN, -- .pll_locked + pll_avl_clk => OPEN, -- .pll_avl_clk + pll_config_clk => OPEN, -- .pll_config_clk + dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl + ); + + + END GENERATE; i_ctlr_gen_rst <= NOT ctlr_gen_rst_n; -- GitLab