diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index fb9412af4dfc3ab142875068423764a28a2cfa2e..18de8df52a034353db4a2280b037fd77a1e1ebc3 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -23,12 +23,11 @@
-- Description
--
-- . Loop back options:
--- ST XGMII XAUI
--- | | |
--- snk_in --> fifo ---\-|-/--> tech_mac_10g ---\-|-/--> tr_xaui ---\-|-/--> i/o pins
--- src_out <-- <--/ | <--/ | \--- <--/ | \--
+-- ST XGMII XAUI
+-- | | |
+-- snk_in --> fifo ---|--> tech_mac_10g ---|--> tr_xaui ---|--> i/o pins
+-- src_out <-- <--|--- <--|--- <--|---
--
--- g_loopback_dp g_loopback_xgmii g_loopback_xaui
--
LIBRARY IEEE, common_lib, dp_lib, diag_lib, tr_xaui_lib, technology_lib, tech_mac_10g_lib;
@@ -52,9 +51,6 @@ ENTITY tr_10GbE IS
g_use_mdio : BOOLEAN;
g_mdio_epcs_dis : BOOLEAN := FALSE; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
g_pkt_len : NATURAL := 100;
- g_loopback_dp : BOOLEAN := FALSE;
- g_loopback_xgmii : BOOLEAN := FALSE;
- g_loopback_xaui : BOOLEAN := FALSE;
g_word_alignment_padding : BOOLEAN := FALSE
);
PORT (
@@ -128,30 +124,15 @@ ARCHITECTURE str OF tr_10GbE IS
SIGNAL dp_fifo_fill_tx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL dp_fifo_fill_tx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL mac_10g_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL mac_10g_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
-
SIGNAL mac_10g_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL mac_10g_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_rx_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_rx_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
-
SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL mac_xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL mac_xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL xaui_xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL xaui_xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
-
- SIGNAL xaui_tx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL xaui_rx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
-
- SIGNAL serial_tx_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
- SIGNAL serial_rx_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
-
BEGIN
---------------------------------------------------------------------------------------
@@ -213,154 +194,97 @@ BEGIN
END GENERATE;
- ---------------------------------------------------------------------------------------
- -- DP loopback
- ---------------------------------------------------------------------------------------
- gen_loopback_dp : IF g_loopback_dp=TRUE GENERATE
- -- DP loopback Tx-Rx
- dp_fifo_fill_tx_src_in_arr <= dp_fifo_dc_rx_snk_out_arr;
- dp_fifo_dc_rx_snk_in_arr <= dp_fifo_fill_tx_src_out_arr;
-
- rx_rst_arr <= tx_rst_arr;
- rx_clk_arr <= tx_clk_arr;
- END GENERATE;
-
---------------------------------------------------------------------------------------
-- DP-MAC connect
---------------------------------------------------------------------------------------
- gen_connect_dp : IF g_loopback_dp=FALSE GENERATE
-
- -- DP-MAC connect Tx-Tx
- dp_fifo_fill_tx_src_in_arr <= mac_10g_snk_out_arr;
- mac_10g_snk_in_arr <= dp_fifo_fill_tx_src_out_arr;
-
- -- DP-MAC connect Rx-Rx
- mac_10g_src_in_arr <= dp_fifo_dc_rx_snk_out_arr;
- dp_fifo_dc_rx_snk_in_arr <= mac_10g_src_out_arr;
-
- gen_tech_mac_10g : FOR i IN 0 TO g_nof_macs-1 GENERATE
- u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
- GENERIC MAP (
- g_technology => g_technology,
- g_pre_header_padding => g_word_alignment_padding
- )
- PORT MAP (
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- csr_mosi => reg_mac_mosi_arr(i), -- CSR = control status register
- csr_miso => reg_mac_miso_arr(i),
-
- -- ST
- tx_clk_156 => tx_clk_arr(i), -- 156.25 MHz local reference
- tx_rst => tx_rst_arr(i),
- tx_snk_in => mac_10g_snk_in_arr(i), -- 64 bit data
- tx_snk_out => mac_10g_snk_out_arr(i),
-
- rx_clk_156 => rx_clk_arr(i), -- 156.25 MHz
- rx_rst => rx_rst_arr(i),
- rx_src_out => mac_10g_src_out_arr(i), -- 64 bit data
- rx_src_in => mac_10g_src_in_arr(i),
-
- -- XGMII
- xgmii_tx_data => mac_xgmii_tx_dc_arr(i), -- 72 bit
- xgmii_rx_data => mac_xgmii_rx_dc_arr(i) -- 72 bit
- );
- END GENERATE;
-
- ---------------------------------------------------------------------------------------
- -- XGMII loopback
- ---------------------------------------------------------------------------------------
- gen_loopback_xgmii: IF g_loopback_xgmii = TRUE GENERATE
- mac_xgmii_rx_dc_arr <= mac_xgmii_tx_dc_arr; -- MAC side loopback Tx-Rx
- xaui_xgmii_rx_dc_arr <= xaui_xgmii_tx_dc_arr; -- PHY side loopback Tx-Rx
- END GENERATE;
-
- gen_connect_xgmii: IF g_loopback_xgmii = FALSE GENERATE
- xaui_xgmii_tx_dc_arr <= mac_xgmii_tx_dc_arr; -- MAC-PHY connect Tx-Tx
- mac_xgmii_rx_dc_arr <= xaui_xgmii_rx_dc_arr; -- MAC-PHY connect Rx-Rx
- END GENERATE;
-
- ---------------------------------------------------------------------------------------
- -- XGMII-XAUI connect
- ---------------------------------------------------------------------------------------
- u_tr_xaui : ENTITY tr_xaui_lib.tr_xaui
+
+ gen_tech_mac_10g : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
GENERIC MAP (
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_use_xgmii => TRUE, -- Use XGMII direct
- g_nof_xaui => g_nof_macs,
- g_mdio => g_use_mdio,
- g_mdio_epcs_dis => g_mdio_epcs_dis
+ g_technology => g_technology,
+ g_pre_header_padding => g_word_alignment_padding
)
PORT MAP (
- -- Transceiver PLL reference clock
- tr_clk => tr_clk, -- = tr_clk_156 = tx_clk_arr
- tr_rst => tr_rst, -- = tr_rst_156
-
- -- Calibration & reconfig clock
- cal_rec_clk => cal_rec_clk,
-
- -- MM clock for register of optional MDIO master
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- -- Streaming TX interfaces
- tx_clk_arr => tx_clk_arr,
- tx_rst_arr => tx_rst_arr,
-
- -- Streaming RX interfaces
- rx_clk_arr_out => rx_clk_arr,
- rx_clk_arr_in => rx_clk_arr,
- rx_rst_arr => rx_rst_arr,
-
- -- Direct XGMII interface
- xgmii_tx_dc_arr => xaui_xgmii_tx_dc_arr,
- xgmii_rx_dc_arr => xaui_xgmii_rx_dc_arr,
-
- --Serial I/O
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- -- XAUI PHY IP MM control/status
- xaui_mosi => xaui_mosi,
- xaui_miso => xaui_miso,
-
- -- MDIO master = mm slave
- mdio_mosi_arr => mdio_mosi_arr(g_nof_macs-1 DOWNTO 0),
- mdio_miso_arr => mdio_miso_arr(g_nof_macs-1 DOWNTO 0),
-
- -- MDIO External clock and serial data.
- mdio_rst => mdio_rst,
- mdio_mdc => mdio_mdc_arr,
- mdio_mdat_in => mdio_mdat_in_arr,
- mdio_mdat_oen => mdio_mdat_oen_arr
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ csr_mosi => reg_mac_mosi_arr(i), -- CSR = control status register
+ csr_miso => reg_mac_miso_arr(i),
+
+ -- ST
+ tx_clk_156 => tx_clk_arr(i), -- 156.25 MHz local reference
+ tx_rst => tx_rst_arr(i),
+ tx_snk_in => dp_fifo_fill_tx_src_out_arr(i), -- 64 bit data
+ tx_snk_out => dp_fifo_fill_tx_src_in_arr(i),
+
+ rx_clk_156 => rx_clk_arr(i), -- 156.25 MHz
+ rx_rst => rx_rst_arr(i),
+ rx_src_out => mac_10g_src_out_arr(i), -- 64 bit data
+ rx_src_in => mac_10g_src_in_arr(i),
+
+ -- XGMII
+ xgmii_tx_data => mac_xgmii_tx_dc_arr(i), -- 72 bit
+ xgmii_rx_data => mac_xgmii_rx_dc_arr(i) -- 72 bit
);
END GENERATE;
-
---------------------------------------------------------------------------------------
- -- PHY IO loopback
+ -- XGMII-XAUI connect
---------------------------------------------------------------------------------------
-
- gen_loopback_phy_io: IF g_loopback_xaui = TRUE GENERATE
- -- XAUI
- xaui_tx_out_arr <= xaui_rx_in_arr; -- pin external loopback Tx-Rx
- xaui_rx_arr <= xaui_tx_arr; -- PHY internal loopback Tx-Rx
- -- 10GBASE-R
- serial_tx_out_arr <= serial_rx_in_arr; -- pin external loopback Tx-Rx
- serial_rx_arr <= serial_tx_arr; -- PHY internal loopback Tx-Rx
- END GENERATE;
+ u_tr_xaui : ENTITY tr_xaui_lib.tr_xaui
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_use_xgmii => TRUE, -- Use XGMII direct
+ g_nof_xaui => g_nof_macs,
+ g_use_mdio => g_use_mdio,
+ g_mdio_epcs_dis => g_mdio_epcs_dis
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_clk => tr_clk, -- = tr_clk_156 = tx_clk_arr
+ tr_rst => tr_rst, -- = tr_rst_156
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_rec_clk,
+
+ -- MM clock for register of optional MDIO master
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ -- Streaming TX interfaces
+ tx_clk_arr => tx_clk_arr,
+ tx_rst_arr => tx_rst_arr,
+
+ -- Streaming RX interfaces
+ rx_clk_arr_out => rx_clk_arr,
+ rx_clk_arr_in => rx_clk_arr,
+ rx_rst_arr => rx_rst_arr,
+
+ -- Direct XGMII interface
+ xgmii_tx_dc_arr => mac_xgmii_tx_dc_arr,
+ xgmii_rx_dc_arr => mac_xgmii_rx_dc_arr,
+
+ --Serial I/O
+ xaui_tx_arr => xaui_tx_out_arr,
+ xaui_rx_arr => xaui_rx_in_arr,
+
+ -- XAUI PHY IP MM control/status
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso,
+
+ -- MDIO master = mm slave
+ mdio_mosi_arr => mdio_mosi_arr(g_nof_macs-1 DOWNTO 0),
+ mdio_miso_arr => mdio_miso_arr(g_nof_macs-1 DOWNTO 0),
+
+ -- MDIO External clock and serial data.
+ mdio_rst => mdio_rst,
+ mdio_mdc => mdio_mdc_arr,
+ mdio_mdat_in => mdio_mdat_in_arr,
+ mdio_mdat_oen => mdio_mdat_oen_arr
+ );
- gen_connect_phy_io: IF g_loopback_xaui = FALSE GENERATE
- -- XAUI
- xaui_tx_out_arr <= xaui_tx_arr; -- PHY-pin connect Tx-Tx
- xaui_rx_arr <= xaui_rx_in_arr; -- PHY-pin connect Rx-Rx
- -- 10GBASE-R
- serial_tx_out_arr <= serial_tx_arr; -- PHY-pin connect Tx-Tx
- serial_rx_arr <= serial_rx_in_arr; -- PHY-pin connect Rx-Rx
- END GENERATE;
---------------------------------------------------------------------------------------
-- RX FIFO: rx_clk -> dp_clk
@@ -378,8 +302,8 @@ BEGIN
rd_rst => dp_rst,
rd_clk => dp_clk,
- snk_out => dp_fifo_dc_rx_snk_out_arr(i),
- snk_in => dp_fifo_dc_rx_snk_in_arr(i),
+ snk_out => mac_10g_src_in_arr(i),
+ snk_in => mac_10g_src_out_arr(i),
src_in => dp_fifo_dc_rx_src_in_arr(i),
src_out => dp_fifo_dc_rx_src_out_arr(i)
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
index 635117308dba84b13018b5e4e485766315375137..9c38a3ae1d05db6b495675080c25c1e4b5676d5d 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
@@ -46,20 +46,14 @@ BEGIN
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
-- g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
--- g_dut_loopback_dp : BOOLEAN := FALSE; -- when TRUE loopback in DUT at ST interface
--- g_dut_loopback_xgmii : BOOLEAN := FALSE; -- when TRUE loopback in DUT at XGMII interface
--- g_dut_loopback_xaui : BOOLEAN := FALSE; -- when TRUE loopback in DUT at XAUI interface
-- -- g_data_type = c_tb_tech_mac_10g_data_type_symbols = 0
-- -- g_data_type = c_tb_tech_mac_10g_data_type_counter = 1
-- g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols
- u_no_dut_counter : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, TRUE, FALSE, FALSE, FALSE, c_tb_tech_mac_10g_data_type_counter) PORT MAP (tb_end_vec(0));
- u_no_dut_symbols : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, TRUE, FALSE, FALSE, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(1));
- u_tr_10GbE_symbols_loopback_dp : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, FALSE, TRUE, FALSE, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(2));
- u_tr_10GbE_symbols_loopback_xgmii : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, FALSE, FALSE, TRUE, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(3));
- u_tr_10GbE_symbols_loopback_xaui : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, FALSE, FALSE, FALSE, TRUE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(4));
- u_tr_10GbE_symbols : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, FALSE, FALSE, FALSE, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(5));
- u_tr_10GbE_symbols_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 1, FALSE, FALSE, FALSE, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(6));
+ u_no_dut_counter : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, TRUE, c_tb_tech_mac_10g_data_type_counter) PORT MAP (tb_end_vec(0));
+ u_no_dut_symbols : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, TRUE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(1));
+ u_tr_10GbE_symbols : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(5));
+ u_tr_10GbE_symbols_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 1, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(6));
p_tb_end : PROCESS
BEGIN
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
index bebb0d6da29b9cb16d058a4700bb6eb0fe3b645b..dec7fe15d9b3404c18595f8c0f9f8693b476937a 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
@@ -54,9 +54,6 @@ ENTITY tb_tr_10GbE IS
g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
- g_dut_loopback_dp : BOOLEAN := FALSE; -- when TRUE loopback in DUT at ST interface
- g_dut_loopback_xgmii : BOOLEAN := FALSE; -- when TRUE loopback in DUT at XGMII interface
- g_dut_loopback_xaui : BOOLEAN := FALSE; -- when TRUE loopback in DUT at XAUI interface
-- g_data_type = c_tb_tech_mac_10g_data_type_symbols = 0
-- g_data_type = c_tb_tech_mac_10g_data_type_counter = 1
g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols
@@ -261,7 +258,7 @@ BEGIN
IF rising_edge(rx_clk) THEN
rx_sosi_reg <= rx_sosi; -- use rx_sosi_reg for verification at eop to account for once cycle latency in expected_sosi_arr()
IF rx_sosi_reg.eop='1' THEN
- IF g_no_dut=FALSE AND g_dut_loopback_dp=FALSE THEN
+ IF g_no_dut=FALSE THEN
IF c_pkt_length_arr(vI) < 64 - 14 - 20 - 8 - 4 THEN -- = minimum frame 64 - ETH 14 - IP 20 - UDP 8 - CRC 4
-- frame shorter than 64 get padded so empty after stripping the Rx CRC is fixed 4, which becomes 6 due to pre header padding for UDP word align
IF TO_UINT(rx_sosi_reg.empty) /= 6 THEN
@@ -308,9 +305,6 @@ BEGIN
g_use_mdio => TRUE,
g_mdio_epcs_dis => TRUE, -- TRUE disables Enhanced PCS on init; e.g. to target a 10GbE card in PC that does not support it
g_pkt_len => 100,
- g_loopback_dp => g_dut_loopback_dp,
- g_loopback_xgmii => g_dut_loopback_xgmii,
- g_loopback_xaui => g_dut_loopback_xaui,
g_word_alignment_padding => TRUE
)
PORT MAP (