diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
index 83a183ca206c9414932862eae79044700881061d..0014d8a37859e8e234f7cdcd15f7646b51501e4b 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140;
-LIBRARY ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140;
-LIBRARY ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140;
+LIBRARY ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141;
+LIBRARY ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141;
+LIBRARY ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141;
LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index 266c1e5e10e805328ce7df251343655913a5b7ea..6202680f61e95d5f37eba24f81740c6390560e92 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_flash_lib;
-LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_140;
+LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_141;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index d0221926c21152979ddfd62cf2f74d771a3c55de..cf5214844eb457604c6193d121552af45d2db605 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_flash_lib;
-LIBRARY ip_arria10_remote_update_altera_remote_update_140;
+LIBRARY ip_arria10_remote_update_altera_remote_update_141;
ENTITY tech_flash_remote_update IS
GENERIC (
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..56979bf03cf14fdbbaccd07c2ed8eda1a0edcea7
--- /dev/null
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk125/generated/sim"
+
+#vlib ./work/ ;# Assume library work already exists
+
+vmap ip_arria10_pll_clk125_altera_iopll_141 ./work/
+
+vlog "$IP_DIR/../altera_iopll_141/sim/ip_arria10_pll_clk125_altera_iopll_141_qufmo5q.vo" -work ip_arria10_pll_clk125_altera_iopll_141
+vcom "$IP_DIR/ip_arria10_pll_clk125.vhd"
+
+
diff --git a/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e0036549162a3f7fbbe7bb0026515281b9b7e84f
--- /dev/null
+++ b/libraries/technology/ip_arria10/pll_clk125/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_pll_clk125.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a09fe31c2dd58c7334f7befaf2541d639b303bd6
--- /dev/null
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_pll_clk125
+hdl_library_clause_name = ip_arria10_pll_clk125_altera_iopll_141
+hdl_lib_uses =
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_pll_clk125.qip
diff --git a/libraries/technology/ip_arria10/pll_clk125/ip_arria10_pll_clk125.qsys b/libraries/technology/ip_arria10/pll_clk125/ip_arria10_pll_clk125.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..36b79ec1505851ff6056a51b346baf1869bb7d62
--- /dev/null
+++ b/libraries/technology/ip_arria10/pll_clk125/ip_arria10_pll_clk125.qsys
@@ -0,0 +1,358 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start">
+ <port name="outclk_0" internal="outclk_0" />
+ </interface>
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start">
+ <port name="outclk_1" internal="outclk_1" />
+ </interface>
+ <interface name="outclk2" internal="iopll_0.outclk2" type="clock" dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
+ <interface name="outclk3" internal="iopll_0.outclk3" type="clock" dir="start">
+ <port name="outclk_3" internal="outclk_3" />
+ </interface>
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end">
+ <port name="refclk" internal="refclk" />
+ </interface>
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
+ </interface>
+ <module
+ name="iopll_0"
+ kind="altera_iopll"
+ version="14.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="gui_active_clk" value="false" />
+ <parameter name="gui_actual_duty_cycle0" value="50.0" />
+ <parameter name="gui_actual_duty_cycle1" value="50.0" />
+ <parameter name="gui_actual_duty_cycle10" value="50.0" />
+ <parameter name="gui_actual_duty_cycle11" value="50.0" />
+ <parameter name="gui_actual_duty_cycle12" value="50.0" />
+ <parameter name="gui_actual_duty_cycle13" value="50.0" />
+ <parameter name="gui_actual_duty_cycle14" value="50.0" />
+ <parameter name="gui_actual_duty_cycle15" value="50.0" />
+ <parameter name="gui_actual_duty_cycle16" value="50.0" />
+ <parameter name="gui_actual_duty_cycle17" value="50.0" />
+ <parameter name="gui_actual_duty_cycle2" value="50.0" />
+ <parameter name="gui_actual_duty_cycle3" value="50.0" />
+ <parameter name="gui_actual_duty_cycle4" value="50.0" />
+ <parameter name="gui_actual_duty_cycle5" value="50.0" />
+ <parameter name="gui_actual_duty_cycle6" value="50.0" />
+ <parameter name="gui_actual_duty_cycle7" value="50.0" />
+ <parameter name="gui_actual_duty_cycle8" value="50.0" />
+ <parameter name="gui_actual_duty_cycle9" value="50.0" />
+ <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_actual_phase_shift0" value="0.0" />
+ <parameter name="gui_actual_phase_shift1" value="0.0" />
+ <parameter name="gui_actual_phase_shift10" value="0.0" />
+ <parameter name="gui_actual_phase_shift11" value="0.0" />
+ <parameter name="gui_actual_phase_shift12" value="0.0" />
+ <parameter name="gui_actual_phase_shift13" value="0.0" />
+ <parameter name="gui_actual_phase_shift14" value="0.0" />
+ <parameter name="gui_actual_phase_shift15" value="0.0" />
+ <parameter name="gui_actual_phase_shift16" value="0.0" />
+ <parameter name="gui_actual_phase_shift17" value="0.0" />
+ <parameter name="gui_actual_phase_shift2" value="0.0" />
+ <parameter name="gui_actual_phase_shift3" value="0.0" />
+ <parameter name="gui_actual_phase_shift4" value="0.0" />
+ <parameter name="gui_actual_phase_shift5" value="0.0" />
+ <parameter name="gui_actual_phase_shift6" value="0.0" />
+ <parameter name="gui_actual_phase_shift7" value="0.0" />
+ <parameter name="gui_actual_phase_shift8" value="0.0" />
+ <parameter name="gui_actual_phase_shift9" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_clk_bad" value="false" />
+ <parameter name="gui_clock_name_global0" value="true" />
+ <parameter name="gui_clock_name_global1" value="true" />
+ <parameter name="gui_clock_name_global10" value="false" />
+ <parameter name="gui_clock_name_global11" value="false" />
+ <parameter name="gui_clock_name_global12" value="false" />
+ <parameter name="gui_clock_name_global13" value="false" />
+ <parameter name="gui_clock_name_global14" value="false" />
+ <parameter name="gui_clock_name_global15" value="false" />
+ <parameter name="gui_clock_name_global16" value="false" />
+ <parameter name="gui_clock_name_global17" value="false" />
+ <parameter name="gui_clock_name_global2" value="true" />
+ <parameter name="gui_clock_name_global3" value="true" />
+ <parameter name="gui_clock_name_global4" value="false" />
+ <parameter name="gui_clock_name_global5" value="false" />
+ <parameter name="gui_clock_name_global6" value="false" />
+ <parameter name="gui_clock_name_global7" value="false" />
+ <parameter name="gui_clock_name_global8" value="false" />
+ <parameter name="gui_clock_name_global9" value="false" />
+ <parameter name="gui_clock_name_string0" value="pll_clk20" />
+ <parameter name="gui_clock_name_string1" value="pll_clk50" />
+ <parameter name="gui_clock_name_string10" value="outclk10" />
+ <parameter name="gui_clock_name_string11" value="outclk11" />
+ <parameter name="gui_clock_name_string12" value="outclk12" />
+ <parameter name="gui_clock_name_string13" value="outclk13" />
+ <parameter name="gui_clock_name_string14" value="outclk14" />
+ <parameter name="gui_clock_name_string15" value="outclk15" />
+ <parameter name="gui_clock_name_string16" value="outclk16" />
+ <parameter name="gui_clock_name_string17" value="outclk17" />
+ <parameter name="gui_clock_name_string2" value="pll_clk100" />
+ <parameter name="gui_clock_name_string3" value="pll_clk125" />
+ <parameter name="gui_clock_name_string4" value="outclk4" />
+ <parameter name="gui_clock_name_string5" value="outclk5" />
+ <parameter name="gui_clock_name_string6" value="outclk6" />
+ <parameter name="gui_clock_name_string7" value="outclk7" />
+ <parameter name="gui_clock_name_string8" value="outclk8" />
+ <parameter name="gui_clock_name_string9" value="outclk9" />
+ <parameter name="gui_device_speed_grade" value="1" />
+ <parameter name="gui_divide_factor_c0" value="6" />
+ <parameter name="gui_divide_factor_c1" value="6" />
+ <parameter name="gui_divide_factor_c10" value="6" />
+ <parameter name="gui_divide_factor_c11" value="6" />
+ <parameter name="gui_divide_factor_c12" value="6" />
+ <parameter name="gui_divide_factor_c13" value="6" />
+ <parameter name="gui_divide_factor_c14" value="6" />
+ <parameter name="gui_divide_factor_c15" value="6" />
+ <parameter name="gui_divide_factor_c16" value="6" />
+ <parameter name="gui_divide_factor_c17" value="6" />
+ <parameter name="gui_divide_factor_c2" value="6" />
+ <parameter name="gui_divide_factor_c3" value="6" />
+ <parameter name="gui_divide_factor_c4" value="6" />
+ <parameter name="gui_divide_factor_c5" value="6" />
+ <parameter name="gui_divide_factor_c6" value="6" />
+ <parameter name="gui_divide_factor_c7" value="6" />
+ <parameter name="gui_divide_factor_c8" value="6" />
+ <parameter name="gui_divide_factor_c9" value="6" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="false" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_mif_generate" value="false" />
+ <parameter name="gui_multiply_factor" value="6" />
+ <parameter name="gui_number_of_clocks" value="4" />
+ <parameter name="gui_operation_mode" value="direct" />
+ <parameter name="gui_output_clock_frequency0" value="20.0" />
+ <parameter name="gui_output_clock_frequency1" value="50.0" />
+ <parameter name="gui_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_output_clock_frequency3" value="125.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_phase_shift0" value="0.0" />
+ <parameter name="gui_phase_shift1" value="0.0" />
+ <parameter name="gui_phase_shift10" value="0.0" />
+ <parameter name="gui_phase_shift11" value="0.0" />
+ <parameter name="gui_phase_shift12" value="0.0" />
+ <parameter name="gui_phase_shift13" value="0.0" />
+ <parameter name="gui_phase_shift14" value="0.0" />
+ <parameter name="gui_phase_shift15" value="0.0" />
+ <parameter name="gui_phase_shift16" value="0.0" />
+ <parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
+ <parameter name="gui_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="125.0" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="system_info_device_component" value="10AX115U3F45I2LG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="2" />
+ <parameter name="system_part_trait_speed_grade" value="2" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index f189f3845b3d4210f61a0f0b687d8205ae87c7cd..0c60da766de1571dadcd1c7f4eb39ea811023d30 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -32,7 +32,7 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_clk25/generated
vmap ip_arria10_pll_clk25_altera_iopll_141 ./work/
-vlog "$IP_DIR/../altera_iopll_140/sim/ip_arria10_pll_clk25_altera_iopll_141_ve3shky.vo" -work ip_arria10_pll_clk25_altera_iopll_141
+vlog "$IP_DIR/../altera_iopll_141/sim/ip_arria10_pll_clk25_altera_iopll_141_ve3shky.vo" -work ip_arria10_pll_clk25_altera_iopll_141
vcom "$IP_DIR/ip_arria10_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys b/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys
index f552f07286bd6cb58cac0695b81e2aa30fcff108..c5871838f155566d0f24e729eb5349fa1910f498 100644
--- a/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys
+++ b/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys
@@ -6,11 +6,16 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element iopll_0
{
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
index 4539cfd73055c63835bedae12c9ed68a245d338f..29b109ad7c0ebba6350092e30dc6a4f314976140 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_mac_10g_alt_em10g32_140;
+LIBRARY ip_arria10_mac_10g_alt_em10g32_141;
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index 105d9f4bf58e8b8419b73427dd99e9c1ec159b98..3f0ddfe5a6e7973640f5dccaf1b1d5430c751c15 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_pll
hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_clk200 ip_arria10_pll_clk25 common
+hdl_lib_uses = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_clk200 ip_arria10_pll_clk25 ip_arria10_pll_clk125 common
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
@@ -12,5 +12,6 @@ synth_files =
tech_pll_clk200_p6.vhd
tech_pll_xgmii_mac_clocks.vhd
tech_pll_clk25.vhd
+ tech_pll_clk125.vhd
test_bench_files =
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ae53669ba65cadf3d1c93725064dc93c072242ae
--- /dev/null
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -0,0 +1,63 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_pll_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_pll_clk125_altera_iopll_141;
+
+ENTITY tech_pll_clk125 IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default
+ );
+ PORT (
+ areset : IN STD_LOGIC := '0';
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC ;
+ c2 : OUT STD_LOGIC ;
+ c3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+END tech_pll_clk125;
+
+ARCHITECTURE str OF tech_pll_clk125 IS
+
+BEGIN
+
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ip_arria10_pll_clk125
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
+
+END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 7f318db9bb6dfaf7518005a5a84ffb0ef5c41896..c045dd2f3382c160a4eb932aae8bc27f01832c38 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -27,7 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_pll_lib;
-LIBRARY ip_arria10_pll_clk200_altera_iopll_140;
+LIBRARY ip_arria10_pll_clk200_altera_iopll_141;
ENTITY tech_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 5d1bd1c78d88c852ff56e71b974d13e5f6819ed4..9e56bb05ff5f98db9a08a6674ae7d4f3e98ebae9 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_pll_clk25_altera_iopll_140;
+LIBRARY ip_arria10_pll_clk25_altera_iopll_141;
ENTITY tech_pll_clk25 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index 1d1ab7193860b20994fa66dc29d010f1a640c6f8..acfe1e870f9e517995e812c639b4723cc0358c0b 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -136,6 +136,19 @@ PACKAGE tech_pll_component_pkg IS
locked : OUT STD_LOGIC
);
END COMPONENT;
+
+ COMPONENT ip_arria10_pll_clk125 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
END tech_pll_component_pkg;
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index d2c493eb1367ea866eb04ac7a2bbfbffc18d4073..c149f89babd3acfd241b30e4716e514f1723738d 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -41,7 +41,7 @@ USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140;
+LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_141;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
diff --git a/libraries/technology/technology_select_pkg.vhd b/libraries/technology/technology_select_pkg.vhd
index d523ac4fb94ae39ca17738f2a87ccf8f3910c87f..9b94b6981ac358a804a91c24cbb0e2d643e306bb 100644
--- a/libraries/technology/technology_select_pkg.vhd
+++ b/libraries/technology/technology_select_pkg.vhd
@@ -30,7 +30,7 @@ USE work.technology_pkg.ALL;
PACKAGE technology_select_pkg IS
- CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
+ --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
+ CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
END technology_select_pkg;
diff --git a/libraries/technology/tse/tech_tse_arria10.vhd b/libraries/technology/tse/tech_tse_arria10.vhd
index d736ebfb4dc7544cb10e69def2966cc178db1414..773dd83d47b5c3ab0f174958652da0a9ef1b0231 100644
--- a/libraries/technology/tse/tech_tse_arria10.vhd
+++ b/libraries/technology/tse/tech_tse_arria10.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_tse_sgmii_lvds_altera_eth_tse_140;
-LIBRARY ip_arria10_tse_sgmii_gx_altera_eth_tse_140;
+LIBRARY ip_arria10_tse_sgmii_lvds_altera_eth_tse_141;
+LIBRARY ip_arria10_tse_sgmii_gx_altera_eth_tse_141;
ENTITY tech_tse_arria10 IS
GENERIC (