From a909ae8ac10806daa3271278cccbb708de2f64d8 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 4 Apr 2024 10:04:43 +0200
Subject: [PATCH] L2SDP-1032, apply vhdl_style assert/report rule
---
.../lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd | 3 +-
.../lofar1/RSP/pft2/src/vhdl/pft_bf.vhd | 3 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd | 24 +-
.../tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd | 12 +-
.../tb/vhdl/tb_lofar2_unb2b_beamformer.vhd | 20 +-
.../tb/vhdl/tb_lofar2_unb2b_filterbank.vhd | 12 +-
.../tb/vhdl/tb_lofar2_unb2b_ring.vhd | 80 +++-
.../tb_disturb2_unb2b_sdp_station_full_wg.vhd | 16 +-
.../tb_lofar2_unb2b_sdp_station_adc.vhd | 12 +-
.../tb_lofar2_unb2b_sdp_station_bf.vhd | 108 ++++--
.../tb_lofar2_unb2b_sdp_station_fsub.vhd | 26 +-
.../tb_lofar2_unb2b_sdp_station_xsub_one.vhd | 34 +-
.../tb_lofar2_unb2b_sdp_station_xsub_ring.vhd | 70 +++-
.../tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd | 4 +-
.../tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd | 8 +-
.../tb/vhdl/tb_lofar2_unb2c_filterbank.vhd | 12 +-
.../tb/vhdl/tb_lofar2_unb2c_ring.vhd | 80 +++-
.../tb_lofar2_unb2c_sdp_station_adc.vhd | 12 +-
.../tb_lofar2_unb2c_sdp_station_adc_jesd.vhd | 34 +-
.../tb_lofar2_unb2c_sdp_station_bf.vhd | 152 ++++++--
.../tb_lofar2_unb2c_sdp_station_bf_ring.vhd | 144 ++++++--
.../tb_lofar2_unb2c_sdp_station_fsub.vhd | 66 +++-
.../tb_lofar2_unb2c_sdp_station_xsub_one.vhd | 42 ++-
...unb2c_sdp_station_xsub_one_xst_offload.vhd | 20 +-
.../tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd | 4 +-
.../libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd | 4 +-
.../lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd | 4 +-
.../sdp/tb/vhdl/tb_sdp_beamformer_output.vhd | 24 +-
.../tb/vhdl/tb_sdp_beamformer_remote_ring.vhd | 8 +-
.../tb/vhdl/tb_sdp_crosslets_remote_ring.vhd | 16 +-
.../vhdl/tb_sdp_crosslets_subband_select.vhd | 50 ++-
.../libraries/sdp/tb/vhdl/tb_sdp_info.vhd | 88 +++--
.../libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd | 347 +++++++++++++-----
.../sdp/tb/vhdl/tb_sdp_statistics_offload.vhd | 24 +-
.../tb/vhdl/tb_rdma_generator.vhd | 63 ++--
.../tb_rdma_packetiser_assemble_header.vhd | 32 +-
.../hardware/lofar2_unb2b_ring_bsp/top.vhd | 4 +-
.../ta2_channel_cross/ta2_channel_cross.vhd | 4 +-
.../ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd | 4 +-
.../tb/vhdl/tb_node_unb1_bn_capture.vhd | 11 +-
.../tb/vhdl/tb_unb1_bn_capture_input.vhd | 16 +-
.../vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd | 4 +-
.../tb_unb1_minimal_qsys_stimuli.vhd | 36 +-
.../tb/vhdl/tb_mms_unb1_board_sens.vhd | 20 +-
.../vhdl/tb_unb1_board_mesh_reorder_bidir.vhd | 24 +-
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 8 +-
.../tb/vhdl/tb_mms_unb2_board_sens.vhd | 20 +-
.../unb2a_test/src/vhdl/unb2a_test.vhd | 12 +-
.../tb/vhdl/tb_mms_unb2_board_sens.vhd | 20 +-
.../unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd | 15 +-
.../unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd | 3 +-
.../tb/vhdl/tb_unb2b_arp_ping.vhd | 15 +-
.../avs2_eth_coe_10/sim/common_pkg.vhd | 16 +-
.../avs2_eth_coe_10/sim/dp_stream_pkg.vhd | 18 +-
.../avs2_eth_coe_10/synth/common_pkg.vhd | 16 +-
.../avs2_eth_coe_10/synth/dp_stream_pkg.vhd | 18 +-
.../avs2_eth_coe_10/sim/common_pkg.vhd | 16 +-
.../avs2_eth_coe_10/sim/dp_stream_pkg.vhd | 18 +-
.../avs2_eth_coe_10/synth/common_pkg.vhd | 16 +-
.../avs2_eth_coe_10/synth/dp_stream_pkg.vhd | 18 +-
.../unb2b_test/src/vhdl/unb2b_test.vhd | 12 +-
.../tb/vhdl/tb_mms_unb2b_board_sens.vhd | 20 +-
.../unb2c_test/src/vhdl/unb2c_test.vhd | 12 +-
.../base/axi4/src/vhdl/axi4_stream_pkg.vhd | 18 +-
.../axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd | 3 +-
.../base/common/src/vhdl/common_counter.vhd | 4 +-
.../base/common/src/vhdl/common_math_pkg.vhd | 4 +-
.../base/common/src/vhdl/common_operation.vhd | 8 +-
libraries/base/common/src/vhdl/common_pkg.vhd | 29 +-
.../common/src/vhdl/common_requantize.vhd | 4 +-
.../base/common/tb/vhdl/tb_common_add_sub.vhd | 4 +-
.../common/tb/vhdl/tb_common_adder_tree.vhd | 4 +-
.../tb_common_create_strobes_from_valid.vhd | 40 +-
.../common/tb/vhdl/tb_common_fanout_tree.vhd | 12 +-
.../base/common/tb/vhdl/tb_common_gcd.vhd | 40 +-
.../base/common/tb/vhdl/tb_common_mem_mux.vhd | 3 +-
.../tb/vhdl/tb_common_operation_tree.vhd | 4 +-
.../tb/vhdl/tb_common_paged_ram_cr_cw.vhd | 6 +-
.../tb/vhdl/tb_common_paged_ram_crw_crw.vhd | 6 +-
.../tb/vhdl/tb_common_paged_ram_rw_rw.vhd | 6 +-
.../base/common/tb/vhdl/tb_common_pkg.vhd | 113 ++++--
.../common/tb/vhdl/tb_common_pulse_delay.vhd | 6 +-
.../common/tb/vhdl/tb_common_shiftram.vhd | 3 +-
.../common/tb/vhdl/tb_common_to_sreal.vhd | 30 +-
.../tb/vhdl/tb_common_variable_delay.vhd | 8 +-
.../tb/vhdl/tb_mms_common_variable_delay.vhd | 8 +-
libraries/base/common/tb/vhdl/tb_resize.vhd | 57 ++-
libraries/base/common/tb/vhdl/tb_round.vhd | 240 +++++++++---
.../tb/vhdl/tb_common_complex_mult.vhd | 12 +-
.../common_mult/tb/vhdl/tb_common_mult.vhd | 16 +-
.../tb/vhdl/tb_common_mult_add2.vhd | 4 +-
.../base/diag/src/vhdl/diag_data_buffer.vhd | 4 +-
.../diag/src/vhdl/diag_data_buffer_dev.vhd | 4 +-
libraries/base/diag/src/vhdl/diag_rx_seq.vhd | 3 +-
.../base/diag/src/vhdl/diag_wg_wideband.vhd | 4 +-
.../base/diag/src/vhdl/mms_diag_rx_seq.vhd | 4 +-
.../base/diag/tb/vhdl/tb_diag_frm_monitor.vhd | 15 +-
libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd | 57 ++-
.../base/diag/tb/vhdl/tb_diag_rx_seq.vhd | 3 +-
.../base/diag/tb/vhdl/tb_diag_wg_wideband.vhd | 52 ++-
.../diag/tb/vhdl/tb_mms_diag_block_gen.vhd | 30 +-
.../base/diag/tb/vhdl/tb_mms_diag_seq.vhd | 16 +-
.../tb/vhdl/tb_diagnostics_trnb_pkg.vhd | 4 +-
.../dp/src/vhdl/dp_block_gen_valid_arr.vhd | 8 +-
.../dp/src/vhdl/dp_block_validate_channel.vhd | 4 +-
.../dp/src/vhdl/dp_bsn_sync_scheduler.vhd | 4 +-
.../base/dp/src/vhdl/dp_calculate_crc.vhd | 3 +-
libraries/base/dp/src/vhdl/dp_concat.vhd | 4 +-
.../base/dp/src/vhdl/dp_concat_field_blk.vhd | 4 +-
.../base/dp/src/vhdl/dp_fifo_from_mm.vhd | 4 +-
libraries/base/dp/src/vhdl/dp_frame_rx.vhd | 4 +-
.../base/dp/src/vhdl/dp_offload_tx_v3.vhd | 4 +-
.../dp/src/vhdl/dp_packet_dec_channel_lo.vhd | 4 +-
.../dp/src/vhdl/dp_packet_enc_channel_lo.vhd | 4 +-
libraries/base/dp/src/vhdl/dp_requantize.vhd | 4 +-
libraries/base/dp/src/vhdl/dp_split.vhd | 4 +-
libraries/base/dp/src/vhdl/dp_stream_pkg.vhd | 18 +-
.../dp/src/vhdl/dp_strobe_total_count.vhd | 8 +-
libraries/base/dp/src/vhdl/dp_unframe.vhd | 2 +-
libraries/base/dp/tb/vhdl/dp_statistics.vhd | 12 +-
.../base/dp/tb/vhdl/tb_dp_block_from_mm.vhd | 16 +-
.../base/dp/tb/vhdl/tb_dp_block_reshape.vhd | 4 +-
.../dp/tb/vhdl/tb_dp_block_reshape_sync.vhd | 48 ++-
.../base/dp/tb/vhdl/tb_dp_block_select.vhd | 68 +++-
.../vhdl/tb_dp_block_validate_bsn_at_sync.vhd | 28 +-
.../tb/vhdl/tb_dp_block_validate_channel.vhd | 120 ++++--
.../dp/tb/vhdl/tb_dp_block_validate_err.vhd | 64 +++-
.../tb/vhdl/tb_dp_block_validate_length.vhd | 80 +++-
.../base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd | 38 +-
.../base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd | 48 ++-
.../base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd | 48 ++-
.../base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd | 44 ++-
.../dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd | 31 +-
.../base/dp/tb/vhdl/tb_dp_calculate_crc.vhd | 6 +-
libraries/base/dp/tb/vhdl/tb_dp_counter.vhd | 12 +-
.../base/dp/tb/vhdl/tb_dp_counter_func.vhd | 12 +-
.../base/dp/tb/vhdl/tb_dp_counter_offset.vhd | 12 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd | 4 +-
.../base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd | 4 +-
.../base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd | 12 +-
.../base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd | 8 +-
libraries/base/dp/tb/vhdl/tb_dp_flush.vhd | 24 +-
libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd | 6 +-
.../base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd | 21 +-
.../base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd | 40 +-
.../base/dp/tb/vhdl/tb_dp_packet_merge.vhd | 8 +-
.../base/dp/tb/vhdl/tb_dp_packetizing.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd | 195 +++++++---
.../base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd | 4 +-
.../base/dp/tb/vhdl/tb_dp_rsn_source.vhd | 44 ++-
.../base/dp/tb/vhdl/tb_dp_selector_arr.vhd | 32 +-
.../dp/tb/vhdl/tb_dp_strobe_total_count.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_dp_switch.vhd | 6 +-
.../base/dp/tb/vhdl/tb_dp_sync_checker.vhd | 24 +-
.../base/dp/tb/vhdl/tb_dp_sync_insert.vhd | 8 +-
.../base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd | 20 +-
.../base/dp/tb/vhdl/tb_dp_sync_recover.vhd | 20 +-
.../base/dp/tb/vhdl/tb_dp_throttle_xon.vhd | 8 +-
.../dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd | 16 +-
.../dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd | 34 +-
.../tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd | 81 ++--
.../base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd | 12 +-
.../dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd | 20 +-
.../tb_mms_dp_force_data_parallel_arr.vhd | 88 +++--
.../vhdl/tb_mms_dp_force_data_serial_arr.vhd | 76 +++-
.../base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd | 20 +-
.../dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd | 20 +-
libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd | 8 +-
.../dp/tb/vhdl/tb_mms_dp_sync_checker.vhd | 16 +-
libraries/base/mm/src/vhdl/mm_bus_comb.vhd | 4 +-
libraries/base/mm/src/vhdl/mm_bus_pipe.vhd | 4 +-
libraries/base/mm/tb/vhdl/mm_file_pkg.vhd | 24 +-
libraries/base/mm/tb/vhdl/tb_mm_bus.vhd | 7 +-
libraries/base/mm/tb/vhdl/tb_mm_file.vhd | 8 +-
.../base/mm/tb/vhdl/tb_mm_master_mux.vhd | 3 +-
.../base/reorder/src/vhdl/reorder_pkg.vhd | 8 +-
.../reorder/src/vhdl/reorder_sequencer.vhd | 24 +-
.../base/reorder/tb/vhdl/reorder_pkg_test.vhd | 12 +-
.../vhdl/tb_reorder_col_wide_row_select.vhd | 24 +-
.../base/ring/tb/vhdl/tb_ring_lane_info.vhd | 16 +-
libraries/base/sens/tb/vhdl/tb_sens.vhd | 3 +-
libraries/base/tst/src/vhdl/tst_input.vhd | 3 +-
libraries/base/uth/src/vhdl/uth_rx.vhd | 8 +-
libraries/base/uth/src/vhdl/uth_tx_tlen.vhd | 3 +-
libraries/base/uth/tb/vhdl/tb_uth.vhd | 3 +-
.../base/uth/tb/vhdl/tb_uth_dp_packet.vhd | 3 +-
.../tb/vhdl/tb_corr_accumulator.vhd | 10 +-
libraries/dsp/fft/src/vhdl/fft_pkg.vhd | 20 +-
.../dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd | 16 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd | 32 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd | 36 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd | 40 +-
.../fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd | 8 +-
libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd | 8 +-
libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd | 12 +-
.../dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd | 20 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd | 24 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd | 16 +-
.../tb/vhdl/tb_fil_ppf_wide_file_data.vhd | 16 +-
.../fringe_stop/src/vhdl/fringe_stop_unit.vhd | 8 +-
.../tb/vhdl/tb_fringe_stop_unit.vhd | 8 +-
.../tb/vhdl/tb_mmf_fringe_stop_unit.vhd | 79 ++--
libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd | 32 +-
.../dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd | 36 +-
libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd | 32 +-
.../iquv/tb/vhdl/tb_iquv_iab_file_data.vhd | 12 +-
.../dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd | 4 +-
libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd | 12 +-
libraries/dsp/si/tb/vhdl/tb_si.vhd | 11 +-
.../dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd | 16 +-
libraries/dsp/st/tb/vhdl/tb_st_acc.vhd | 4 +-
libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd | 24 +-
libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd | 4 +-
libraries/dsp/st/tb/vhdl/tb_st_xst.vhd | 4 +-
.../dsp/verify_pfb/tb_verify_pfb_response.vhd | 4 +-
libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd | 26 +-
libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd | 4 +-
libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd | 24 +-
.../dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd | 60 ++-
libraries/io/aduh/src/vhdl/aduh_pll.vhd | 6 +-
libraries/io/aduh/src/vhdl/lvdsh_pll.vhd | 3 +-
libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd | 6 +-
.../io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd | 8 +-
libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd | 6 +-
.../io/aduh/tb/vhdl/tb_aduh_power_sum.vhd | 8 +-
libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd | 12 +-
.../io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd | 8 +-
libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd | 4 +-
.../io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd | 80 +++-
libraries/io/ddr/src/vhdl/io_ddr.vhd | 4 +-
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd | 43 ++-
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 3 +-
libraries/io/ddr3/src/vhdl/ddr3_seq.vhd | 4 +-
libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd | 12 +-
libraries/io/eth/src/vhdl/eth_tester_rx.vhd | 4 +-
libraries/io/eth/tb/vhdl/tb_eth.vhd | 15 +-
libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd | 12 +-
libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd | 64 +++-
.../eth/tb/vhdl/tb_eth_ip_header_checksum.vhd | 28 +-
.../io/eth/tb/vhdl/tb_eth_stream_udp.vhd | 48 ++-
libraries/io/eth/tb/vhdl/tb_eth_tester.vhd | 103 ++++--
.../io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd | 84 +++--
.../io/eth/tb/vhdl/tb_eth_udp_offload.vhd | 4 +-
libraries/io/eth/tb/vhdl/tb_tb_eth.vhd | 3 +-
libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd | 3 +-
.../eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd | 3 +-
libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd | 15 +-
libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd | 3 +-
libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd | 12 +-
.../tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd | 12 +-
.../tb/vhdl/tb_i2c_commander_unb2_sens.vhd | 12 +-
libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd | 10 +-
libraries/io/mdio/src/vhdl/mdio_phy.vhd | 4 +-
libraries/io/mdio/tb/vhdl/mmd_slave.vhd | 7 +-
libraries/io/mdio/tb/vhdl/tb_mdio.vhd | 6 +-
libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd | 12 +-
.../io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd | 6 +-
libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd | 6 +-
.../io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd | 3 +-
libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd | 80 +++-
libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd | 48 ++-
.../io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd | 3 +-
.../tb/vhdl/tb_tb_tr_nonbonded.vhd | 7 +-
.../tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd | 22 +-
.../io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd | 3 +-
libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd | 10 +-
.../tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd | 4 +-
.../10gbase_r/tb_tech_10gbase_r.vhd | 3 +-
.../ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd | 6 +-
.../ram/ip_agi027_1e1v_ram_cr_cw.vhd | 4 +-
.../ram/ip_agi027_1e1v_ram_crk_cw.vhd | 4 +-
.../ram/ip_agi027_1e1v_ram_r_w.vhd | 4 +-
.../ram/ip_agi027_1e1v_ram_rw_rw.vhd | 4 +-
.../ddio/sim/tb_ip_arria10_ddio_1.vhd | 6 +-
.../ip_arria10/ram/ip_arria10_ram_cr_cw.vhd | 4 +-
.../ip_arria10/ram/ip_arria10_ram_crw_crw.vhd | 4 +-
.../ip_arria10/ram/ip_arria10_ram_r_w.vhd | 4 +-
.../tb_ip_arria10_tse_sgmii_gx.vhd | 53 ++-
.../tb_ip_arria10_tse_sgmii_lvds.vhd | 53 ++-
.../ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd | 6 +-
.../ram/ip_arria10_e1sg_ram_cr_cw.vhd | 4 +-
.../ram/ip_arria10_e1sg_ram_crw_crw.vhd | 4 +-
.../ram/ip_arria10_e1sg_ram_r_w.vhd | 4 +-
.../tb_ip_arria10_e1sg_tse_sgmii_gx.vhd | 53 ++-
.../tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd | 53 ++-
.../ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd | 6 +-
.../ram/ip_arria10_e2sg_ram_cr_cw.vhd | 4 +-
.../ram/ip_arria10_e2sg_ram_crw_crw.vhd | 4 +-
.../ram/ip_arria10_e2sg_ram_r_w.vhd | 4 +-
.../tb_ip_arria10_e2sg_tse_sgmii_gx.vhd | 53 ++-
.../tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd | 53 ++-
.../ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd | 6 +-
.../ram/ip_arria10_e3sge3_ram_cr_cw.vhd | 4 +-
.../ram/ip_arria10_e3sge3_ram_crw_crw.vhd | 4 +-
.../ram/ip_arria10_e3sge3_ram_r_w.vhd | 4 +-
.../tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd | 53 ++-
.../tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd | 53 ++-
.../phy_xaui/tb_ip_stratixiv_phy_xaui.vhd | 10 +-
.../tb_ip_stratixiv_tse_sgmii_lvds.vhd | 53 ++-
.../ram/ip_ultrascale_ram_cr_cw.vhd | 8 +-
.../ram/ip_ultrascale_ram_crw_crw.vhd | 8 +-
.../technology/jesd204b/tb_tech_jesd204b.vhd | 10 +-
.../jesd204b/tb_tech_jesd204b_v2.vhd | 10 +-
.../technology/mac_10g/tb_tb_tech_mac_10g.vhd | 3 +-
.../mac_10g/tb_tech_mac_10g_pkg.vhd | 52 ++-
.../tb_tech_mac_10g_simulation_end.vhd | 6 +-
.../tb_tech_mac_10g_verify_rx_at_eop.vhd | 10 +-
.../tb_tech_mac_10g_verify_rx_pkt_cnt.vhd | 12 +-
libraries/technology/technology_pkg.vhd | 3 +-
.../transceiver/sim_transceiver_gx.vhd | 4 +-
.../transceiver/tb_sim_transceiver_serdes.vhd | 4 +-
libraries/technology/tse/tb_tb_tech_tse.vhd | 3 +-
libraries/technology/tse/tb_tech_tse.vhd | 15 +-
libraries/technology/tse/tb_tech_tse_pkg.vhd | 44 ++-
.../technology/tse/tb_tech_tse_with_setup.vhd | 19 +-
315 files changed, 5165 insertions(+), 1915 deletions(-)
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index dbf3d35cf7..3b1780f0f2 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -352,5 +352,6 @@ begin
end process;
end generate;
- assert c_regbank_size >= c_pipeline severity FAILURE;
+ assert c_regbank_size >= c_pipeline
+ severity FAILURE;
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index 15716280cd..e6da4e6d2f 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -399,5 +399,6 @@ begin
end process;
end generate;
- assert c_regbank_size >= c_pipeline severity FAILURE;
+ assert c_regbank_size >= c_pipeline
+ severity FAILURE;
end rtl;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
index 7c4aa160e9..4b63bb5663 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
@@ -491,8 +491,12 @@ begin
diff_max_fft_re <= largest(abs(diff_fft_re), diff_max_fft_re);
diff_max_fft_im <= largest(abs(diff_fft_im), diff_max_fft_im);
- assert diff_max_fft_re <= c_diff_max report "FFT re output differs to much from reference data" severity ERROR;
- assert diff_max_fft_im <= c_diff_max report "FFT im output differs to much from reference data" severity ERROR;
+ assert diff_max_fft_re <= c_diff_max
+ report "FFT re output differs to much from reference data"
+ severity ERROR;
+ assert diff_max_fft_im <= c_diff_max
+ report "FFT im output differs to much from reference data"
+ severity ERROR;
p_report : process(diff_rdy)
begin
@@ -521,10 +525,18 @@ begin
diff_max_y_re <= largest(abs(diff_y_re), diff_max_y_re);
diff_max_y_im <= largest(abs(diff_y_im), diff_max_y_im);
- assert diff_max_x_re <= c_diff_max report "FFT X re output differs too much from reference data" severity ERROR;
- assert diff_max_x_im <= c_diff_max report "FFT X im output differs too much from reference data" severity ERROR;
- assert diff_max_y_re <= c_diff_max report "FFT Y re output differs too much from reference data" severity ERROR;
- assert diff_max_y_im <= c_diff_max report "FFT Y im output differs too much from reference data" severity ERROR;
+ assert diff_max_x_re <= c_diff_max
+ report "FFT X re output differs too much from reference data"
+ severity ERROR;
+ assert diff_max_x_im <= c_diff_max
+ report "FFT X im output differs too much from reference data"
+ severity ERROR;
+ assert diff_max_y_re <= c_diff_max
+ report "FFT Y re output differs too much from reference data"
+ severity ERROR;
+ assert diff_max_y_im <= c_diff_max
+ report "FFT Y im output differs too much from reference data"
+ severity ERROR;
p_report : process(diff_rdy)
begin
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
index 470c7ab175..65df1495f0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -266,7 +266,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -320,8 +322,12 @@ begin
-- Convert UNSIGNED sp_power_sum to REAL
v_sp_power_sum := real(real(to_integer(sp_power_sum(61 downto 30))) * real(2**30) + real(to_integer(sp_power_sum(29 downto 0))));
- assert v_sp_power_sum > c_lo_factor * c_exp_wg_power_sp report "Wrong SP power for SP 0" severity ERROR;
- assert v_sp_power_sum < c_hi_factor * c_exp_wg_power_sp report "Wrong SP power for SP 0" severity ERROR;
+ assert v_sp_power_sum > c_lo_factor * c_exp_wg_power_sp
+ report "Wrong SP power for SP 0"
+ severity ERROR;
+ assert v_sp_power_sum < c_hi_factor * c_exp_wg_power_sp
+ report "Wrong SP power for SP 0"
+ severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index 38c9c29ca5..c8a64db8c3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -362,7 +362,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -503,8 +505,12 @@ begin
-- verify if subband power and beamlet power are the same. This is expected because we only use 1 WG input and the BF weights have unit value.
-- the difference should not be larger than 0.5% (+/- 2^13 for low values)
- assert v_sp_beamlet_power > 0.995 * v_sp_subband_power - 2.0**13 report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal" severity ERROR;
- assert v_sp_beamlet_power < 1.005 * v_sp_subband_power + 2.0**13 report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal" severity ERROR;
+ assert v_sp_beamlet_power > 0.995 * v_sp_subband_power - 2.0**13
+ report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal"
+ severity ERROR;
+ assert v_sp_beamlet_power < 1.005 * v_sp_subband_power + 2.0**13
+ report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal"
+ severity ERROR;
end if;
end loop;
@@ -526,8 +532,12 @@ begin
---------------------------------------------------------------------------
-- Verify 10GbE UDP offload
---------------------------------------------------------------------------
- assert beamlet_arr2_re(c_exp_beamlet_index) = c_exp_beamlet_re report "Wrong 10GbE output (re)" severity ERROR;
- assert beamlet_arr2_im(c_exp_beamlet_index) = c_exp_beamlet_im report "Wrong 10GbE output (im)" severity ERROR;
+ assert beamlet_arr2_re(c_exp_beamlet_index) = c_exp_beamlet_re
+ report "Wrong 10GbE output (re)"
+ severity ERROR;
+ assert beamlet_arr2_im(c_exp_beamlet_index) = c_exp_beamlet_im
+ report "Wrong 10GbE output (im)"
+ severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
index a0ade62951..fcde0cefe1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
@@ -290,7 +290,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -345,8 +347,12 @@ begin
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
- assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
- assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
+ assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
+ assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
---------------------------------------------------------------------------
-- Read subband statistics
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index a41b295e62..cd14f27ce5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -298,22 +298,38 @@ begin
for I in 0 to c_nof_lanes - 1 loop
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
end loop;
----------------------------------------------------------------------------
@@ -331,33 +347,57 @@ begin
-- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
if (I mod 2 = 0 and (RN + 1) mod g_nof_rn = J) or (I mod 2 = 1 and (RN + g_nof_rn - 1) mod g_nof_rn = J) then
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '1'
+ report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
else
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '0'
+ report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
end if;
if RN = J then -- No packets received from itself as the previous RN should have removed it from the ring.
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '1'
+ report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
else
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '0'
+ report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
end if;
end loop;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
index b84d16cc0e..9291484adc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
@@ -362,7 +362,9 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_bf_scale, v_offset + 0, rd_data, tb_clk);
rd_beamlet_scale <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
- assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale report "Wrong MM read beamlet_scale for beamset " & natural'image(bset) severity ERROR;
+ assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale
+ report "Wrong MM read beamlet_scale for beamset " & natural'image(bset)
+ severity ERROR;
end loop;
----------------------------------------------------------------------------
@@ -401,7 +403,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -515,8 +519,12 @@ begin
print_str(". c_exp_beamlet_im_sp_2 = " & int_to_str(integer(c_exp_beamlet_im_sp_2)));
-- WG at subband center will yield same subband value in every subband period
- assert signed(beamlet_arr2_re(c_exp_beamlet_index)) = c_exp_beamlet_re_sp_0 report "Wrong 10GbE beamlet output /= c_exp_beamlet_re_sp_0 in beamset 0" severity ERROR;
- assert signed(beamlet_arr2_im(c_exp_beamlet_index)) = c_exp_beamlet_im_sp_0 report "Wrong 10GbE beamlet output /= c_exp_beamlet_im_sp_0 in beamset 0" severity ERROR;
+ assert signed(beamlet_arr2_re(c_exp_beamlet_index)) = c_exp_beamlet_re_sp_0
+ report "Wrong 10GbE beamlet output /= c_exp_beamlet_re_sp_0 in beamset 0"
+ severity ERROR;
+ assert signed(beamlet_arr2_im(c_exp_beamlet_index)) = c_exp_beamlet_im_sp_0
+ report "Wrong 10GbE beamlet output /= c_exp_beamlet_im_sp_0 in beamset 0"
+ severity ERROR;
-- WG at subband edge will change phase 180 degrees in every subband period, so expect factor +-1
assert signed(beamlet_arr2_re(c_exp_beamlet_index_os)) = c_exp_beamlet_re_sp_2 or
signed(beamlet_arr2_re(c_exp_beamlet_index_os)) = -c_exp_beamlet_re_sp_2 report "Wrong 10GbE beamlet output /= c_exp_beamlet_re_sp_2 in beamset 1 (shifted subbands)" severity ERROR;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
index eefec65249..823bc93446 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -261,7 +261,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -288,8 +290,12 @@ begin
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
- assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
- assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
+ assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
+ assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index 3eb4663984..fc2fc3c7bd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -549,9 +549,15 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_sdp_info, 0, rd_data, tb_clk); rd_sdp_info.block_period <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
-- . Verify read
- assert c_exp_sdp_info.f_adc = rd_sdp_info.f_adc report "Wrong MM read SDP info f_adc" severity ERROR;
- assert c_exp_sdp_info.fsub_type = rd_sdp_info.fsub_type report "Wrong MM read SDP info fsub_type" severity ERROR;
- assert c_exp_sdp_info.block_period = rd_sdp_info.block_period report "Wrong MM read SDP info block_period" severity ERROR;
+ assert c_exp_sdp_info.f_adc = rd_sdp_info.f_adc
+ report "Wrong MM read SDP info f_adc"
+ severity ERROR;
+ assert c_exp_sdp_info.fsub_type = rd_sdp_info.fsub_type
+ report "Wrong MM read SDP info fsub_type"
+ severity ERROR;
+ assert c_exp_sdp_info.block_period = rd_sdp_info.block_period
+ report "Wrong MM read SDP info block_period"
+ severity ERROR;
------------------------------------------------------------------------------
---- Set and check BF per beamset
@@ -567,7 +573,9 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_bf_scale, v_offset + 0, rd_data, tb_clk);
rd_beamlet_scale <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
- assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale report "Wrong MM read beamlet_scale for beamset " & natural'image(bset) severity ERROR;
+ assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale
+ report "Wrong MM read beamlet_scale for beamset " & natural'image(bset)
+ severity ERROR;
-- CEP beamlet output header
-- c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := (
@@ -631,12 +639,24 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
-- . verify read
- assert unsigned(rd_cep_eth_src_mac) = 0 report "Wrong MM read rd_cep_eth_src_mac != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_ip_src_addr) = 0 report "Wrong MM read rd_cep_ip_src_addr != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_udp_src_port) = 0 report "Wrong MM read rd_cep_udp_src_port != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_eth_dst_mac) = 0 report "Wrong MM read rd_cep_eth_dst_mac != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_ip_dst_addr) = 0 report "Wrong MM read rd_cep_ip_dst_addr != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_udp_dst_port) = 0 report "Wrong MM read rd_cep_udp_dst_port != 0 for beamset " & natural'image(bset) severity ERROR;
+ assert unsigned(rd_cep_eth_src_mac) = 0
+ report "Wrong MM read rd_cep_eth_src_mac != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_ip_src_addr) = 0
+ report "Wrong MM read rd_cep_ip_src_addr != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_udp_src_port) = 0
+ report "Wrong MM read rd_cep_udp_src_port != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_eth_dst_mac) = 0
+ report "Wrong MM read rd_cep_eth_dst_mac != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_ip_dst_addr) = 0
+ report "Wrong MM read rd_cep_ip_dst_addr != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_udp_dst_port) = 0
+ report "Wrong MM read rd_cep_udp_dst_port != 0 for beamset " & natural'image(bset)
+ severity ERROR;
-- Write tb defaults
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 39, TO_UINT(c_cep_eth_src_mac(47 downto 32)), tb_clk);
@@ -660,12 +680,24 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
-- . verify read back
- assert rd_cep_eth_src_mac = c_cep_eth_src_mac report "Wrong MM read rd_cep_eth_src_mac for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_ip_src_addr = c_cep_ip_src_addr report "Wrong MM read rd_cep_ip_src_addr for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_udp_src_port = c_cep_udp_src_port report "Wrong MM read rd_cep_udp_src_port for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac report "Wrong MM read rd_cep_eth_dst_mac for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr report "Wrong MM read rd_cep_ip_dst_addr for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port report "Wrong MM read rd_cep_udp_dst_port for beamset " & natural'image(bset) severity ERROR;
+ assert rd_cep_eth_src_mac = c_cep_eth_src_mac
+ report "Wrong MM read rd_cep_eth_src_mac for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_ip_src_addr = c_cep_ip_src_addr
+ report "Wrong MM read rd_cep_ip_src_addr for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_udp_src_port = c_cep_udp_src_port
+ report "Wrong MM read rd_cep_udp_src_port for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac
+ report "Wrong MM read rd_cep_eth_dst_mac for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr
+ report "Wrong MM read rd_cep_ip_dst_addr for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port
+ report "Wrong MM read rd_cep_udp_dst_port for beamset " & natural'image(bset)
+ severity ERROR;
----------------------------------------------------------------------------
-- Enable beamlet UDP offload (dp_xonoff)
@@ -708,7 +740,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -979,8 +1013,12 @@ begin
---------------------------------------------------------------------------
-- verify expected subband power based on WG power
- assert sp_subband_sst > c_stat_lo_factor * c_exp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
- assert sp_subband_sst < c_stat_hi_factor * c_exp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
+ assert sp_subband_sst > c_stat_lo_factor * c_exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
+ assert sp_subband_sst < c_stat_hi_factor * c_exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
-- verify expected beamlet power based on WG power and BF weigths
--
@@ -993,10 +1031,18 @@ begin
-- g_sp = Y --> w_yy --> beamlet Y = c_exp_beamlet_bst
--
for U in 0 to c_sdp_N_beamsets - 1 loop
- assert pol_beamlet_bst_X_arr(U) > c_stat_lo_factor * c_exp_beamlet_bst report "Wrong beamlet power for X in beamset " & natural'image(U) severity ERROR;
- assert pol_beamlet_bst_X_arr(U) < c_stat_hi_factor * c_exp_beamlet_bst report "Wrong beamlet power for X in beamset " & natural'image(U) severity ERROR;
- assert pol_beamlet_bst_Y_arr(U) > c_stat_lo_factor * c_exp_beamlet_bst report "Wrong beamlet power for Y in beamset " & natural'image(U) severity ERROR;
- assert pol_beamlet_bst_Y_arr(U) < c_stat_hi_factor * c_exp_beamlet_bst report "Wrong beamlet power for Y in beamset " & natural'image(U) severity ERROR;
+ assert pol_beamlet_bst_X_arr(U) > c_stat_lo_factor * c_exp_beamlet_bst
+ report "Wrong beamlet power for X in beamset " & natural'image(U)
+ severity ERROR;
+ assert pol_beamlet_bst_X_arr(U) < c_stat_hi_factor * c_exp_beamlet_bst
+ report "Wrong beamlet power for X in beamset " & natural'image(U)
+ severity ERROR;
+ assert pol_beamlet_bst_Y_arr(U) > c_stat_lo_factor * c_exp_beamlet_bst
+ report "Wrong beamlet power for Y in beamset " & natural'image(U)
+ severity ERROR;
+ assert pol_beamlet_bst_Y_arr(U) < c_stat_hi_factor * c_exp_beamlet_bst
+ report "Wrong beamlet power for Y in beamset " & natural'image(U)
+ severity ERROR;
end loop;
---------------------------------------------------------------------------
@@ -1004,10 +1050,18 @@ begin
---------------------------------------------------------------------------
v_re := TO_SINT(rx_packet_list_re(c_exp_g_beamlet_index)); v_re_exp := c_exp_beamlet_output_re;
v_im := TO_SINT(rx_packet_list_im(c_exp_g_beamlet_index)); v_im_exp := c_exp_beamlet_output_im;
- assert v_re > integer(v_re_exp) - c_beamlet_output_delta report "Wrong 10GbE output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_re < integer(v_re_exp) + c_beamlet_output_delta report "Wrong 10GbE output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_im > integer(v_im_exp) - c_beamlet_output_delta report "Wrong 10GbE output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
- assert v_im < integer(v_im_exp) + c_beamlet_output_delta report "Wrong 10GbE output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
+ assert v_re > integer(v_re_exp) - c_beamlet_output_delta
+ report "Wrong 10GbE output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_re < integer(v_re_exp) + c_beamlet_output_delta
+ report "Wrong 10GbE output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_im > integer(v_im_exp) - c_beamlet_output_delta
+ report "Wrong 10GbE output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
+ assert v_im < integer(v_im_exp) + c_beamlet_output_delta
+ report "Wrong 10GbE output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index 01b7d1a62a..aad09fffa4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -355,7 +355,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -448,7 +450,8 @@ begin
if sp_subband_sst > c_eps and v_power > c_eps then
sp_subband_sst_leakage_snr_dB <= 10.0 * LOG10(sp_subband_sst / v_power);
elsif g_read_all_SST then
- report "Wrong, zero leakage is unexpected for SP-" & natural'image(g_sp) severity ERROR;
+ report "Wrong, zero leakage is unexpected for SP-" & natural'image(g_sp)
+ severity ERROR;
end if;
-- The sp_subband_sst_crosstalk shows how much power from one WPFB input cross talks
@@ -459,7 +462,8 @@ begin
if sp_subband_sst > c_eps and v_power > c_eps then
sp_subband_sst_crosstalk_snr_dB <= 10.0 * LOG10(sp_subband_sst / v_power);
elsif g_read_all_SST then
- report "Zero crosstalk for SP-" & natural'image(g_sp) severity NOTE;
+ report "Zero crosstalk for SP-" & natural'image(g_sp)
+ severity NOTE;
end if;
proc_common_wait_some_cycles(tb_clk, 10);
@@ -506,13 +510,21 @@ begin
-- Verify SST
---------------------------------------------------------------------------
-- verify expected subband power based on WG power
- assert sp_subband_sst > c_lo_factor * exp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
- assert sp_subband_sst < c_hi_factor * exp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
+ assert sp_subband_sst > c_lo_factor * exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
+ assert sp_subband_sst < c_hi_factor * exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
if g_read_all_SST then
-- Verify expected SNR quality measures
- assert sp_subband_sst_leakage = 0.0 or sp_subband_sst_leakage_snr_dB > c_exp_subband_sst_leakage_snr_dB report "Wrong too much leakage for SP " & natural'image(g_sp) severity ERROR;
- assert sp_subband_sst_crosstalk = 0.0 or sp_subband_sst_crosstalk_snr_dB > c_exp_subband_sst_crosstalk_snr_dB report "Wrong too much crosstalk for SP " & natural'image(g_sp) severity ERROR;
+ assert sp_subband_sst_leakage = 0.0 or sp_subband_sst_leakage_snr_dB > c_exp_subband_sst_leakage_snr_dB
+ report "Wrong too much leakage for SP " & natural'image(g_sp)
+ severity ERROR;
+ assert sp_subband_sst_crosstalk = 0.0 or sp_subband_sst_crosstalk_snr_dB > c_exp_subband_sst_crosstalk_snr_dB
+ report "Wrong too much crosstalk for SP " & natural'image(g_sp)
+ severity ERROR;
end if;
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index 3902a64fd6..30aaa35d78 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -277,7 +277,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -328,28 +330,46 @@ begin
-- Check real values of even indices
if v_C = 0 and v_A_even = 0 and v_B_even = 0 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0))
+ report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check real values of odd indices
if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex))
+ report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check real values of even correlated with odd indices
if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex))
+ report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
-- Check im values of even indices
if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1)))
+ report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check im values of odd indices
if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1)))
+ report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check im values of even correlated with odd indices
if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1)))
+ report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check if values are > 0
if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index 40bdccebcd..b058a52c3d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -355,7 +355,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
for RN in 0 to c_nof_rn - 1 loop
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk); -- first write low then high part
@@ -412,28 +414,46 @@ begin
-- Check real values of even indices
if v_C = 0 and v_A_even = 0 and v_B_even = 0 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0))
+ report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check real values of odd indices
if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex))
+ report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check real values of even correlated with odd indices
if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex))
+ report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
-- Check im values of even indices
if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1)))
+ report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check im values of odd indices
if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1)))
+ report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check im values of even correlated with odd indices
if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1)))
+ report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check if values are > 0
if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
@@ -445,30 +465,42 @@ begin
for RN in 0 to c_nof_rn - 1 loop
for J in 0 to c_P_sq - 1 loop -- bsn_monitor index
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 0, rd_data, tb_clk); -- status bits
- report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 1, rd_data, tb_clk); -- bsn at sync
- report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 3, rd_data, tb_clk); -- nof_sop
- report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 4, rd_data, tb_clk); -- nof_valid
- report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 5, rd_data, tb_clk); -- nof_err
- report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 6, rd_data, tb_clk); -- latency
- report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "."
+ severity NOTE;
end loop;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 0, rd_data, tb_clk); -- status bits
- report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 1, rd_data, tb_clk); -- bsn at sync
- report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 3, rd_data, tb_clk); -- nof_sop
- report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 4, rd_data, tb_clk); -- nof_valid
- report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 5, rd_data, tb_clk); -- nof_err
- report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "."
+ severity NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 6, rd_data, tb_clk); -- latency
- report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "."
+ severity NOTE;
end loop;
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
index a057ddef1e..769c5df7b6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -224,7 +224,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 2b57c8af91..9642373d92 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -254,7 +254,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & natural'image(v_bsn) & " > " & natural'image(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & natural'image(v_bsn) & " > " & natural'image(c_bsn_start_wg)
+ severity ERROR;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -383,7 +385,9 @@ begin
-----------------------------------------------------------------------------------------------------------------------------
tb_end <= '1';
- assert false report "Test: OK" severity FAILURE;
+ assert false
+ report "Test: OK"
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
index 260d1427fd..a270960bda 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
@@ -290,7 +290,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -345,8 +347,12 @@ begin
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
- assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
- assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
+ assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
+ assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
---------------------------------------------------------------------------
-- Read subband statistics
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
index 60dc7bbea0..86e179c82e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
@@ -290,22 +290,38 @@ begin
for I in 0 to c_nof_lanes - 1 loop
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1."
+ severity ERROR;
end loop;
----------------------------------------------------------------------------
@@ -323,33 +339,57 @@ begin
-- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
if (I mod 2 = 0 and (RN + 1) mod g_nof_rn = J) or (I mod 2 = 1 and (RN + g_nof_rn - 1) mod g_nof_rn = J) then
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '1'
+ report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
else
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '0'
+ report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
end if;
if RN = J then -- No packets received from itself as the previous RN should have removed it from the ring.
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '1'
+ report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
else
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
- assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert rd_data(2) = '0'
+ report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
- assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_bsn_at_sync
+ report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
- assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_sop
+ report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
- assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = c_exp_nof_valid
+ report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
- assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3."
+ severity ERROR;
end if;
end loop;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
index e94d9e9a29..5d14bdcbe6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
@@ -243,7 +243,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -270,8 +272,12 @@ begin
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
- assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
- assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
+ assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
+ assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
index da2dc05893..8ae5191ce5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
@@ -537,7 +537,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -568,9 +570,11 @@ begin
-----------------------------------------------------------------------
if I < c_nof_jesd204b_tx then
assert unsigned(reg_jesd204b_rx_err_enable) = tech_jesd204b_field_rx_err_enable_reset
- report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_enable)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset) severity ERROR;
+ report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_enable)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset)
+ severity ERROR;
assert unsigned(reg_jesd204b_rx_err_link_reinit) = tech_jesd204b_field_rx_err_link_reinit_reset
- report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_link_reinit)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset) severity ERROR;
+ report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_link_reinit)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset)
+ severity ERROR;
end if;
end loop;
@@ -589,8 +593,12 @@ begin
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
- assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
- assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
+ assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
+ assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0
+ report "Wrong SP power for SP 0"
+ severity ERROR;
-- Try to reset via JESD_CTRL. This JESD_CTRL should be ignored.
-- Note: Awkward way to set MSbit without negative integer warning, using TO_SINT(v_word).
@@ -605,7 +613,9 @@ begin
pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w - 1 downto 0);
pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
proc_common_wait_some_cycles(tb_clk, 1);
- assert pio_jesd_ctrl_reset = '0' report "JESD_CTRL reset should be ignored when BSN source is on." severity ERROR;
+ assert pio_jesd_ctrl_reset = '0'
+ report "JESD_CTRL reset should be ignored when BSN source is on."
+ severity ERROR;
-- remove JESD_CTRL reset
v_word := (others => '0');
v_word(c_sdp_jesd_ctrl_reset_bi) := '0'; -- reset
@@ -645,7 +655,9 @@ begin
pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w - 1 downto 0);
pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
proc_common_wait_some_cycles(tb_clk, 1);
- assert pio_jesd_ctrl_reset = '1' report "JESD_CTRL reset should be applied when BSN source is off." severity ERROR;
+ assert pio_jesd_ctrl_reset = '1'
+ report "JESD_CTRL reset should be applied when BSN source is off."
+ severity ERROR;
wait for 1 us;
-- Read Rx JESD_204B IP status during reset
@@ -662,7 +674,9 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_dp_shiftram, 0, rd_data, tb_clk);
rd_input_delay <= TO_UINT(rd_data);
proc_common_wait_some_cycles(tb_clk, 1);
- assert rd_input_delay = v_exp_input_delay report "wrong rd_input_delay during JESD reset." severity ERROR;
+ assert rd_input_delay = v_exp_input_delay
+ report "wrong rd_input_delay during JESD reset."
+ severity ERROR;
-- Hold JESD_CTRL reset for > one sync period, so also during a JESD204B_SYSREF pulse,
-- to see that JESD_CTRL reset stops JESD204B OUT rx_sysref too.
@@ -683,7 +697,9 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_dp_shiftram, 0, rd_data, tb_clk);
rd_input_delay <= TO_UINT(rd_data);
proc_common_wait_some_cycles(tb_clk, 1);
- assert rd_input_delay = v_exp_input_delay report "wrong rd_input_delay after JESD reset." severity ERROR;
+ assert rd_input_delay = v_exp_input_delay
+ report "wrong rd_input_delay after JESD reset."
+ severity ERROR;
-- Wait for a JESD204B_SYSREF pulse
wait for c_pps_period;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index 5961e34066..c4f00556fd 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -728,9 +728,15 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_sdp_info, 0, rd_data, tb_clk); rd_sdp_info.block_period <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
-- . Verify read
- assert c_exp_sdp_info.f_adc = rd_sdp_info.f_adc report "Wrong MM read SDP info f_adc" severity ERROR;
- assert c_exp_sdp_info.fsub_type = rd_sdp_info.fsub_type report "Wrong MM read SDP info fsub_type" severity ERROR;
- assert c_exp_sdp_info.block_period = rd_sdp_info.block_period report "Wrong MM read SDP info block_period" severity ERROR;
+ assert c_exp_sdp_info.f_adc = rd_sdp_info.f_adc
+ report "Wrong MM read SDP info f_adc"
+ severity ERROR;
+ assert c_exp_sdp_info.fsub_type = rd_sdp_info.fsub_type
+ report "Wrong MM read SDP info fsub_type"
+ severity ERROR;
+ assert c_exp_sdp_info.block_period = rd_sdp_info.block_period
+ report "Wrong MM read SDP info block_period"
+ severity ERROR;
------------------------------------------------------------------------------
---- Set and check BF per beamset
@@ -748,7 +754,9 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_bf_scale, v_offset + 0, rd_data, tb_clk);
rd_beamlet_scale <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
- assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale report "Wrong MM read beamlet_scale for beamset " & natural'image(bset) severity ERROR;
+ assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale
+ report "Wrong MM read beamlet_scale for beamset " & natural'image(bset)
+ severity ERROR;
----------------------------------------------------------------------------
-- Set CEP beamlets output MAC,IP,UDP port
@@ -815,12 +823,24 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
-- . verify read
- assert unsigned(rd_cep_eth_src_mac) = 0 report "Wrong MM read rd_cep_eth_src_mac != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_ip_src_addr) = 0 report "Wrong MM read rd_cep_ip_src_addr != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_udp_src_port) = 0 report "Wrong MM read rd_cep_udp_src_port != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_eth_dst_mac) = 0 report "Wrong MM read rd_cep_eth_dst_mac != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_ip_dst_addr) = 0 report "Wrong MM read rd_cep_ip_dst_addr != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_udp_dst_port) = 0 report "Wrong MM read rd_cep_udp_dst_port != 0 for beamset " & natural'image(bset) severity ERROR;
+ assert unsigned(rd_cep_eth_src_mac) = 0
+ report "Wrong MM read rd_cep_eth_src_mac != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_ip_src_addr) = 0
+ report "Wrong MM read rd_cep_ip_src_addr != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_udp_src_port) = 0
+ report "Wrong MM read rd_cep_udp_src_port != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_eth_dst_mac) = 0
+ report "Wrong MM read rd_cep_eth_dst_mac != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_ip_dst_addr) = 0
+ report "Wrong MM read rd_cep_ip_dst_addr != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_udp_dst_port) = 0
+ report "Wrong MM read rd_cep_udp_dst_port != 0 for beamset " & natural'image(bset)
+ severity ERROR;
-- Write tb defaults
-- . Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on c_gn_index
@@ -880,19 +900,39 @@ begin
proc_common_wait_some_cycles(tb_clk, 1);
-- . verify read back source MAC/IP/UDP
- assert rd_cep_eth_src_mac = c_cep_eth_src_mac report "Wrong MM read rd_cep_eth_src_mac for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_ip_src_addr = c_cep_ip_src_addr report "Wrong MM read rd_cep_ip_src_addr for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_udp_src_port = c_cep_udp_src_port report "Wrong MM read rd_cep_udp_src_port for beamset " & natural'image(bset) severity ERROR;
+ assert rd_cep_eth_src_mac = c_cep_eth_src_mac
+ report "Wrong MM read rd_cep_eth_src_mac for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_ip_src_addr = c_cep_ip_src_addr
+ report "Wrong MM read rd_cep_ip_src_addr for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_udp_src_port = c_cep_udp_src_port
+ report "Wrong MM read rd_cep_udp_src_port for beamset " & natural'image(bset)
+ severity ERROR;
-- . verify read back destination MAC/IP/UDP
- assert rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac report "Wrong MM read rd_cep_eth_dst_mac for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr report "Wrong MM read rd_cep_ip_dst_addr for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port report "Wrong MM read rd_cep_udp_dst_port for beamset " & natural'image(bset) severity ERROR;
+ assert rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac
+ report "Wrong MM read rd_cep_eth_dst_mac for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr
+ report "Wrong MM read rd_cep_ip_dst_addr for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port
+ report "Wrong MM read rd_cep_udp_dst_port for beamset " & natural'image(bset)
+ severity ERROR;
if c_nof_bdo_destinations_max > 1 then
-- . Verify read back nof destinations info
- assert rd_nof_destinations = c_nof_bdo_destinations report "Wrong MM read rd_nof_destinations for beamset " & natural'image(bset) severity ERROR;
- assert rd_nof_destinations_act = c_nof_bdo_destinations report "Wrong MM read rd_nof_destinations_act for beamset " & natural'image(bset) severity ERROR;
- assert rd_nof_destinations_max = c_nof_bdo_destinations_max report "Wrong MM read rd_nof_destinations_max for beamset " & natural'image(bset) severity ERROR;
- assert rd_nof_blocks_per_packet = c_sdp_cep_nof_blocks_per_packet report "Wrong MM read rd_nof_blocks_per_packet for beamset " & natural'image(bset) severity ERROR;
+ assert rd_nof_destinations = c_nof_bdo_destinations
+ report "Wrong MM read rd_nof_destinations for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_nof_destinations_act = c_nof_bdo_destinations
+ report "Wrong MM read rd_nof_destinations_act for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_nof_destinations_max = c_nof_bdo_destinations_max
+ report "Wrong MM read rd_nof_destinations_max for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_nof_blocks_per_packet = c_sdp_cep_nof_blocks_per_packet
+ report "Wrong MM read rd_nof_blocks_per_packet for beamset " & natural'image(bset)
+ severity ERROR;
end if;
----------------------------------------------------------------------------
-- Enable BST offload (not verified here, but only for view in Wave window)
@@ -955,7 +995,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -1021,7 +1063,9 @@ begin
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- assert sp_subband_select_arr(g_beamlet * c_sdp_N_pol + v_P) = g_subband report "Wrong subband select at beamlet index." severity ERROR;
+ assert sp_subband_select_arr(g_beamlet * c_sdp_N_pol + v_P) = g_subband
+ report "Wrong subband select at beamlet index."
+ severity ERROR;
proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
----------------------------------------------------------------------------
@@ -1289,8 +1333,12 @@ begin
-- Verify SST
---------------------------------------------------------------------------
-- verify expected subband power based on WG power
- assert sp_sst > c_stat_lo_factor * c_exp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
- assert sp_sst < c_stat_hi_factor * c_exp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
+ assert sp_sst > c_stat_lo_factor * c_exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
+ assert sp_sst < c_stat_hi_factor * c_exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
---------------------------------------------------------------------------
-- Verify BST
@@ -1298,11 +1346,19 @@ begin
-- verify expected beamlet power based on WG power and BF weigths
for U in 0 to c_sdp_N_beamsets - 1 loop
-- X-pol
- assert bst_x_arr(U) < c_stat_hi_factor * c_exp_beamlet_x_bst report "Wrong beamlet X power in beamset " & natural'image(U) severity ERROR;
- assert bst_x_arr(U) > c_stat_lo_factor * c_exp_beamlet_x_bst report "Wrong beamlet X power in beamset " & natural'image(U) severity ERROR;
+ assert bst_x_arr(U) < c_stat_hi_factor * c_exp_beamlet_x_bst
+ report "Wrong beamlet X power in beamset " & natural'image(U)
+ severity ERROR;
+ assert bst_x_arr(U) > c_stat_lo_factor * c_exp_beamlet_x_bst
+ report "Wrong beamlet X power in beamset " & natural'image(U)
+ severity ERROR;
-- Y-pol
- assert bst_y_arr(U) > c_stat_lo_factor * c_exp_beamlet_y_bst report "Wrong beamlet Y power in beamset " & natural'image(U) severity ERROR;
- assert bst_y_arr(U) < c_stat_hi_factor * c_exp_beamlet_y_bst report "Wrong beamlet Y power in beamset " & natural'image(U) severity ERROR;
+ assert bst_y_arr(U) > c_stat_lo_factor * c_exp_beamlet_y_bst
+ report "Wrong beamlet Y power in beamset " & natural'image(U)
+ severity ERROR;
+ assert bst_y_arr(U) < c_stat_hi_factor * c_exp_beamlet_y_bst
+ report "Wrong beamlet Y power in beamset " & natural'image(U)
+ severity ERROR;
end loop;
---------------------------------------------------------------------------
@@ -1311,17 +1367,33 @@ begin
-- X-pol
v_re := rx_beamlet_x_output_re; v_re_exp := c_exp_beamlet_x_output_re;
v_im := rx_beamlet_x_output_im; v_im_exp := c_exp_beamlet_x_output_im;
- assert v_re > integer(v_re_exp) - c_beamlet_output_delta report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_re < integer(v_re_exp) + c_beamlet_output_delta report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_im > integer(v_im_exp) - c_beamlet_output_delta report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
- assert v_im < integer(v_im_exp) + c_beamlet_output_delta report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
+ assert v_re > integer(v_re_exp) - c_beamlet_output_delta
+ report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_re < integer(v_re_exp) + c_beamlet_output_delta
+ report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_im > integer(v_im_exp) - c_beamlet_output_delta
+ report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
+ assert v_im < integer(v_im_exp) + c_beamlet_output_delta
+ report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
-- Y-pol
v_re := rx_beamlet_y_output_re; v_re_exp := c_exp_beamlet_y_output_re;
v_im := rx_beamlet_y_output_im; v_im_exp := c_exp_beamlet_y_output_im;
- assert v_re > integer(v_re_exp) - c_beamlet_output_delta report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_re < integer(v_re_exp) + c_beamlet_output_delta report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_im > integer(v_im_exp) - c_beamlet_output_delta report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
- assert v_im < integer(v_im_exp) + c_beamlet_output_delta report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
+ assert v_re > integer(v_re_exp) - c_beamlet_output_delta
+ report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_re < integer(v_re_exp) + c_beamlet_output_delta
+ report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_im > integer(v_im_exp) - c_beamlet_output_delta
+ report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
+ assert v_im < integer(v_im_exp) + c_beamlet_output_delta
+ report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
@@ -1489,8 +1561,12 @@ begin
-- then rx_beamlet_list then does not change in time and the other
-- blocks should be the same as the first block.
if verify_rx_beamlet_list = '1' then
- assert rx_beamlet_list_re = prev_rx_beamlet_list_re report "Wrong: rx_beamlet_list_re differs from previous block" severity ERROR;
- assert rx_beamlet_list_im = prev_rx_beamlet_list_im report "Wrong: rx_beamlet_list_im differs from previous block" severity ERROR;
+ assert rx_beamlet_list_re = prev_rx_beamlet_list_re
+ report "Wrong: rx_beamlet_list_re differs from previous block"
+ severity ERROR;
+ assert rx_beamlet_list_im = prev_rx_beamlet_list_im
+ report "Wrong: rx_beamlet_list_im differs from previous block"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
index 3abd033083..2897f90155 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -719,8 +719,12 @@ begin
begin
-- Check g_global_sp
if g_global_sp < c_first_sp or g_global_sp > c_last_sp then
- assert false report "g_global_sp not in ring GN range." severity ERROR;
- assert false report "g_global_sp not in ring GN range." severity FAILURE;
+ assert false
+ report "g_global_sp not in ring GN range."
+ severity ERROR;
+ assert false
+ report "g_global_sp not in ring GN range."
+ severity FAILURE;
end if;
-- Wait for DUT power up after reset
@@ -757,9 +761,15 @@ begin
proc_common_wait_some_cycles(tb_clk, 1);
-- . Verify read
- assert c_exp_sdp_info.f_adc = rd_sdp_info.f_adc report "Wrong MM read SDP info f_adc" severity ERROR;
- assert c_exp_sdp_info.fsub_type = rd_sdp_info.fsub_type report "Wrong MM read SDP info fsub_type" severity ERROR;
- assert c_exp_sdp_info.block_period = rd_sdp_info.block_period report "Wrong MM read SDP info block_period" severity ERROR;
+ assert c_exp_sdp_info.f_adc = rd_sdp_info.f_adc
+ report "Wrong MM read SDP info f_adc"
+ severity ERROR;
+ assert c_exp_sdp_info.fsub_type = rd_sdp_info.fsub_type
+ report "Wrong MM read SDP info fsub_type"
+ severity ERROR;
+ assert c_exp_sdp_info.block_period = rd_sdp_info.block_period
+ report "Wrong MM read SDP info block_period"
+ severity ERROR;
------------------------------------------------------------------------------
---- Set and check BF per beamset
@@ -777,7 +787,9 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_bf_scale, v_offset + 0, rd_data, tb_clk);
rd_beamlet_scale <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
- assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale report "Wrong MM read beamlet_scale for beamset " & natural'image(bset) severity ERROR;
+ assert TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale
+ report "Wrong MM read beamlet_scale for beamset " & natural'image(bset)
+ severity ERROR;
----------------------------------------------------------------------------
-- Set CEP beamlets output MAC,IP,UDP port on last node
@@ -844,12 +856,24 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
-- . verify read
- assert unsigned(rd_cep_eth_src_mac) = 0 report "Wrong MM read rd_cep_eth_src_mac != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_ip_src_addr) = 0 report "Wrong MM read rd_cep_ip_src_addr != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_udp_src_port) = 0 report "Wrong MM read rd_cep_udp_src_port != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_eth_dst_mac) = 0 report "Wrong MM read rd_cep_eth_dst_mac != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_ip_dst_addr) = 0 report "Wrong MM read rd_cep_ip_dst_addr != 0 for beamset " & natural'image(bset) severity ERROR;
- assert unsigned(rd_cep_udp_dst_port) = 0 report "Wrong MM read rd_cep_udp_dst_port != 0 for beamset " & natural'image(bset) severity ERROR;
+ assert unsigned(rd_cep_eth_src_mac) = 0
+ report "Wrong MM read rd_cep_eth_src_mac != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_ip_src_addr) = 0
+ report "Wrong MM read rd_cep_ip_src_addr != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_udp_src_port) = 0
+ report "Wrong MM read rd_cep_udp_src_port != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_eth_dst_mac) = 0
+ report "Wrong MM read rd_cep_eth_dst_mac != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_ip_dst_addr) = 0
+ report "Wrong MM read rd_cep_ip_dst_addr != 0 for beamset " & natural'image(bset)
+ severity ERROR;
+ assert unsigned(rd_cep_udp_dst_port) = 0
+ report "Wrong MM read rd_cep_udp_dst_port != 0 for beamset " & natural'image(bset)
+ severity ERROR;
-- Write tb defaults
-- . Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on c_last_gn
@@ -874,12 +898,24 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
proc_common_wait_some_cycles(tb_clk, 1);
-- . verify read back
- assert rd_cep_eth_src_mac = c_cep_eth_src_mac report "Wrong MM read rd_cep_eth_src_mac for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_ip_src_addr = c_cep_ip_src_addr report "Wrong MM read rd_cep_ip_src_addr for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_udp_src_port = c_cep_udp_src_port report "Wrong MM read rd_cep_udp_src_port for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac report "Wrong MM read rd_cep_eth_dst_mac for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr report "Wrong MM read rd_cep_ip_dst_addr for beamset " & natural'image(bset) severity ERROR;
- assert rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port report "Wrong MM read rd_cep_udp_dst_port for beamset " & natural'image(bset) severity ERROR;
+ assert rd_cep_eth_src_mac = c_cep_eth_src_mac
+ report "Wrong MM read rd_cep_eth_src_mac for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_ip_src_addr = c_cep_ip_src_addr
+ report "Wrong MM read rd_cep_ip_src_addr for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_udp_src_port = c_cep_udp_src_port
+ report "Wrong MM read rd_cep_udp_src_port for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac
+ report "Wrong MM read rd_cep_eth_dst_mac for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr
+ report "Wrong MM read rd_cep_ip_dst_addr for beamset " & natural'image(bset)
+ severity ERROR;
+ assert rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port
+ report "Wrong MM read rd_cep_udp_dst_port for beamset " & natural'image(bset)
+ severity ERROR;
----------------------------------------------------------------------------
-- Enable BST offload on last node (not verified here, but only for view in Wave window)
@@ -990,7 +1026,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
for RN in 0 to c_last_rn loop
v_gn := g_first_gn + RN;
@@ -1062,7 +1100,9 @@ begin
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- assert sp_subband_select_arr(g_beamlet * c_sdp_N_pol + v_P) = g_subband report "Wrong subband select at beamlet index." severity ERROR;
+ assert sp_subband_select_arr(g_beamlet * c_sdp_N_pol + v_P) = g_subband
+ report "Wrong subband select at beamlet index."
+ severity ERROR;
proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
----------------------------------------------------------------------------
@@ -1323,8 +1363,12 @@ begin
-- Verify SST
---------------------------------------------------------------------------
-- verify expected subband power based on WG power
- assert sp_sst > c_stat_lo_factor * c_exp_subband_sst report "Wrong subband power for SP " & natural'image(g_global_sp) severity ERROR;
- assert sp_sst < c_stat_hi_factor * c_exp_subband_sst report "Wrong subband power for SP " & natural'image(g_global_sp) severity ERROR;
+ assert sp_sst > c_stat_lo_factor * c_exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_global_sp)
+ severity ERROR;
+ assert sp_sst < c_stat_hi_factor * c_exp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_global_sp)
+ severity ERROR;
---------------------------------------------------------------------------
-- Verify BST
@@ -1332,11 +1376,19 @@ begin
-- verify expected beamlet power based on WG power and BF weigths
for U in 0 to c_sdp_N_beamsets - 1 loop
-- X-pol
- assert bst_x_arr(U) < c_stat_hi_factor * c_exp_beamlet_x_bst report "Wrong beamlet X power in beamset " & natural'image(U) severity ERROR;
- assert bst_x_arr(U) > c_stat_lo_factor * c_exp_beamlet_x_bst report "Wrong beamlet X power in beamset " & natural'image(U) severity ERROR;
+ assert bst_x_arr(U) < c_stat_hi_factor * c_exp_beamlet_x_bst
+ report "Wrong beamlet X power in beamset " & natural'image(U)
+ severity ERROR;
+ assert bst_x_arr(U) > c_stat_lo_factor * c_exp_beamlet_x_bst
+ report "Wrong beamlet X power in beamset " & natural'image(U)
+ severity ERROR;
-- Y-pol
- assert bst_y_arr(U) > c_stat_lo_factor * c_exp_beamlet_y_bst report "Wrong beamlet Y power in beamset " & natural'image(U) severity ERROR;
- assert bst_y_arr(U) < c_stat_hi_factor * c_exp_beamlet_y_bst report "Wrong beamlet Y power in beamset " & natural'image(U) severity ERROR;
+ assert bst_y_arr(U) > c_stat_lo_factor * c_exp_beamlet_y_bst
+ report "Wrong beamlet Y power in beamset " & natural'image(U)
+ severity ERROR;
+ assert bst_y_arr(U) < c_stat_hi_factor * c_exp_beamlet_y_bst
+ report "Wrong beamlet Y power in beamset " & natural'image(U)
+ severity ERROR;
end loop;
---------------------------------------------------------------------------
@@ -1345,17 +1397,33 @@ begin
-- X-pol
v_re := rx_beamlet_x_output_re; v_re_exp := c_exp_beamlet_x_output_re;
v_im := rx_beamlet_x_output_im; v_im_exp := c_exp_beamlet_x_output_im;
- assert v_re > integer(v_re_exp) - c_beamlet_output_delta report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_re < integer(v_re_exp) + c_beamlet_output_delta report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_im > integer(v_im_exp) - c_beamlet_output_delta report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
- assert v_im < integer(v_im_exp) + c_beamlet_output_delta report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
+ assert v_re > integer(v_re_exp) - c_beamlet_output_delta
+ report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_re < integer(v_re_exp) + c_beamlet_output_delta
+ report "Wrong beamlet X output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_im > integer(v_im_exp) - c_beamlet_output_delta
+ report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
+ assert v_im < integer(v_im_exp) + c_beamlet_output_delta
+ report "Wrong beamlet X output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
-- Y-pol
v_re := rx_beamlet_y_output_re; v_re_exp := c_exp_beamlet_y_output_re;
v_im := rx_beamlet_y_output_im; v_im_exp := c_exp_beamlet_y_output_im;
- assert v_re > integer(v_re_exp) - c_beamlet_output_delta report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_re < integer(v_re_exp) + c_beamlet_output_delta report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp) severity ERROR;
- assert v_im > integer(v_im_exp) - c_beamlet_output_delta report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
- assert v_im < integer(v_im_exp) + c_beamlet_output_delta report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp) severity ERROR;
+ assert v_re > integer(v_re_exp) - c_beamlet_output_delta
+ report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_re < integer(v_re_exp) + c_beamlet_output_delta
+ report "Wrong beamlet Y output (re) " & integer'image(v_re) & " != " & real'image(v_re_exp)
+ severity ERROR;
+ assert v_im > integer(v_im_exp) - c_beamlet_output_delta
+ report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
+ assert v_im < integer(v_im_exp) + c_beamlet_output_delta
+ report "Wrong beamlet Y output (im) " & integer'image(v_im) & " != " & real'image(v_im_exp)
+ severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
@@ -1552,8 +1620,12 @@ begin
-- then rx_beamlet_list then does not change in time and the other
-- blocks should be the same as the first block.
if verify_rx_beamlet_list = '1' then
- assert rx_beamlet_list_re = prev_rx_beamlet_list_re report "Wrong: rx_beamlet_list_re differs from previous block" severity ERROR;
- assert rx_beamlet_list_im = prev_rx_beamlet_list_im report "Wrong: rx_beamlet_list_im differs from previous block" severity ERROR;
+ assert rx_beamlet_list_re = prev_rx_beamlet_list_re
+ report "Wrong: rx_beamlet_list_re differs from previous block"
+ severity ERROR;
+ assert rx_beamlet_list_im = prev_rx_beamlet_list_im
+ report "Wrong: rx_beamlet_list_im differs from previous block"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
index cf06a7e713..a50396a3e3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -394,7 +394,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -415,8 +417,12 @@ begin
sp_co_subband_weight_phase <= COMPLEX_PHASE(real(v_re), real(v_im));
sp_co_subband_weight_val <= '1';
proc_common_wait_some_cycles(tb_clk, 1);
- assert sp_co_subband_weight_re = c_sdp_unit_sub_weight report "Default sp_co_subband_weight_re /= c_sdp_unit_sub_weight" severity ERROR;
- assert sp_co_subband_weight_im = 0 report "Default sp_co_subband_weight_im /= 0" severity ERROR;
+ assert sp_co_subband_weight_re = c_sdp_unit_sub_weight
+ report "Default sp_co_subband_weight_re /= c_sdp_unit_sub_weight"
+ severity ERROR;
+ assert sp_co_subband_weight_im = 0
+ report "Default sp_co_subband_weight_im /= 0"
+ severity ERROR;
-- . write
v_weight := pack_complex(re => c_co_subband_weight_re, im => c_co_subband_weight_im, w => c_sdp_W_sub_weight); -- c_sdp_W_sub_weight = 16 bit
mmf_mm_bus_wr(c_mm_file_ram_equalizer_gains, v_addr, v_weight, tb_clk);
@@ -430,8 +436,12 @@ begin
sp_co_subband_weight_gain <= COMPLEX_RADIUS(real(v_re), real(v_im)) / real(c_sdp_unit_sub_weight);
sp_co_subband_weight_phase <= COMPLEX_PHASE(real(v_re), real(v_im));
proc_common_wait_some_cycles(tb_clk, 1);
- assert sp_co_subband_weight_re = c_co_subband_weight_re report "Readback sp_co_subband_weight_re /= c_co_subband_weight_re" severity ERROR;
- assert sp_co_subband_weight_im = c_co_subband_weight_im report "Readback sp_co_subband_weight_im /= c_co_subband_weight_im" severity ERROR;
+ assert sp_co_subband_weight_re = c_co_subband_weight_re
+ report "Readback sp_co_subband_weight_re /= c_co_subband_weight_re"
+ severity ERROR;
+ assert sp_co_subband_weight_im = c_co_subband_weight_im
+ report "Readback sp_co_subband_weight_im /= c_co_subband_weight_im"
+ severity ERROR;
if g_use_cross_weight then
-- Cross-polarization subband weight for g_sp
@@ -447,8 +457,12 @@ begin
sp_cross_subband_weight_phase <= COMPLEX_PHASE(real(v_re), real(v_im));
sp_cross_subband_weight_val <= '1';
proc_common_wait_some_cycles(tb_clk, 1);
- assert sp_cross_subband_weight_re = 0 report "Default sp_cross_subband_weight_re /= 0" severity ERROR;
- assert sp_cross_subband_weight_im = 0 report "Default sp_cross_subband_weight_im /= 0" severity ERROR;
+ assert sp_cross_subband_weight_re = 0
+ report "Default sp_cross_subband_weight_re /= 0"
+ severity ERROR;
+ assert sp_cross_subband_weight_im = 0
+ report "Default sp_cross_subband_weight_im /= 0"
+ severity ERROR;
-- . write
v_weight := pack_complex(re => c_sp_cross_subband_weight_re, im => c_sp_cross_subband_weight_im, w => c_sdp_W_sub_weight); -- c_sdp_W_sub_weight = 16 bit
mmf_mm_bus_wr(c_mm_file_ram_equalizer_gains_cross, v_addr, v_weight, tb_clk);
@@ -462,8 +476,12 @@ begin
sp_cross_subband_weight_gain <= COMPLEX_RADIUS(real(v_re), real(v_im)) / real(c_sdp_unit_sub_weight);
sp_cross_subband_weight_phase <= COMPLEX_PHASE(real(v_re), real(v_im));
proc_common_wait_some_cycles(tb_clk, 1);
- assert sp_cross_subband_weight_re = c_sp_cross_subband_weight_re report "Readback sp_cross_subband_weight_re /= c_sp_cross_subband_weight_re" severity ERROR;
- assert sp_cross_subband_weight_im = c_sp_cross_subband_weight_im report "Readback sp_cross_subband_weight_im /= c_sp_cross_subband_weight_im" severity ERROR;
+ assert sp_cross_subband_weight_re = c_sp_cross_subband_weight_re
+ report "Readback sp_cross_subband_weight_re /= c_sp_cross_subband_weight_re"
+ severity ERROR;
+ assert sp_cross_subband_weight_im = c_sp_cross_subband_weight_im
+ report "Readback sp_cross_subband_weight_im /= c_sp_cross_subband_weight_im"
+ severity ERROR;
end if;
----------------------------------------------------------------------------
@@ -532,7 +550,8 @@ begin
if sp_subband_sst > c_eps and v_power > c_eps then
sp_subband_sst_leakage_snr_dB <= 10.0 * LOG10(sp_subband_sst / v_power);
elsif g_read_all_SST then
- report "Wrong, zero leakage is unexpected for SP-" & natural'image(g_sp) severity ERROR;
+ report "Wrong, zero leakage is unexpected for SP-" & natural'image(g_sp)
+ severity ERROR;
end if;
if not g_use_cross_weight then
@@ -545,7 +564,8 @@ begin
if sp_subband_sst > c_eps and v_power > c_eps then
sp_subband_sst_crosstalk_snr_dB <= 10.0 * LOG10(sp_subband_sst / v_power);
elsif g_read_all_SST then
- report "Zero crosstalk for SP-" & natural'image(g_sp) severity NOTE;
+ report "Zero crosstalk for SP-" & natural'image(g_sp)
+ severity NOTE;
end if;
end if;
@@ -601,21 +621,33 @@ begin
-- Verify SST
---------------------------------------------------------------------------
-- Verify expected subband power based on WG power for g_sp
- assert sp_subband_sst > c_lo_factor * exp_sp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
- assert sp_subband_sst < c_hi_factor * exp_sp_subband_sst report "Wrong subband power for SP " & natural'image(g_sp) severity ERROR;
+ assert sp_subband_sst > c_lo_factor * exp_sp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
+ assert sp_subband_sst < c_hi_factor * exp_sp_subband_sst
+ report "Wrong subband power for SP " & natural'image(g_sp)
+ severity ERROR;
if g_use_cross_weight then
-- Verify expected subband power based on WG power for c_cross_sp
-- The other WPFB input WG at c_cross_sp is used as cross polarization input, with default
-- unit co-polarization subband weight and zero cross-polarization subband weight.
- assert sp_cross_subband_sst > c_lo_factor * exp_cross_subband_sst report "Wrong subband power for cross SP " & natural'image(c_cross_sp) severity ERROR;
- assert sp_cross_subband_sst < c_hi_factor * exp_cross_subband_sst report "Wrong subband power for cross SP " & natural'image(c_cross_sp) severity ERROR;
+ assert sp_cross_subband_sst > c_lo_factor * exp_cross_subband_sst
+ report "Wrong subband power for cross SP " & natural'image(c_cross_sp)
+ severity ERROR;
+ assert sp_cross_subband_sst < c_hi_factor * exp_cross_subband_sst
+ report "Wrong subband power for cross SP " & natural'image(c_cross_sp)
+ severity ERROR;
end if;
if g_read_all_SST then
-- Verify expected SNR quality measures
- assert sp_subband_sst_leakage = 0.0 or sp_subband_sst_leakage_snr_dB > c_exp_sp_subband_sst_leakage_snr_dB report "Wrong too much leakage for SP " & natural'image(g_sp) severity ERROR;
+ assert sp_subband_sst_leakage = 0.0 or sp_subband_sst_leakage_snr_dB > c_exp_sp_subband_sst_leakage_snr_dB
+ report "Wrong too much leakage for SP " & natural'image(g_sp)
+ severity ERROR;
if not g_use_cross_weight then
- assert sp_subband_sst_crosstalk = 0.0 or sp_subband_sst_crosstalk_snr_dB > c_exp_sp_subband_sst_crosstalk_snr_dB report "Wrong too much crosstalk for SP " & natural'image(g_sp) severity ERROR;
+ assert sp_subband_sst_crosstalk = 0.0 or sp_subband_sst_crosstalk_snr_dB > c_exp_sp_subband_sst_crosstalk_snr_dB
+ report "Wrong too much crosstalk for SP " & natural'image(g_sp)
+ severity ERROR;
end if;
end if;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
index ca762db8b0..fe6c16b591 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -258,7 +258,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -309,28 +311,46 @@ begin
-- Check real values of even indices
if v_C = 0 and v_A_even = 0 and v_B_even = 0 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0))
+ report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check real values of odd indices
if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex))
+ report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check real values of even correlated with odd indices
if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex))
+ report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
-- Check im values of even indices
if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1)))
+ report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check im values of odd indices
if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1)))
+ report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check im values of even correlated with odd indices
if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1)))
+ report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I)
+ severity ERROR;
+ end if;
-- Check if values are > 0
if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
@@ -339,10 +359,14 @@ begin
-- therefore also verify the expected XST value for all XST.
if I mod c_nof_complex = 0 then
-- real part
- assert almost_equal(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, 1.0, c_max_ratio) report "Wrong XST real value at I = " & int_to_str(I) severity ERROR;
+ assert almost_equal(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, 1.0, c_max_ratio)
+ report "Wrong XST real value at I = " & int_to_str(I)
+ severity ERROR;
else
-- imag part
- assert almost_zero(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, c_max_ratio) report "Wrong XST imag value at I = " & int_to_str(I) severity ERROR;
+ assert almost_zero(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, c_max_ratio)
+ report "Wrong XST imag value at I = " & int_to_str(I)
+ severity ERROR;
end if;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
index 657a3cebec..26ed83312f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
@@ -289,7 +289,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -441,10 +443,14 @@ begin
if rx_sdp_stat_re_val = '1' then
if v_subband_ix = c_wg_subband then
-- Expect the strong XST value at the WG subband
- assert almost_equal(TO_SREAL(rx_sdp_stat_re) / c_exp_subband_xst, 1.0, c_max_ratio) report "Wrong XST real value at subband = " & int_to_str(v_subband_ix) severity ERROR;
+ assert almost_equal(TO_SREAL(rx_sdp_stat_re) / c_exp_subband_xst, 1.0, c_max_ratio)
+ report "Wrong XST real value at subband = " & int_to_str(v_subband_ix)
+ severity ERROR;
else
-- WG is only in one subband, so expect almost zero in the other subbands
- assert almost_zero(TO_SREAL(rx_sdp_stat_re) / c_exp_subband_xst, c_max_ratio) report "Too large XST real value at subband = " & int_to_str(v_subband_ix) severity ERROR;
+ assert almost_zero(TO_SREAL(rx_sdp_stat_re) / c_exp_subband_xst, c_max_ratio)
+ report "Too large XST real value at subband = " & int_to_str(v_subband_ix)
+ severity ERROR;
end if;
end if;
if rx_sdp_stat_im_val = '1' then
@@ -453,9 +459,13 @@ begin
-- . The imag part is almost zero for signal inputs a and b that are both connected to the opposite inputs of the WPFB, due
-- to crosstalk rounding difference from input a to b or from input b to a of the complex FFT.
if (rx_a_sp mod c_sdp_Q_fft) = (rx_b_sp mod c_sdp_Q_fft) then
- assert signed(rx_sdp_stat_im) = 0 report "Non zero XST imaginary value at subband = " & int_to_str(v_subband_ix) severity ERROR;
+ assert signed(rx_sdp_stat_im) = 0
+ report "Non zero XST imaginary value at subband = " & int_to_str(v_subband_ix)
+ severity ERROR;
else
- assert almost_zero(TO_SREAL(rx_sdp_stat_im) / c_exp_subband_xst, c_max_ratio) report "Too large XST imaginary value at subband = " & int_to_str(v_subband_ix) severity ERROR;
+ assert almost_zero(TO_SREAL(rx_sdp_stat_im) / c_exp_subband_xst, c_max_ratio)
+ report "Too large XST imaginary value at subband = " & int_to_str(v_subband_ix)
+ severity ERROR;
end if;
end if;
end if;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
index 8bdf7bca75..985c676665 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
@@ -211,7 +211,9 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
+ assert v_bsn <= c_bsn_start_wg
+ report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg)
+ severity ERROR;
v_bsn := c_bsn_start_wg;
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 6df8f1ff9c..513eb078be 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -228,7 +228,9 @@ begin
-- stopping the testbench
wait for c_clk_period * g_block_size;
tb_end <= '1';
- assert false report "Test: OK" severity FAILURE;
+ assert false
+ report "Test: OK"
+ severity FAILURE;
end process;
p_checking_output_data : process -- first do tickets L2SDP-708 and L2SDP-707 before finsishing this is worth time
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 8f6701daf2..c789c12710 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -734,7 +734,9 @@ package body sdp_pkg is
function func_sdp_modulo_N_sub(sub_index : natural) return natural is
begin
- assert sub_index < 2 * c_sdp_N_sub report "func_sdp_modulo_N_sub: sub_index too large" severity FAILURE;
+ assert sub_index < 2 * c_sdp_N_sub
+ report "func_sdp_modulo_N_sub: sub_index too large"
+ severity FAILURE;
if sub_index < c_sdp_N_sub - 1 then
return sub_index;
else
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd
index c63631e39f..1e0530ee6a 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd
@@ -232,7 +232,9 @@ begin
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_nof_destinations <= to_uint(reg_destinations_cipo.rddata(c_word_w - 1 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
- assert rd_nof_destinations = g_nof_destinations report "Wrong MM readback nof_destinations" severity error;
+ assert rd_nof_destinations = g_nof_destinations
+ report "Wrong MM readback nof_destinations"
+ severity error;
-- . Read nof_destinations_act, to check that g_nof_destinations is
-- forced to c_nof_destinations
@@ -241,7 +243,9 @@ begin
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_nof_destinations_act <= to_uint(reg_destinations_cipo.rddata(c_word_w - 1 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
- assert rd_nof_destinations_act = c_nof_destinations report "Wrong MM read nof_destinations_act" severity error;
+ assert rd_nof_destinations_act = c_nof_destinations
+ report "Wrong MM read nof_destinations_act"
+ severity error;
-- . Use same destination MAC/IP/UDP for all destinations, to ease rx_beamlet_header verification
-- and to have same c_exp_ip_header_checksum value for all c_nof_destinations.
@@ -488,8 +492,12 @@ begin
-- Verify incrementing beamlets
v_re := (v_re + 1) mod c_beamlet_mod;
v_im := (v_im + 1) mod c_beamlet_mod;
- assert to_uint(rx_beamlet_list_re(vI)) = v_re report "Wrong re_beamlet." severity error;
- assert to_uint(rx_beamlet_list_im(vI)) = v_im report "Wrong im_beamlet." severity error;
+ assert to_uint(rx_beamlet_list_re(vI)) = v_re
+ report "Wrong re_beamlet."
+ severity error;
+ assert to_uint(rx_beamlet_list_im(vI)) = v_im
+ report "Wrong im_beamlet."
+ severity error;
end loop;
-- . hold last values for next block
prev_re <= v_re;
@@ -616,8 +624,12 @@ begin
-- Verify incrementing beamlets
v_re := (v_re + 1) mod c_beamlet_mod;
v_im := (v_im + 1) mod c_beamlet_mod;
- assert to_uint(rx_mdi_beamlet_list_re(vI)) = v_re report "Wrong mdi re_beamlet." severity error;
- assert to_uint(rx_mdi_beamlet_list_im(vI)) = v_im report "Wrong mdi im_beamlet." severity error;
+ assert to_uint(rx_mdi_beamlet_list_re(vI)) = v_re
+ report "Wrong mdi re_beamlet."
+ severity error;
+ assert to_uint(rx_mdi_beamlet_list_im(vI)) = v_im
+ report "Wrong mdi im_beamlet."
+ severity error;
end loop;
-- . hold last values for next block
mdi_prev_re <= v_re;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
index 4cacb6ce6f..bf21c8a9d0 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
@@ -612,8 +612,12 @@ begin
begin
for RN in 0 to c_last_rn loop
if bf_sum_sosi_arr(RN).valid = '1' then
- assert TO_SINT(bf_sum_sosi_arr(RN).re) = (RN + 1) * c_local_bf_re report "Wrong BF re sum at node " & int_to_str(RN) severity error;
- assert TO_SINT(bf_sum_sosi_arr(RN).im) = (RN + 1) * c_local_bf_im report "Wrong BF im sum at node " & int_to_str(RN) severity error;
+ assert TO_SINT(bf_sum_sosi_arr(RN).re) = (RN + 1) * c_local_bf_re
+ report "Wrong BF re sum at node " & int_to_str(RN)
+ severity error;
+ assert TO_SINT(bf_sum_sosi_arr(RN).im) = (RN + 1) * c_local_bf_im
+ report "Wrong BF im sum at node " & int_to_str(RN)
+ severity error;
end if;
end loop;
end process;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
index a94a8c33fa..7e83acc6cb 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
@@ -832,17 +832,25 @@ begin
for RN in 0 to c_last_rn loop
for P in 0 to c_P_sq - 1 loop
if x_sosi_2arr(RN)(P).valid = '1' then
- assert TO_SINT(x_sosi_2arr(RN)(P).re) /= 0 report "Wrong crosslet re at node " & int_to_str(RN) severity error;
- assert TO_SINT(x_sosi_2arr(RN)(P).im) /= 0 report "Wrong crosslet im at node " & int_to_str(RN) severity error;
+ assert TO_SINT(x_sosi_2arr(RN)(P).re) /= 0
+ report "Wrong crosslet re at node " & int_to_str(RN)
+ severity error;
+ assert TO_SINT(x_sosi_2arr(RN)(P).im) /= 0
+ report "Wrong crosslet im at node " & int_to_str(RN)
+ severity error;
end if;
end loop;
end loop;
-- Verify that all aligned outputs on all RN are valid at the same time
if x_sosi.valid = '1' then
- assert vector_and(x_sosi_2arr_valids) = '1' report "Missing aligned output valid" severity error;
+ assert vector_and(x_sosi_2arr_valids) = '1'
+ report "Missing aligned output valid"
+ severity error;
else
- assert vector_or(x_sosi_2arr_valids) = '0' report "Unexpected aligned output valid" severity error;
+ assert vector_or(x_sosi_2arr_valids) = '0'
+ report "Unexpected aligned output valid"
+ severity error;
end if;
end process;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 39f4fb1d94..2aa8e4d760 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -131,9 +131,13 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
-- Verify that readback crosslet info is active crosslets_info
for I in 0 to c_N_crosslets - 1 loop
- assert rd_crosslet_offsets(I) = 0 report "Wrong crosslet offset after rst." severity ERROR;
+ assert rd_crosslet_offsets(I) = 0
+ report "Wrong crosslet offset after rst."
+ severity ERROR;
end loop;
- assert rd_crosslet_step = 0 report "Wrong crosslet step after rst." severity ERROR;
+ assert rd_crosslet_step = 0
+ report "Wrong crosslet step after rst."
+ severity ERROR;
-- b) Read crosslets_info in every sync interval
while true loop
@@ -151,9 +155,13 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
-- Verify that readback crosslet info is active crosslets_info
for I in 0 to c_N_crosslets - 1 loop
- assert rd_crosslet_offsets(I) = exp_cur_crosslets_info_rec.offset_arr(I) report "Wrong active crosslet offset in output sync interval." severity ERROR;
+ assert rd_crosslet_offsets(I) = exp_cur_crosslets_info_rec.offset_arr(I)
+ report "Wrong active crosslet offset in output sync interval."
+ severity ERROR;
end loop;
- assert rd_crosslet_step = exp_cur_crosslets_info_rec.step report "Wrong active crosslet step in output sync interval." severity ERROR;
+ assert rd_crosslet_step = exp_cur_crosslets_info_rec.step
+ report "Wrong active crosslet step in output sync interval."
+ severity ERROR;
end loop;
wait;
@@ -262,17 +270,33 @@ begin
p_verify_out_data : process(clk)
begin
if rising_edge(clk) then
- assert out_sosi.valid = exp_sosi.valid report "Wrong out_sosi.valid" severity ERROR;
- assert out_sosi.sop = exp_sosi.sop report "Wrong out_sosi.sop" severity ERROR;
- assert out_sosi.eop = exp_sosi.eop report "Wrong out_sosi.eop" severity ERROR;
- assert out_sosi.sync = exp_sosi.sync report "Wrong out_sosi.sync" severity ERROR;
-
- assert cur_crosslets_info_rec = exp_cur_crosslets_info_rec report "Wrong cur_crosslets_info" severity ERROR;
- assert prev_crosslets_info_rec = exp_prev_crosslets_info_rec report "Wrong prev_crosslets_info" severity ERROR;
+ assert out_sosi.valid = exp_sosi.valid
+ report "Wrong out_sosi.valid"
+ severity ERROR;
+ assert out_sosi.sop = exp_sosi.sop
+ report "Wrong out_sosi.sop"
+ severity ERROR;
+ assert out_sosi.eop = exp_sosi.eop
+ report "Wrong out_sosi.eop"
+ severity ERROR;
+ assert out_sosi.sync = exp_sosi.sync
+ report "Wrong out_sosi.sync"
+ severity ERROR;
+
+ assert cur_crosslets_info_rec = exp_cur_crosslets_info_rec
+ report "Wrong cur_crosslets_info"
+ severity ERROR;
+ assert prev_crosslets_info_rec = exp_prev_crosslets_info_rec
+ report "Wrong prev_crosslets_info"
+ severity ERROR;
if exp_sosi.valid = '1' then
- assert out_sosi.re = exp_sosi.re report "Wrong out_sosi.re" severity ERROR;
- assert out_sosi.im = exp_sosi.im report "Wrong out_sosi.im" severity ERROR;
+ assert out_sosi.re = exp_sosi.re
+ report "Wrong out_sosi.re"
+ severity ERROR;
+ assert out_sosi.im = exp_sosi.im
+ report "Wrong out_sosi.im"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index 5203e24044..d906688c65 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -110,54 +110,72 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response /= 11 report "Wrong block_period (not read only)" severity ERROR;
+ assert mm_natural_response /= 11
+ report "Wrong block_period (not read only)"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_beam_repositioning_flag, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 1 report "Wrong beam_repositioning_flag" severity ERROR;
+ assert mm_natural_response = 1
+ report "Wrong beam_repositioning_flag"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_fsub_type, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response /= 1 report "Wrong fsub_type (not read only)" severity ERROR;
+ assert mm_natural_response /= 1
+ report "Wrong fsub_type (not read only)"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_f_adc, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response /= 1 report "Wrong f_adc (not read only)" severity ERROR;
+ assert mm_natural_response /= 1
+ report "Wrong f_adc (not read only)"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_nyquist_zone_index, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 3 report "Wrong nyquist_zone_index" severity ERROR;
+ assert mm_natural_response = 3
+ report "Wrong nyquist_zone_index"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_observation_id, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 16 report "Wrong observation_id" severity ERROR;
+ assert mm_natural_response = 16
+ report "Wrong observation_id"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_antenna_band_index, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 1 report "Wrong antenna_band_index" severity ERROR;
+ assert mm_natural_response = 1
+ report "Wrong antenna_band_index"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_station_id, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 17 report "Wrong station_id" severity ERROR;
+ assert mm_natural_response = 17
+ report "Wrong station_id"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_antenna_field_index, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata);
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 15 report "Wrong antenna_field_index" severity ERROR;
+ assert mm_natural_response = 15
+ report "Wrong antenna_field_index"
+ severity ERROR;
-- check block_period if f_adc and fsub_type are changed
-- f_adc = '0' and fsub_type = '0' => block_period = 6400
@@ -170,28 +188,36 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata(15 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 6400 report "wrong block_period, expected 6400" severity ERROR;
+ assert mm_natural_response = 6400
+ report "wrong block_period, expected 6400"
+ severity ERROR;
f_adc <= '1'; fsub_type <= '0';
proc_common_wait_cross_clock_domain_latency(dp_clk, mm_clk);
proc_mem_mm_bus_rd(c_mm_addr_block_period, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata(15 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 5120 report "wrong block_period, expected 5120" severity ERROR;
+ assert mm_natural_response = 5120
+ report "wrong block_period, expected 5120"
+ severity ERROR;
f_adc <= '0'; fsub_type <= '1';
proc_common_wait_cross_clock_domain_latency(dp_clk, mm_clk);
proc_mem_mm_bus_rd(c_mm_addr_block_period, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata(15 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 5400 report "wrong block_period, expected 5400" severity ERROR;
+ assert mm_natural_response = 5400
+ report "wrong block_period, expected 5400"
+ severity ERROR;
f_adc <= '1'; fsub_type <= '1';
proc_common_wait_cross_clock_domain_latency(dp_clk, mm_clk);
proc_mem_mm_bus_rd(c_mm_addr_block_period, mm_clk, reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata(15 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 4320 report "wrong block_period, expected 4320" severity ERROR;
+ assert mm_natural_response = 4320
+ report "wrong block_period, expected 4320"
+ severity ERROR;
proc_common_wait_some_cycles(mm_clk, 100);
tb_mm_reg_end <= '1';
@@ -203,15 +229,33 @@ begin
begin
proc_common_wait_until_high(mm_clk, tb_mm_reg_end); -- wait for p_mm_reg_stimuli done
- assert TO_UINT(sdp_info.block_period) = 4320 report "wrong sdp_info.block_period value" severity ERROR;
- assert sdp_info.beam_repositioning_flag = '1' report "wrong sdp_info.beam_repositioning_flag value" severity ERROR;
- assert sdp_info.fsub_type = '1' report "wrong sdp_info.fsub_type value" severity ERROR;
- assert sdp_info.f_adc = '1' report "wrong sdp_info.f_adc value" severity ERROR;
- assert TO_UINT(sdp_info.nyquist_zone_index) = 3 report "wrong sdp_info.nyquist_zone_index value" severity ERROR;
- assert TO_UINT(sdp_info.observation_id) = 16 report "wrong sdp_info.observation_id value" severity ERROR;
- assert sdp_info.antenna_band_index = '1' report "wrong sdp_info.antenna_band_index value" severity ERROR;
- assert TO_UINT(sdp_info.station_id) = 17 report "wrong sdp_info.station_id value" severity ERROR;
- assert TO_UINT(sdp_info.antenna_field_index) = 15 report "wrong sdp_info.antenna_field_index value" severity ERROR;
+ assert TO_UINT(sdp_info.block_period) = 4320
+ report "wrong sdp_info.block_period value"
+ severity ERROR;
+ assert sdp_info.beam_repositioning_flag = '1'
+ report "wrong sdp_info.beam_repositioning_flag value"
+ severity ERROR;
+ assert sdp_info.fsub_type = '1'
+ report "wrong sdp_info.fsub_type value"
+ severity ERROR;
+ assert sdp_info.f_adc = '1'
+ report "wrong sdp_info.f_adc value"
+ severity ERROR;
+ assert TO_UINT(sdp_info.nyquist_zone_index) = 3
+ report "wrong sdp_info.nyquist_zone_index value"
+ severity ERROR;
+ assert TO_UINT(sdp_info.observation_id) = 16
+ report "wrong sdp_info.observation_id value"
+ severity ERROR;
+ assert sdp_info.antenna_band_index = '1'
+ report "wrong sdp_info.antenna_band_index value"
+ severity ERROR;
+ assert TO_UINT(sdp_info.station_id) = 17
+ report "wrong sdp_info.station_id value"
+ severity ERROR;
+ assert TO_UINT(sdp_info.antenna_field_index) = 15
+ report "wrong sdp_info.antenna_field_index value"
+ severity ERROR;
proc_common_wait_some_cycles(mm_clk, 100);
tb_end <= '1';
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index c55cec9834..69daed37a1 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -282,68 +282,157 @@ package body tb_sdp_pkg is
function func_sdp_verify_stat_header(g_statistics_type : string; in_hdr, exp_hdr : t_sdp_stat_header) return boolean is
begin
-- eth header
- assert in_hdr.eth.dst_mac = exp_hdr.eth.dst_mac report "Wrong " & g_statistics_type & " eth.dst_mac" severity ERROR;
- assert in_hdr.eth.src_mac = exp_hdr.eth.src_mac report "Wrong " & g_statistics_type & " eth.src_mac" severity ERROR;
- assert in_hdr.eth.eth_type = exp_hdr.eth.eth_type report "Wrong " & g_statistics_type & " eth.eth_type" severity ERROR;
+ assert in_hdr.eth.dst_mac = exp_hdr.eth.dst_mac
+ report "Wrong " & g_statistics_type & " eth.dst_mac"
+ severity ERROR;
+ assert in_hdr.eth.src_mac = exp_hdr.eth.src_mac
+ report "Wrong " & g_statistics_type & " eth.src_mac"
+ severity ERROR;
+ assert in_hdr.eth.eth_type = exp_hdr.eth.eth_type
+ report "Wrong " & g_statistics_type & " eth.eth_type"
+ severity ERROR;
-- ip header
- assert in_hdr.ip.version = exp_hdr.ip.version report "Wrong " & g_statistics_type & " ip.version" severity ERROR;
- assert in_hdr.ip.header_length = exp_hdr.ip.header_length report "Wrong " & g_statistics_type & " ip.header_length" severity ERROR;
- assert in_hdr.ip.services = exp_hdr.ip.services report "Wrong " & g_statistics_type & " ip.services" severity ERROR;
- assert in_hdr.ip.total_length = exp_hdr.ip.total_length report "Wrong " & g_statistics_type & " ip.total_length" severity ERROR;
- assert in_hdr.ip.identification = exp_hdr.ip.identification report "Wrong " & g_statistics_type & " ip.identification" severity ERROR;
- assert in_hdr.ip.flags = exp_hdr.ip.flags report "Wrong " & g_statistics_type & " ip.flags" severity ERROR;
- assert in_hdr.ip.fragment_offset = exp_hdr.ip.fragment_offset report "Wrong " & g_statistics_type & " ip.fragment_offset" severity ERROR;
- assert in_hdr.ip.time_to_live = exp_hdr.ip.time_to_live report "Wrong " & g_statistics_type & " ip.time_to_live" severity ERROR;
- assert in_hdr.ip.protocol = exp_hdr.ip.protocol report "Wrong " & g_statistics_type & " ip.protocol" severity ERROR;
- assert in_hdr.ip.header_checksum = exp_hdr.ip.header_checksum report "Wrong " & g_statistics_type & " ip.header_checksum" severity ERROR;
- assert in_hdr.ip.src_ip_addr = exp_hdr.ip.src_ip_addr report "Wrong " & g_statistics_type & " ip.src_ip_addr" severity ERROR;
- assert in_hdr.ip.dst_ip_addr = exp_hdr.ip.dst_ip_addr report "Wrong " & g_statistics_type & " ip.dst_ip_addr" severity ERROR;
+ assert in_hdr.ip.version = exp_hdr.ip.version
+ report "Wrong " & g_statistics_type & " ip.version"
+ severity ERROR;
+ assert in_hdr.ip.header_length = exp_hdr.ip.header_length
+ report "Wrong " & g_statistics_type & " ip.header_length"
+ severity ERROR;
+ assert in_hdr.ip.services = exp_hdr.ip.services
+ report "Wrong " & g_statistics_type & " ip.services"
+ severity ERROR;
+ assert in_hdr.ip.total_length = exp_hdr.ip.total_length
+ report "Wrong " & g_statistics_type & " ip.total_length"
+ severity ERROR;
+ assert in_hdr.ip.identification = exp_hdr.ip.identification
+ report "Wrong " & g_statistics_type & " ip.identification"
+ severity ERROR;
+ assert in_hdr.ip.flags = exp_hdr.ip.flags
+ report "Wrong " & g_statistics_type & " ip.flags"
+ severity ERROR;
+ assert in_hdr.ip.fragment_offset = exp_hdr.ip.fragment_offset
+ report "Wrong " & g_statistics_type & " ip.fragment_offset"
+ severity ERROR;
+ assert in_hdr.ip.time_to_live = exp_hdr.ip.time_to_live
+ report "Wrong " & g_statistics_type & " ip.time_to_live"
+ severity ERROR;
+ assert in_hdr.ip.protocol = exp_hdr.ip.protocol
+ report "Wrong " & g_statistics_type & " ip.protocol"
+ severity ERROR;
+ assert in_hdr.ip.header_checksum = exp_hdr.ip.header_checksum
+ report "Wrong " & g_statistics_type & " ip.header_checksum"
+ severity ERROR;
+ assert in_hdr.ip.src_ip_addr = exp_hdr.ip.src_ip_addr
+ report "Wrong " & g_statistics_type & " ip.src_ip_addr"
+ severity ERROR;
+ assert in_hdr.ip.dst_ip_addr = exp_hdr.ip.dst_ip_addr
+ report "Wrong " & g_statistics_type & " ip.dst_ip_addr"
+ severity ERROR;
-- udp header
- assert in_hdr.udp.src_port = exp_hdr.udp.src_port report "Wrong " & g_statistics_type & " udp.src_port" severity ERROR;
- assert in_hdr.udp.dst_port = exp_hdr.udp.dst_port report "Wrong " & g_statistics_type & " udp.dst_port" severity ERROR;
- assert in_hdr.udp.total_length = exp_hdr.udp.total_length report "Wrong " & g_statistics_type & " udp.total_length" severity ERROR;
- assert in_hdr.udp.checksum = exp_hdr.udp.checksum report "Wrong " & g_statistics_type & " udp.checksum" severity ERROR;
+ assert in_hdr.udp.src_port = exp_hdr.udp.src_port
+ report "Wrong " & g_statistics_type & " udp.src_port"
+ severity ERROR;
+ assert in_hdr.udp.dst_port = exp_hdr.udp.dst_port
+ report "Wrong " & g_statistics_type & " udp.dst_port"
+ severity ERROR;
+ assert in_hdr.udp.total_length = exp_hdr.udp.total_length
+ report "Wrong " & g_statistics_type & " udp.total_length"
+ severity ERROR;
+ assert in_hdr.udp.checksum = exp_hdr.udp.checksum
+ report "Wrong " & g_statistics_type & " udp.checksum"
+ severity ERROR;
-- app header
- assert in_hdr.app.sdp_marker = exp_hdr.app.sdp_marker report "Wrong " & g_statistics_type & " app.sdp_marker" severity ERROR;
- assert in_hdr.app.sdp_version_id = exp_hdr.app.sdp_version_id report "Wrong " & g_statistics_type & " app.sdp_version_id" severity ERROR;
- assert in_hdr.app.sdp_observation_id = exp_hdr.app.sdp_observation_id report "Wrong " & g_statistics_type & " app.sdp_observation_id" severity ERROR;
- assert in_hdr.app.sdp_station_info = exp_hdr.app.sdp_station_info report "Wrong " & g_statistics_type & " app.sdp_station_info" severity ERROR;
-
- assert in_hdr.app.sdp_source_info_antenna_band_id = exp_hdr.app.sdp_source_info_antenna_band_id report "Wrong " & g_statistics_type & " app.sdp_source_info_antenna_band_id" severity ERROR;
- assert in_hdr.app.sdp_source_info_nyquist_zone_id = exp_hdr.app.sdp_source_info_nyquist_zone_id report "Wrong " & g_statistics_type & " app.sdp_source_info_nyquist_zone_id" severity ERROR;
- assert in_hdr.app.sdp_source_info_f_adc = exp_hdr.app.sdp_source_info_f_adc report "Wrong " & g_statistics_type & " app.sdp_source_info_f_adc" severity ERROR;
- assert in_hdr.app.sdp_source_info_fsub_type = exp_hdr.app.sdp_source_info_fsub_type report "Wrong " & g_statistics_type & " app.sdp_source_info_fsub_type" severity ERROR;
- assert in_hdr.app.sdp_source_info_payload_error = exp_hdr.app.sdp_source_info_payload_error report "Wrong " & g_statistics_type & " app.sdp_source_info_payload_error" severity ERROR;
- assert in_hdr.app.sdp_source_info_beam_repositioning_flag = exp_hdr.app.sdp_source_info_beam_repositioning_flag report "Wrong " & g_statistics_type & " app.sdp_source_info_beam_repositioning_flag" severity ERROR;
- assert in_hdr.app.sdp_source_info_weighted_subbands_flag = exp_hdr.app.sdp_source_info_weighted_subbands_flag report "Wrong " & g_statistics_type & " app.sdp_source_info_weighted_subbands_flag" severity ERROR;
- assert in_hdr.app.sdp_source_info_gn_id = exp_hdr.app.sdp_source_info_gn_id report "Wrong " & g_statistics_type & " app.sdp_source_info_gn_id" severity ERROR;
-
- assert in_hdr.app.sdp_reserved = exp_hdr.app.sdp_reserved report "Wrong " & g_statistics_type & " app.sdp_reserved" severity ERROR;
- assert in_hdr.app.sdp_integration_interval = exp_hdr.app.sdp_integration_interval report "Wrong " & g_statistics_type & " app.sdp_integration_interval" severity ERROR;
+ assert in_hdr.app.sdp_marker = exp_hdr.app.sdp_marker
+ report "Wrong " & g_statistics_type & " app.sdp_marker"
+ severity ERROR;
+ assert in_hdr.app.sdp_version_id = exp_hdr.app.sdp_version_id
+ report "Wrong " & g_statistics_type & " app.sdp_version_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_observation_id = exp_hdr.app.sdp_observation_id
+ report "Wrong " & g_statistics_type & " app.sdp_observation_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_station_info = exp_hdr.app.sdp_station_info
+ report "Wrong " & g_statistics_type & " app.sdp_station_info"
+ severity ERROR;
+
+ assert in_hdr.app.sdp_source_info_antenna_band_id = exp_hdr.app.sdp_source_info_antenna_band_id
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_antenna_band_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_nyquist_zone_id = exp_hdr.app.sdp_source_info_nyquist_zone_id
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_nyquist_zone_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_f_adc = exp_hdr.app.sdp_source_info_f_adc
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_f_adc"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_fsub_type = exp_hdr.app.sdp_source_info_fsub_type
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_fsub_type"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_payload_error = exp_hdr.app.sdp_source_info_payload_error
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_payload_error"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_beam_repositioning_flag = exp_hdr.app.sdp_source_info_beam_repositioning_flag
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_beam_repositioning_flag"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_weighted_subbands_flag = exp_hdr.app.sdp_source_info_weighted_subbands_flag
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_weighted_subbands_flag"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_gn_id = exp_hdr.app.sdp_source_info_gn_id
+ report "Wrong " & g_statistics_type & " app.sdp_source_info_gn_id"
+ severity ERROR;
+
+ assert in_hdr.app.sdp_reserved = exp_hdr.app.sdp_reserved
+ report "Wrong " & g_statistics_type & " app.sdp_reserved"
+ severity ERROR;
+ assert in_hdr.app.sdp_integration_interval = exp_hdr.app.sdp_integration_interval
+ report "Wrong " & g_statistics_type & " app.sdp_integration_interval"
+ severity ERROR;
-- . sdp_data_id word and fields per g_statistics_type
- assert in_hdr.app.sdp_data_id = exp_hdr.app.sdp_data_id report "Wrong " & g_statistics_type & " app.sdp_data_id" severity ERROR;
+ assert in_hdr.app.sdp_data_id = exp_hdr.app.sdp_data_id
+ report "Wrong " & g_statistics_type & " app.sdp_data_id"
+ severity ERROR;
if g_statistics_type = "SST" or g_statistics_type = "SST_OS" then
- assert in_hdr.app.sdp_data_id_sst_signal_input_index = exp_hdr.app.sdp_data_id_sst_signal_input_index report "Wrong " & g_statistics_type & " app.sdp_data_id_sst_signal_input_index" severity ERROR;
+ assert in_hdr.app.sdp_data_id_sst_signal_input_index = exp_hdr.app.sdp_data_id_sst_signal_input_index
+ report "Wrong " & g_statistics_type & " app.sdp_data_id_sst_signal_input_index"
+ severity ERROR;
elsif g_statistics_type = "BST" then
- assert in_hdr.app.sdp_data_id_bst_beamlet_index = exp_hdr.app.sdp_data_id_bst_beamlet_index report "Wrong " & g_statistics_type & " app.sdp_data_id_bst_beamlet_index" severity ERROR;
+ assert in_hdr.app.sdp_data_id_bst_beamlet_index = exp_hdr.app.sdp_data_id_bst_beamlet_index
+ report "Wrong " & g_statistics_type & " app.sdp_data_id_bst_beamlet_index"
+ severity ERROR;
elsif g_statistics_type = "XST" then
- assert in_hdr.app.sdp_data_id_xst_subband_index = exp_hdr.app.sdp_data_id_xst_subband_index report "Wrong " & g_statistics_type & " app.sdp_data_id_xst_subband_index" severity ERROR;
- assert in_hdr.app.sdp_data_id_xst_signal_input_A_index = exp_hdr.app.sdp_data_id_xst_signal_input_A_index report "Wrong " & g_statistics_type & " app.sdp_data_id_xst_signal_input_A_index" severity ERROR;
- assert in_hdr.app.sdp_data_id_xst_signal_input_B_index = exp_hdr.app.sdp_data_id_xst_signal_input_B_index report "Wrong " & g_statistics_type & " app.sdp_data_id_xst_signal_input_B_index" severity ERROR;
+ assert in_hdr.app.sdp_data_id_xst_subband_index = exp_hdr.app.sdp_data_id_xst_subband_index
+ report "Wrong " & g_statistics_type & " app.sdp_data_id_xst_subband_index"
+ severity ERROR;
+ assert in_hdr.app.sdp_data_id_xst_signal_input_A_index = exp_hdr.app.sdp_data_id_xst_signal_input_A_index
+ report "Wrong " & g_statistics_type & " app.sdp_data_id_xst_signal_input_A_index"
+ severity ERROR;
+ assert in_hdr.app.sdp_data_id_xst_signal_input_B_index = exp_hdr.app.sdp_data_id_xst_signal_input_B_index
+ report "Wrong " & g_statistics_type & " app.sdp_data_id_xst_signal_input_B_index"
+ severity ERROR;
else
- report "Wrong " & g_statistics_type severity FAILURE;
+ report "Wrong " & g_statistics_type
+ severity FAILURE;
end if;
- assert in_hdr.app.sdp_nof_signal_inputs = exp_hdr.app.sdp_nof_signal_inputs report "Wrong " & g_statistics_type & " app.sdp_nof_signal_inputs" severity ERROR;
- assert in_hdr.app.sdp_nof_bytes_per_statistic = exp_hdr.app.sdp_nof_bytes_per_statistic report "Wrong " & g_statistics_type & " app.sdp_nof_bytes_per_statistic" severity ERROR;
- assert in_hdr.app.sdp_nof_statistics_per_packet = exp_hdr.app.sdp_nof_statistics_per_packet report "Wrong " & g_statistics_type & " app.sdp_nof_statistics_per_packet" severity ERROR;
- assert in_hdr.app.sdp_block_period = exp_hdr.app.sdp_block_period report "Wrong " & g_statistics_type & " app.sdp_block_period" severity ERROR;
-
- assert in_hdr.app.dp_bsn = exp_hdr.app.dp_bsn report "Wrong " & g_statistics_type & " app.dp_bsn" severity ERROR;
+ assert in_hdr.app.sdp_nof_signal_inputs = exp_hdr.app.sdp_nof_signal_inputs
+ report "Wrong " & g_statistics_type & " app.sdp_nof_signal_inputs"
+ severity ERROR;
+ assert in_hdr.app.sdp_nof_bytes_per_statistic = exp_hdr.app.sdp_nof_bytes_per_statistic
+ report "Wrong " & g_statistics_type & " app.sdp_nof_bytes_per_statistic"
+ severity ERROR;
+ assert in_hdr.app.sdp_nof_statistics_per_packet = exp_hdr.app.sdp_nof_statistics_per_packet
+ report "Wrong " & g_statistics_type & " app.sdp_nof_statistics_per_packet"
+ severity ERROR;
+ assert in_hdr.app.sdp_block_period = exp_hdr.app.sdp_block_period
+ report "Wrong " & g_statistics_type & " app.sdp_block_period"
+ severity ERROR;
+
+ assert in_hdr.app.dp_bsn = exp_hdr.app.dp_bsn
+ report "Wrong " & g_statistics_type & " app.dp_bsn"
+ severity ERROR;
return true;
end func_sdp_verify_stat_header;
@@ -488,59 +577,137 @@ package body tb_sdp_pkg is
variable v_beamlet_index : natural;
begin
-- eth header
- assert in_hdr.eth.dst_mac = exp_hdr.eth.dst_mac report "Wrong beamlet eth.dst_mac" severity ERROR;
- assert in_hdr.eth.src_mac = exp_hdr.eth.src_mac report "Wrong beamlet eth.src_mac" severity ERROR;
- assert in_hdr.eth.eth_type = exp_hdr.eth.eth_type report "Wrong beamlet eth.eth_type" severity ERROR;
+ assert in_hdr.eth.dst_mac = exp_hdr.eth.dst_mac
+ report "Wrong beamlet eth.dst_mac"
+ severity ERROR;
+ assert in_hdr.eth.src_mac = exp_hdr.eth.src_mac
+ report "Wrong beamlet eth.src_mac"
+ severity ERROR;
+ assert in_hdr.eth.eth_type = exp_hdr.eth.eth_type
+ report "Wrong beamlet eth.eth_type"
+ severity ERROR;
-- ip header
- assert in_hdr.ip.version = exp_hdr.ip.version report "Wrong beamlet ip.version" severity ERROR;
- assert in_hdr.ip.header_length = exp_hdr.ip.header_length report "Wrong beamlet ip.header_length" severity ERROR;
- assert in_hdr.ip.services = exp_hdr.ip.services report "Wrong beamlet ip.services" severity ERROR;
- assert in_hdr.ip.total_length = exp_hdr.ip.total_length report "Wrong beamlet ip.total_length" severity ERROR;
- assert in_hdr.ip.identification = exp_hdr.ip.identification report "Wrong beamlet ip.identification" severity ERROR;
- assert in_hdr.ip.flags = exp_hdr.ip.flags report "Wrong beamlet ip.flags" severity ERROR;
- assert in_hdr.ip.fragment_offset = exp_hdr.ip.fragment_offset report "Wrong beamlet ip.fragment_offset" severity ERROR;
- assert in_hdr.ip.time_to_live = exp_hdr.ip.time_to_live report "Wrong beamlet ip.time_to_live" severity ERROR;
- assert in_hdr.ip.protocol = exp_hdr.ip.protocol report "Wrong beamlet ip.protocol" severity ERROR;
- assert in_hdr.ip.header_checksum = exp_hdr.ip.header_checksum report "Wrong beamlet ip.header_checksum" severity ERROR;
- assert in_hdr.ip.src_ip_addr = exp_hdr.ip.src_ip_addr report "Wrong beamlet ip.src_ip_addr" severity ERROR;
- assert in_hdr.ip.dst_ip_addr = exp_hdr.ip.dst_ip_addr report "Wrong beamlet ip.dst_ip_addr" severity ERROR;
+ assert in_hdr.ip.version = exp_hdr.ip.version
+ report "Wrong beamlet ip.version"
+ severity ERROR;
+ assert in_hdr.ip.header_length = exp_hdr.ip.header_length
+ report "Wrong beamlet ip.header_length"
+ severity ERROR;
+ assert in_hdr.ip.services = exp_hdr.ip.services
+ report "Wrong beamlet ip.services"
+ severity ERROR;
+ assert in_hdr.ip.total_length = exp_hdr.ip.total_length
+ report "Wrong beamlet ip.total_length"
+ severity ERROR;
+ assert in_hdr.ip.identification = exp_hdr.ip.identification
+ report "Wrong beamlet ip.identification"
+ severity ERROR;
+ assert in_hdr.ip.flags = exp_hdr.ip.flags
+ report "Wrong beamlet ip.flags"
+ severity ERROR;
+ assert in_hdr.ip.fragment_offset = exp_hdr.ip.fragment_offset
+ report "Wrong beamlet ip.fragment_offset"
+ severity ERROR;
+ assert in_hdr.ip.time_to_live = exp_hdr.ip.time_to_live
+ report "Wrong beamlet ip.time_to_live"
+ severity ERROR;
+ assert in_hdr.ip.protocol = exp_hdr.ip.protocol
+ report "Wrong beamlet ip.protocol"
+ severity ERROR;
+ assert in_hdr.ip.header_checksum = exp_hdr.ip.header_checksum
+ report "Wrong beamlet ip.header_checksum"
+ severity ERROR;
+ assert in_hdr.ip.src_ip_addr = exp_hdr.ip.src_ip_addr
+ report "Wrong beamlet ip.src_ip_addr"
+ severity ERROR;
+ assert in_hdr.ip.dst_ip_addr = exp_hdr.ip.dst_ip_addr
+ report "Wrong beamlet ip.dst_ip_addr"
+ severity ERROR;
-- udp header
- assert in_hdr.udp.src_port = exp_hdr.udp.src_port report "Wrong beamlet udp.src_port" severity ERROR;
- assert in_hdr.udp.dst_port = exp_hdr.udp.dst_port report "Wrong beamlet udp.dst_port" severity ERROR;
- assert in_hdr.udp.total_length = exp_hdr.udp.total_length report "Wrong beamlet udp.total_length" severity ERROR;
- assert in_hdr.udp.checksum = exp_hdr.udp.checksum report "Wrong beamlet udp.checksum" severity ERROR;
+ assert in_hdr.udp.src_port = exp_hdr.udp.src_port
+ report "Wrong beamlet udp.src_port"
+ severity ERROR;
+ assert in_hdr.udp.dst_port = exp_hdr.udp.dst_port
+ report "Wrong beamlet udp.dst_port"
+ severity ERROR;
+ assert in_hdr.udp.total_length = exp_hdr.udp.total_length
+ report "Wrong beamlet udp.total_length"
+ severity ERROR;
+ assert in_hdr.udp.checksum = exp_hdr.udp.checksum
+ report "Wrong beamlet udp.checksum"
+ severity ERROR;
-- app header
- assert in_hdr.app.sdp_marker = exp_hdr.app.sdp_marker report "Wrong beamlet app.sdp_marker" severity ERROR;
- assert in_hdr.app.sdp_version_id = exp_hdr.app.sdp_version_id report "Wrong beamlet app.sdp_version_id" severity ERROR;
- assert in_hdr.app.sdp_observation_id = exp_hdr.app.sdp_observation_id report "Wrong beamlet app.sdp_observation_id" severity ERROR;
- assert in_hdr.app.sdp_station_info = exp_hdr.app.sdp_station_info report "Wrong beamlet app.sdp_station_info" severity ERROR;
-
- assert in_hdr.app.sdp_source_info_reserved = exp_hdr.app.sdp_source_info_reserved report "Wrong beamlet app.sdp_source_info_reserved" severity ERROR;
- assert in_hdr.app.sdp_source_info_antenna_band_id = exp_hdr.app.sdp_source_info_antenna_band_id report "Wrong beamlet app.sdp_source_info_antenna_band_id" severity ERROR;
- assert in_hdr.app.sdp_source_info_nyquist_zone_id = exp_hdr.app.sdp_source_info_nyquist_zone_id report "Wrong beamlet app.sdp_source_info_nyquist_zone_id" severity ERROR;
- assert in_hdr.app.sdp_source_info_f_adc = exp_hdr.app.sdp_source_info_f_adc report "Wrong beamlet app.sdp_source_info_f_adc" severity ERROR;
- assert in_hdr.app.sdp_source_info_fsub_type = exp_hdr.app.sdp_source_info_fsub_type report "Wrong beamlet app.sdp_source_info_fsub_type" severity ERROR;
- assert in_hdr.app.sdp_source_info_payload_error = exp_hdr.app.sdp_source_info_payload_error report "Wrong beamlet app.sdp_source_info_payload_error" severity ERROR;
- assert in_hdr.app.sdp_source_info_beam_repositioning_flag = exp_hdr.app.sdp_source_info_beam_repositioning_flag report "Wrong beamlet app.sdp_source_info_beam_repositioning_flag" severity ERROR;
- assert in_hdr.app.sdp_source_info_beamlet_width = exp_hdr.app.sdp_source_info_beamlet_width report "Wrong beamlet app.sdp_source_info_beamlet_width" severity ERROR;
- assert in_hdr.app.sdp_source_info_gn_id = exp_hdr.app.sdp_source_info_gn_id report "Wrong beamlet app.sdp_source_info_gn_id" severity ERROR;
-
- assert in_hdr.app.sdp_reserved = exp_hdr.app.sdp_reserved report "Wrong beamlet app.sdp_reserved" severity ERROR;
- assert in_hdr.app.sdp_beamlet_scale = exp_hdr.app.sdp_beamlet_scale report "Wrong beamlet app.sdp_beamlet_scale" severity ERROR;
+ assert in_hdr.app.sdp_marker = exp_hdr.app.sdp_marker
+ report "Wrong beamlet app.sdp_marker"
+ severity ERROR;
+ assert in_hdr.app.sdp_version_id = exp_hdr.app.sdp_version_id
+ report "Wrong beamlet app.sdp_version_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_observation_id = exp_hdr.app.sdp_observation_id
+ report "Wrong beamlet app.sdp_observation_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_station_info = exp_hdr.app.sdp_station_info
+ report "Wrong beamlet app.sdp_station_info"
+ severity ERROR;
+
+ assert in_hdr.app.sdp_source_info_reserved = exp_hdr.app.sdp_source_info_reserved
+ report "Wrong beamlet app.sdp_source_info_reserved"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_antenna_band_id = exp_hdr.app.sdp_source_info_antenna_band_id
+ report "Wrong beamlet app.sdp_source_info_antenna_band_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_nyquist_zone_id = exp_hdr.app.sdp_source_info_nyquist_zone_id
+ report "Wrong beamlet app.sdp_source_info_nyquist_zone_id"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_f_adc = exp_hdr.app.sdp_source_info_f_adc
+ report "Wrong beamlet app.sdp_source_info_f_adc"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_fsub_type = exp_hdr.app.sdp_source_info_fsub_type
+ report "Wrong beamlet app.sdp_source_info_fsub_type"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_payload_error = exp_hdr.app.sdp_source_info_payload_error
+ report "Wrong beamlet app.sdp_source_info_payload_error"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_beam_repositioning_flag = exp_hdr.app.sdp_source_info_beam_repositioning_flag
+ report "Wrong beamlet app.sdp_source_info_beam_repositioning_flag"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_beamlet_width = exp_hdr.app.sdp_source_info_beamlet_width
+ report "Wrong beamlet app.sdp_source_info_beamlet_width"
+ severity ERROR;
+ assert in_hdr.app.sdp_source_info_gn_id = exp_hdr.app.sdp_source_info_gn_id
+ report "Wrong beamlet app.sdp_source_info_gn_id"
+ severity ERROR;
+
+ assert in_hdr.app.sdp_reserved = exp_hdr.app.sdp_reserved
+ report "Wrong beamlet app.sdp_reserved"
+ severity ERROR;
+ assert in_hdr.app.sdp_beamlet_scale = exp_hdr.app.sdp_beamlet_scale
+ report "Wrong beamlet app.sdp_beamlet_scale"
+ severity ERROR;
v_beamlet_index := TO_UINT(in_hdr.app.sdp_beamlet_index);
if beamlet_index_mod then
-- Treat beamlet_index modulo c_sdp_S_sub_bf, because the beamlet packets from different beamsets may arrive in arbitrary order
v_beamlet_index := v_beamlet_index mod c_sdp_S_sub_bf;
end if;
- assert v_beamlet_index = TO_UINT(exp_hdr.app.sdp_beamlet_index) report "Wrong beamlet app.sdp_beamlet_index" severity ERROR;
- assert in_hdr.app.sdp_nof_blocks_per_packet = exp_hdr.app.sdp_nof_blocks_per_packet report "Wrong beamlet app.sdp_nof_blocks_per_packet" severity ERROR;
- assert in_hdr.app.sdp_nof_beamlets_per_block = exp_hdr.app.sdp_nof_beamlets_per_block report "Wrong beamlet app.sdp_nof_beamlets_per_block" severity ERROR;
- assert in_hdr.app.sdp_block_period = exp_hdr.app.sdp_block_period report "Wrong beamlet app.sdp_block_period" severity ERROR;
-
- assert in_hdr.app.dp_bsn = exp_hdr.app.dp_bsn report "Wrong beamlet app.dp_bsn" severity ERROR;
+ assert v_beamlet_index = TO_UINT(exp_hdr.app.sdp_beamlet_index)
+ report "Wrong beamlet app.sdp_beamlet_index"
+ severity ERROR;
+ assert in_hdr.app.sdp_nof_blocks_per_packet = exp_hdr.app.sdp_nof_blocks_per_packet
+ report "Wrong beamlet app.sdp_nof_blocks_per_packet"
+ severity ERROR;
+ assert in_hdr.app.sdp_nof_beamlets_per_block = exp_hdr.app.sdp_nof_beamlets_per_block
+ report "Wrong beamlet app.sdp_nof_beamlets_per_block"
+ severity ERROR;
+ assert in_hdr.app.sdp_block_period = exp_hdr.app.sdp_block_period
+ report "Wrong beamlet app.sdp_block_period"
+ severity ERROR;
+
+ assert in_hdr.app.dp_bsn = exp_hdr.app.dp_bsn
+ report "Wrong beamlet app.dp_bsn"
+ severity ERROR;
return true;
end func_sdp_verify_cep_header;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index d7b7ac5602..5b2da154df 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -250,7 +250,9 @@ architecture tb of tb_sdp_statistics_offload is
signal dbg_c_nof_clk_per_sync : natural := c_nof_clk_per_sync;
begin
-- Check consistency of constant value dependencies
- assert c_ram_size = c_mm_ram_size report "Wrong derivation of RAM size." severity FAILURE;
+ assert c_ram_size = c_mm_ram_size
+ report "Wrong derivation of RAM size."
+ severity FAILURE;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
@@ -436,7 +438,9 @@ begin
begin
if rising_edge(dp_clk) then
if rx_offload_sosi.sync = '1' and rx_sync_cnt > 1 then
- assert rx_packet_cnt = c_rx_nof_packets report "Wrong number of packets per sync interval" severity ERROR;
+ assert rx_packet_cnt = c_rx_nof_packets
+ report "Wrong number of packets per sync interval"
+ severity ERROR;
end if;
end if;
end process;
@@ -446,7 +450,9 @@ begin
if rising_edge(dp_clk) then
if rx_offload_sosi.eop = '1' then
rx_valid_cnt <= 0;
- assert rx_valid_cnt = c_packet_size - 1 report "Wrong number of valid per packet" severity ERROR;
+ assert rx_valid_cnt = c_packet_size - 1
+ report "Wrong number of valid per packet"
+ severity ERROR;
elsif rx_offload_sosi.valid = '1' then
rx_valid_cnt <= rx_valid_cnt + 1;
end if;
@@ -531,7 +537,9 @@ begin
else
v_exp_data := v_exp_data - I + c_mm_user_size-1;
end if;
- assert v_exp_data = v_rx_data report "Wrong BST payload data Rx" severity ERROR;
+ assert v_exp_data = v_rx_data
+ report "Wrong BST payload data Rx"
+ severity ERROR;
elsif g_statistics_type = "XST" then
-- . c_nof_used_P_sq = 4
@@ -576,7 +584,9 @@ begin
end if;
v_exp_data := v_exp_data + J * c_packet_size; -- c_packet_size = 576
v_exp_data := v_exp_data + K * c_mm_Xsq_span; -- c_mm_Xsq_span = 4096
- assert v_exp_data = v_rx_data report "Wrong XST payload data Rx" severity ERROR;
+ assert v_exp_data = v_rx_data
+ report "Wrong XST payload data Rx"
+ severity ERROR;
end if;
-- for debug in wave window
rx_val <= '1';
@@ -691,7 +701,9 @@ begin
);
-- Verify crosslets_info functions
- assert c_crosslets_info_rec = func_sdp_map_crosslets_info(c_crosslets_info_slv) report "Error in func_sdp_map_crosslets_info()" severity FAILURE;
+ assert c_crosslets_info_rec = func_sdp_map_crosslets_info(c_crosslets_info_slv)
+ report "Error in func_sdp_map_crosslets_info()"
+ severity FAILURE;
-- To view the 32 bit 1GbE offload data more easily in the Wave window
sdp_offload_data <= sdp_offload_sosi.data(c_word_w - 1 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd b/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
index a2a3ee4571..2dee1870b7 100644
--- a/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
+++ b/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
@@ -365,37 +365,42 @@ begin
-- Verify, only log when wrong
if c_bg_nof_bps_total < 10.0**9 then
- assert tx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ assert tx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Tx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Rx total nof packets count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ assert rx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof packets count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_valid_arr(I) = rx_exp_total_count_nof_valid_arr(I) report c_tb_str &
- "Wrong Rx total nof valids count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
+ assert rx_total_count_nof_valid_arr(I) = rx_exp_total_count_nof_valid_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof valids count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I) report c_tb_str &
- "Wrong Rx total nof corrupted count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
+ assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof corrupted count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
" = Expected count" severity ERROR;
else
-- Verify that Tx total nof packets = Rx total nof packets, also when
-- BG experiences siso.xon block level flow control, to stay below
-- 1 Gbps of the 1GbE link rate.
- assert tx_total_count_nof_packet_arr(I) = rx_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ assert tx_total_count_nof_packet_arr(I) = rx_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
" = Rx count" severity ERROR;
end if;
end loop;
@@ -431,17 +436,22 @@ begin
-- the ETH data rate < 1 Gbps and no BG block flow control.
-- Verify, only log when wrong
if I = 0 then
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first
+ report
c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx
+ report
c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
else
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others
+ report
c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx
+ report
c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
end if;
- assert tx_mon_latency_arr(I) = c_tx_exp_latency report
+ assert tx_mon_latency_arr(I) = c_tx_exp_latency
+ report
c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
-- For short block lengths the Rx latency appears to become less, the
@@ -449,7 +459,8 @@ begin
-- latency is not critical, therefore it is sufficient to only very
-- the latency when it is more or less fixed.
if c_rx_exp_latency_en then
- assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10) report
+ assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10)
+ report
c_tb_str & "Wrong rx latency using st interface (" & natural'image(I) & ")" severity ERROR;
end if;
end if;
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
index 4c5582c7f9..07cd065701 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
@@ -255,14 +255,30 @@ begin
proc_common_wait_some_cycles(dp_clk, 1);
-- assert when header is not as expected.
- assert rx_rdma_header = exp_rdma_header report "Wrong rx_rdma_header" severity error;
- assert rx_rdma_header.ip.total_length = exp_rdma_header.ip.total_length report "Wrong rx_rdma_header.ip.total_length value" severity error;
- assert rx_rdma_header.udp.total_length = exp_rdma_header.udp.total_length report "Wrong rx_rdma_header.udp.total_length value" severity error;
- assert rx_rdma_header.bth.opcode = exp_rdma_header.bth.opcode report "Wrong rx_rdma_header.bth.opcode value" severity error;
- assert rx_rdma_header.bth.psn = exp_rdma_header.bth.psn report "Wrong rx_rdma_header.bth.psn value" severity error;
- assert rx_rdma_header.reth.virtual_address = exp_rdma_header.reth.virtual_address report "Wrong rx_rdma_header.reth.virtual_address value" severity error;
- assert rx_rdma_header.reth.dma_length = exp_rdma_header.reth.dma_length report "Wrong rx_rdma_header.reth.dma_length value" severity error;
- assert rx_rdma_header.immediate_data = exp_rdma_header.immediate_data report "Wrong rx_rdma_header.immediate_data value" severity error;
+ assert rx_rdma_header = exp_rdma_header
+ report "Wrong rx_rdma_header"
+ severity error;
+ assert rx_rdma_header.ip.total_length = exp_rdma_header.ip.total_length
+ report "Wrong rx_rdma_header.ip.total_length value"
+ severity error;
+ assert rx_rdma_header.udp.total_length = exp_rdma_header.udp.total_length
+ report "Wrong rx_rdma_header.udp.total_length value"
+ severity error;
+ assert rx_rdma_header.bth.opcode = exp_rdma_header.bth.opcode
+ report "Wrong rx_rdma_header.bth.opcode value"
+ severity error;
+ assert rx_rdma_header.bth.psn = exp_rdma_header.bth.psn
+ report "Wrong rx_rdma_header.bth.psn value"
+ severity error;
+ assert rx_rdma_header.reth.virtual_address = exp_rdma_header.reth.virtual_address
+ report "Wrong rx_rdma_header.reth.virtual_address value"
+ severity error;
+ assert rx_rdma_header.reth.dma_length = exp_rdma_header.reth.dma_length
+ report "Wrong rx_rdma_header.reth.dma_length value"
+ severity error;
+ assert rx_rdma_header.immediate_data = exp_rdma_header.immediate_data
+ report "Wrong rx_rdma_header.immediate_data value"
+ severity error;
end loop;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index d13377d1b3..ce0c365be3 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -385,7 +385,9 @@ architecture str of top is
signal this_rn_id : std_logic_vector(c_sdp_W_gn_id - 1 downto 0);
signal sdp_info : t_sdp_info := c_sdp_info_rst;
begin
- assert g_nof_lanes <= c_nof_streams_ring report "g_nof_lanes is configured too high!" severity ERROR;
+ assert g_nof_lanes <= c_nof_streams_ring
+ report "g_nof_lanes is configured too high!"
+ severity ERROR;
------------
-- Front IO
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 931a44d841..b7b648148e 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -125,7 +125,9 @@ architecture str of ta2_channel_cross is
signal dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
begin
- assert g_nof_bytes <= 32 report "g_nof_bytes of ta2_channel_cross is configured higher than 32" severity ERROR;
+ assert g_nof_bytes <= 32
+ report "g_nof_bytes of ta2_channel_cross is configured higher than 32"
+ severity ERROR;
gen_streams: for stream in 0 to g_nof_streams - 1 generate
-- dp_snk_in -> kernel_src_out
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
index 262dbfdd93..53eb27d0a2 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -68,7 +68,9 @@ begin
p_verify : process
begin
wait until tb_end = '1';
- assert TO_UINT(mm_miso.rddata(31 downto 0)) = c_data_value report "Wrong read data." severity ERROR;
+ assert TO_UINT(mm_miso.rddata(31 downto 0)) = c_data_value
+ report "Wrong read data."
+ severity ERROR;
end process;
u_dut : entity work.ta2_unb2b_mm_io
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
index 6c96281275..4470cf6bff 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
@@ -351,7 +351,8 @@ begin
cmdr_result_error_cnt(c_A) <= TO_UINT(reg_commander_miso_arr(c_A).rddata);
proc_common_wait_some_cycles(mm_clk, 1);
assert cmdr_result_error_cnt(c_A) = 0
- report "The result error count is not 0" severity ERROR;
+ report "The result error count is not 0"
+ severity ERROR;
-- Read commander result data
for J in 0 to c_i2c_cmdr_aduh_nof_result_data_arr(c_P) - 1 loop
@@ -371,8 +372,12 @@ begin
end loop;
proc_common_wait_some_cycles(mm_clk, 100);
i2c_adu_stimuli_done <= '1';
- assert cmdr_result_data = exp_result_data report "Unexpected ADU temperature read via I2C" severity ERROR;
- assert cmdr_result_error_cnt = exp_result_error_cnt report "Unexpected ADU I2C access error count > 0" severity ERROR;
+ assert cmdr_result_data = exp_result_data
+ report "Unexpected ADU temperature read via I2C"
+ severity ERROR;
+ assert cmdr_result_error_cnt = exp_result_error_cnt
+ report "Unexpected ADU I2C access error count > 0"
+ severity ERROR;
wait;
end process;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index 3c4226b3cc..54bddf1eda 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -329,8 +329,12 @@ begin
proc_mem_mm_bus_rd(0, mm_clk, reg_adc_quad_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); aduh_ab_locked <= reg_adc_quad_miso.rddata(31 downto 0);
proc_mem_mm_bus_rd(1, mm_clk, reg_adc_quad_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); aduh_cd_locked <= reg_adc_quad_miso.rddata(31 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
- assert TO_UINT(aduh_ab_locked(1 downto 0)) = 3 report "ADU-AB input not locked" severity ERROR;
- assert TO_UINT(aduh_cd_locked(1 downto 0)) = 3 report "ADU-CD input not locked" severity ERROR;
+ assert TO_UINT(aduh_ab_locked(1 downto 0)) = 3
+ report "ADU-AB input not locked"
+ severity ERROR;
+ assert TO_UINT(aduh_cd_locked(1 downto 0)) = 3
+ report "ADU-CD input not locked"
+ severity ERROR;
-- Read signal path statistics for [0,1,2,3] = [A,B,C,D]
-- * address 0:1 = 64b mean sum (LSWord first)
@@ -392,8 +396,12 @@ begin
exp_power_sum <= (others => TO_UVEC(396343296, 64)); -- exact expected power sum for Fs/16 full scale sinus = [4*(49**2 + 90**2 + 117**2) + 2*(0**2 + 127**2)] * 48/16 * 1024 = 396343296
proc_common_wait_some_cycles(mm_clk, 1);
for I in 0 to c_ai.nof_sp - 1 loop
- assert stat_mean_sum(I) = exp_mean_sum(I) report "Wrong mean sum value for sinus" severity ERROR;
- assert stat_power_sum(I) = exp_power_sum(I) report "Wrong power sum value for sinus" severity ERROR;
+ assert stat_mean_sum(I) = exp_mean_sum(I)
+ report "Wrong mean sum value for sinus"
+ severity ERROR;
+ assert stat_power_sum(I) = exp_power_sum(I)
+ report "Wrong power sum value for sinus"
+ severity ERROR;
end loop;
verify_stat_done <= '1';
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
index b521c00a23..4a43adb619 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
@@ -110,5 +110,7 @@ begin
-- Test bench end
------------------------------------------------------------------------------
- assert not(NOW > 0 ps and tb_end = '1') report "Note: TB END" severity FAILURE; -- need to use FAILURE to stop the simulation, apparently resetting the tr_nonbonded is not enough
+ assert not(NOW > 0 ps and tb_end = '1')
+ report "Note: TB END"
+ severity FAILURE; -- need to use FAILURE to stop the simulation, apparently resetting the tr_nonbonded is not enough
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
index 984cbc8b4c..204e317060 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
@@ -245,10 +245,18 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_unb_sens, 5, rd_data, tb_clk); rd_temp_high <= TO_SINT(rd_data);
proc_common_wait_some_cycles(tb_clk, 1);
- assert rd_fpga_temp = c_fpga_temp report "REG_UNB_SENS wrong FPGA temperature" severity ERROR;
- assert rd_eth_temp = c_eth_temp report "REG_UNB_SENS wrong ETH temperature" severity ERROR;
- assert rd_sens_err = 0 report "REG_UNB_SENS I2C access went wrong" severity ERROR;
- assert rd_temp_high = c_temp_high report "REG_UNB_SENS wrong high temperature" severity ERROR;
+ assert rd_fpga_temp = c_fpga_temp
+ report "REG_UNB_SENS wrong FPGA temperature"
+ severity ERROR;
+ assert rd_eth_temp = c_eth_temp
+ report "REG_UNB_SENS wrong ETH temperature"
+ severity ERROR;
+ assert rd_sens_err = 0
+ report "REG_UNB_SENS I2C access went wrong"
+ severity ERROR;
+ assert rd_temp_high = c_temp_high
+ report "REG_UNB_SENS wrong high temperature"
+ severity ERROR;
----------------------------------------------------------------------------
-- Read PPSH
@@ -262,7 +270,9 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_ppsh, 0, rd_data, tb_clk);
proc_common_wait_some_cycles(tb_clk, 1);
- assert rd_ppsh_toggle = not rd_data(31) report "REG_PPHS wrong toggle" severity ERROR;
+ assert rd_ppsh_toggle = not rd_data(31)
+ report "REG_PPHS wrong toggle"
+ severity ERROR;
-- verify PPS edge, stable and capture cnt and expected cnt
-- The capture cnt and expected cnt cannot be equal in this simulation so therefore PPS will not become stable
@@ -278,10 +288,18 @@ begin
rd_ppsh_expected_cnt <= TO_UINT(rd_data(30 downto 0));
proc_common_wait_some_cycles(tb_clk, 1);
- assert rd_ppsh_stable = '0' report "REG_PPHS wrong stable" severity ERROR;
- assert rd_ppsh_capture_cnt = c_ext_pps_period report "REG_PPHS wrong capture count" severity ERROR;
- assert rd_ppsh_edge = '0' report "REG_PPHS wrong edge" severity ERROR;
- assert rd_ppsh_expected_cnt = c_extpected_cnt report "REG_PPHS wrong capture count" severity ERROR;
+ assert rd_ppsh_stable = '0'
+ report "REG_PPHS wrong stable"
+ severity ERROR;
+ assert rd_ppsh_capture_cnt = c_ext_pps_period
+ report "REG_PPHS wrong capture count"
+ severity ERROR;
+ assert rd_ppsh_edge = '0'
+ report "REG_PPHS wrong edge"
+ severity ERROR;
+ assert rd_ppsh_expected_cnt = c_extpected_cnt
+ report "REG_PPHS wrong capture count"
+ severity ERROR;
proc_common_wait_some_cycles(tb_clk, 10);
tb_end <= '1';
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index ca4d940d7b..23432ff479 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -134,15 +134,25 @@ begin
wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
proc_common_wait_until_high(clk, sens_val);
- assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(0)
+ report "Wrong FPGA temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(1) report "Wrong ETH temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(1)
+ report "Wrong ETH temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(2) report "Wrong hot swap V sense value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(2)
+ report "Wrong hot swap V sense value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(3)
+ report "Wrong hot swap V source value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(4)
+ report "An I2C error occurred"
+ severity ERROR;
end process;
-- I2C sensors master
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index 4040873b96..abb4bbfabc 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -206,11 +206,19 @@ begin
begin
if rising_edge(clk) then
-- SOSI
- assert fn_tx_valid = bn_rx_valid report "Mesh bn_rx_valid error" severity ERROR;
- assert bn_tx_valid = fn_rx_valid report "Mesh fn_rx_valid error" severity ERROR;
+ assert fn_tx_valid = bn_rx_valid
+ report "Mesh bn_rx_valid error"
+ severity ERROR;
+ assert bn_tx_valid = fn_rx_valid
+ report "Mesh fn_rx_valid error"
+ severity ERROR;
-- SISO
- assert fn_rx_ready = bn_tx_ready report "Mesh bn_tx_ready error" severity ERROR;
- assert bn_rx_ready = fn_tx_ready report "Mesh fn_tx_ready error" severity ERROR;
+ assert fn_rx_ready = bn_tx_ready
+ report "Mesh bn_tx_ready error"
+ severity ERROR;
+ assert bn_rx_ready = fn_tx_ready
+ report "Mesh fn_tx_ready error"
+ severity ERROR;
end if;
end process;
@@ -290,8 +298,12 @@ begin
p_verify_serial : process(clk)
begin
if rising_edge(clk) then
- assert bn_rx_phy_sl = bn_rx_phy_valid report "unb1_board_mesh_model_sl FN->BN error" severity ERROR;
- assert fn_rx_phy_sl = fn_rx_phy_valid report "unb1_board_mesh_model_sl BN->FN error" severity ERROR;
+ assert bn_rx_phy_sl = bn_rx_phy_valid
+ report "unb1_board_mesh_model_sl FN->BN error"
+ severity ERROR;
+ assert fn_rx_phy_sl = fn_rx_phy_valid
+ report "unb1_board_mesh_model_sl BN->FN error"
+ severity ERROR;
end if;
end process;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 66f15cf9b1..2624bb02ed 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -1079,8 +1079,12 @@ begin
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
- assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio) report "unb2_test: DDR4 data widths are not an integer ratio" severity FAILURE;
- assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II) report "unb2_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
+ assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio)
+ report "unb2_test: DDR4 data widths are not an integer ratio"
+ severity FAILURE;
+ assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II)
+ report "unb2_test: DDR4 MB_I and MB_II must have the same ctlr data widths"
+ severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 3449629f92..4194722980 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -134,15 +134,25 @@ begin
wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
proc_common_wait_until_high(clk, sens_val);
- assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(0)
+ report "Wrong FPGA temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(1) report "Wrong ETH temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(1)
+ report "Wrong ETH temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(2) report "Wrong hot swap V sense value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(2)
+ report "Wrong hot swap V sense value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(3)
+ report "Wrong hot swap V source value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(4)
+ report "An I2C error occurred"
+ severity ERROR;
end process;
-- I2C sensors master
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index 8ff0a270b2..0acc2b320e 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -432,7 +432,9 @@ architecture str of unb2a_test is
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
begin
- assert false report "g_design_name=" & g_design_name severity WARNING;
+ assert false
+ report "g_design_name=" & g_design_name
+ severity WARNING;
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -1091,8 +1093,12 @@ begin
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
- assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio) report "unb2a_test: DDR4 data widths are not an integer ratio" severity FAILURE;
- assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II) report "unb2a_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
+ assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio)
+ report "unb2a_test: DDR4 data widths are not an integer ratio"
+ severity FAILURE;
+ assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II)
+ report "unb2a_test: DDR4 MB_I and MB_II must have the same ctlr data widths"
+ severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index a91ab0e90c..5b08ac5ac1 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -135,15 +135,25 @@ begin
wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
proc_common_wait_until_high(clk, sens_val);
- assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(0)
+ report "Wrong FPGA temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(1) report "Wrong ETH temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(1)
+ report "Wrong ETH temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(2) report "Wrong hot swap V sense value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(2)
+ report "Wrong hot swap V sense value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(3)
+ report "Wrong hot swap V source value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(4)
+ report "An I2C error occurred"
+ severity ERROR;
end process;
-- I2C sensors master
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
index e506669594..d51cd74dd4 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
@@ -628,19 +628,24 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt + rx_pkt_discarded_cnt + TO_UINT(rx_pkt_flushed_cnt) then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
wait for 1 us;
tb_end <= '1';
if g_tb_end = false then
- report "Tb simulation finished." severity NOTE;
+ report "Tb simulation finished."
+ severity NOTE;
else
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
index ce140222f1..5158a89c4c 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
@@ -71,7 +71,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
index 7acf42ed8e..71f3a1a8ae 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
@@ -556,19 +556,24 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt + rx_pkt_discarded_cnt + TO_UINT(rx_pkt_flushed_cnt) then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
wait for 1 us;
tb_end <= '1';
if g_tb_end = false then
- report "Tb simulation finished." severity NOTE;
+ report "Tb simulation finished."
+ severity NOTE;
else
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 39b5813291..a5284764c0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -673,7 +673,9 @@ package body common_pkg is
elsif operation = "OR" then v_stage_arr := (others => (others => '0'));
elsif operation = "XOR" then v_stage_arr := (others => (others => '0'));
else
- assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
+ assert true
+ report "common_pkg: Unsupported vector_tree operation"
+ severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
@@ -2161,9 +2163,15 @@ package body common_pkg is
-- Therefore only check on wr_full going high when wr_rst='0'.
--synthesis translate_off
- assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
- assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
- assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+ assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1')
+ report c_fifo_name & " : read from empty fifo occurred!"
+ severity FAILURE;
+ assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0')
+ report c_fifo_name & " : fifo is full now"
+ severity NOTE;
+ assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1')
+ report c_fifo_name & " : fifo overflow occurred!"
+ severity FAILURE;
--synthesis translate_on
end procedure proc_common_fifo_asserts;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 8f2d68af5f..7221f10110 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -406,7 +406,8 @@ package body dp_stream_pkg is
if rising_edge(clk) then
-- Check DP sink
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
@@ -437,7 +438,8 @@ package body dp_stream_pkg is
for i in 0 to sosi_arr'length - 1 loop
-- Check DP sink
if sosi_arr(i).valid = '1' and ready_reg(i * (c_ready_latency + 1) + 1) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg(i * (c_ready_latency + 1) + 1 to i * (c_ready_latency + 1) + c_ready_latency) <= ready_reg(i * (c_ready_latency + 1) to i * (c_ready_latency + 1) + c_ready_latency - 1);
end loop;
@@ -609,7 +611,9 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
+ assert nof_symbols_from_tail < vN
+ report "func_dp_data_shift_first : no symbols from head"
+ severity FAILURE;
-- use the other sosi from head_sosi
v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
for I in 1 to vN - 1 loop -- I > 0
@@ -659,8 +663,12 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert vK > 0 report "func_dp_data_shift_last : no symbols from tail" severity FAILURE;
- assert vK + vL <= vN report "func_dp_data_shift_last : impossible shift" severity FAILURE;
+ assert vK > 0
+ report "func_dp_data_shift_last : no symbols from tail"
+ severity FAILURE;
+ assert vK + vL <= vN
+ report "func_dp_data_shift_last : impossible shift"
+ severity FAILURE;
v_sosi := tail_sosi;
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 39b5813291..a5284764c0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -673,7 +673,9 @@ package body common_pkg is
elsif operation = "OR" then v_stage_arr := (others => (others => '0'));
elsif operation = "XOR" then v_stage_arr := (others => (others => '0'));
else
- assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
+ assert true
+ report "common_pkg: Unsupported vector_tree operation"
+ severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
@@ -2161,9 +2163,15 @@ package body common_pkg is
-- Therefore only check on wr_full going high when wr_rst='0'.
--synthesis translate_off
- assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
- assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
- assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+ assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1')
+ report c_fifo_name & " : read from empty fifo occurred!"
+ severity FAILURE;
+ assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0')
+ report c_fifo_name & " : fifo is full now"
+ severity NOTE;
+ assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1')
+ report c_fifo_name & " : fifo overflow occurred!"
+ severity FAILURE;
--synthesis translate_on
end procedure proc_common_fifo_asserts;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 8f2d68af5f..7221f10110 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -406,7 +406,8 @@ package body dp_stream_pkg is
if rising_edge(clk) then
-- Check DP sink
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
@@ -437,7 +438,8 @@ package body dp_stream_pkg is
for i in 0 to sosi_arr'length - 1 loop
-- Check DP sink
if sosi_arr(i).valid = '1' and ready_reg(i * (c_ready_latency + 1) + 1) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg(i * (c_ready_latency + 1) + 1 to i * (c_ready_latency + 1) + c_ready_latency) <= ready_reg(i * (c_ready_latency + 1) to i * (c_ready_latency + 1) + c_ready_latency - 1);
end loop;
@@ -609,7 +611,9 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
+ assert nof_symbols_from_tail < vN
+ report "func_dp_data_shift_first : no symbols from head"
+ severity FAILURE;
-- use the other sosi from head_sosi
v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
for I in 1 to vN - 1 loop -- I > 0
@@ -659,8 +663,12 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert vK > 0 report "func_dp_data_shift_last : no symbols from tail" severity FAILURE;
- assert vK + vL <= vN report "func_dp_data_shift_last : impossible shift" severity FAILURE;
+ assert vK > 0
+ report "func_dp_data_shift_last : no symbols from tail"
+ severity FAILURE;
+ assert vK + vL <= vN
+ report "func_dp_data_shift_last : impossible shift"
+ severity FAILURE;
v_sosi := tail_sosi;
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 39b5813291..a5284764c0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -673,7 +673,9 @@ package body common_pkg is
elsif operation = "OR" then v_stage_arr := (others => (others => '0'));
elsif operation = "XOR" then v_stage_arr := (others => (others => '0'));
else
- assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
+ assert true
+ report "common_pkg: Unsupported vector_tree operation"
+ severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
@@ -2161,9 +2163,15 @@ package body common_pkg is
-- Therefore only check on wr_full going high when wr_rst='0'.
--synthesis translate_off
- assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
- assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
- assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+ assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1')
+ report c_fifo_name & " : read from empty fifo occurred!"
+ severity FAILURE;
+ assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0')
+ report c_fifo_name & " : fifo is full now"
+ severity NOTE;
+ assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1')
+ report c_fifo_name & " : fifo overflow occurred!"
+ severity FAILURE;
--synthesis translate_on
end procedure proc_common_fifo_asserts;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 8f2d68af5f..7221f10110 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -406,7 +406,8 @@ package body dp_stream_pkg is
if rising_edge(clk) then
-- Check DP sink
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
@@ -437,7 +438,8 @@ package body dp_stream_pkg is
for i in 0 to sosi_arr'length - 1 loop
-- Check DP sink
if sosi_arr(i).valid = '1' and ready_reg(i * (c_ready_latency + 1) + 1) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg(i * (c_ready_latency + 1) + 1 to i * (c_ready_latency + 1) + c_ready_latency) <= ready_reg(i * (c_ready_latency + 1) to i * (c_ready_latency + 1) + c_ready_latency - 1);
end loop;
@@ -609,7 +611,9 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
+ assert nof_symbols_from_tail < vN
+ report "func_dp_data_shift_first : no symbols from head"
+ severity FAILURE;
-- use the other sosi from head_sosi
v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
for I in 1 to vN - 1 loop -- I > 0
@@ -659,8 +663,12 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert vK > 0 report "func_dp_data_shift_last : no symbols from tail" severity FAILURE;
- assert vK + vL <= vN report "func_dp_data_shift_last : impossible shift" severity FAILURE;
+ assert vK > 0
+ report "func_dp_data_shift_last : no symbols from tail"
+ severity FAILURE;
+ assert vK + vL <= vN
+ report "func_dp_data_shift_last : impossible shift"
+ severity FAILURE;
v_sosi := tail_sosi;
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 39b5813291..a5284764c0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -673,7 +673,9 @@ package body common_pkg is
elsif operation = "OR" then v_stage_arr := (others => (others => '0'));
elsif operation = "XOR" then v_stage_arr := (others => (others => '0'));
else
- assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
+ assert true
+ report "common_pkg: Unsupported vector_tree operation"
+ severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
@@ -2161,9 +2163,15 @@ package body common_pkg is
-- Therefore only check on wr_full going high when wr_rst='0'.
--synthesis translate_off
- assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
- assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
- assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+ assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1')
+ report c_fifo_name & " : read from empty fifo occurred!"
+ severity FAILURE;
+ assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0')
+ report c_fifo_name & " : fifo is full now"
+ severity NOTE;
+ assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1')
+ report c_fifo_name & " : fifo overflow occurred!"
+ severity FAILURE;
--synthesis translate_on
end procedure proc_common_fifo_asserts;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 8f2d68af5f..7221f10110 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -406,7 +406,8 @@ package body dp_stream_pkg is
if rising_edge(clk) then
-- Check DP sink
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
@@ -437,7 +438,8 @@ package body dp_stream_pkg is
for i in 0 to sosi_arr'length - 1 loop
-- Check DP sink
if sosi_arr(i).valid = '1' and ready_reg(i * (c_ready_latency + 1) + 1) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg(i * (c_ready_latency + 1) + 1 to i * (c_ready_latency + 1) + c_ready_latency) <= ready_reg(i * (c_ready_latency + 1) to i * (c_ready_latency + 1) + c_ready_latency - 1);
end loop;
@@ -609,7 +611,9 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
+ assert nof_symbols_from_tail < vN
+ report "func_dp_data_shift_first : no symbols from head"
+ severity FAILURE;
-- use the other sosi from head_sosi
v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
for I in 1 to vN - 1 loop -- I > 0
@@ -659,8 +663,12 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert vK > 0 report "func_dp_data_shift_last : no symbols from tail" severity FAILURE;
- assert vK + vL <= vN report "func_dp_data_shift_last : impossible shift" severity FAILURE;
+ assert vK > 0
+ report "func_dp_data_shift_last : no symbols from tail"
+ severity FAILURE;
+ assert vK + vL <= vN
+ report "func_dp_data_shift_last : impossible shift"
+ severity FAILURE;
v_sosi := tail_sosi;
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index c2449c7172..44fc1bea8d 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -429,7 +429,9 @@ architecture str of unb2b_test is
signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
begin
- assert false report "g_design_name=" & g_design_name severity WARNING;
+ assert false
+ report "g_design_name=" & g_design_name
+ severity WARNING;
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -1083,8 +1085,12 @@ begin
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
- assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio) report "unb2b_test: DDR4 data widths are not an integer ratio" severity FAILURE;
- assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II) report "unb2b_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
+ assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio)
+ report "unb2b_test: DDR4 data widths are not an integer ratio"
+ severity FAILURE;
+ assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II)
+ report "unb2b_test: DDR4 MB_I and MB_II must have the same ctlr data widths"
+ severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index ef80a940f5..c0ad6b0c9c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -135,15 +135,25 @@ begin
wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
proc_common_wait_until_high(clk, sens_val);
- assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(0)
+ report "Wrong FPGA temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(1) report "Wrong ETH temperature value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(1)
+ report "Wrong ETH temperature value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(2) report "Wrong hot swap V sense value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(2)
+ report "Wrong hot swap V sense value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(3)
+ report "Wrong hot swap V source value"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
+ assert TO_UINT(sens_dat) = c_sens_expected(4)
+ report "An I2C error occurred"
+ severity ERROR;
end process;
-- I2C sensors master
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index a2b0e6140e..0141de7e02 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -470,7 +470,9 @@ architecture str of unb2c_test is
signal qsfp_green_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
begin
- assert false report "g_design_name = " & g_design_name severity NOTE;
+ assert false
+ report "g_design_name = " & g_design_name
+ severity NOTE;
gn_index <= TO_UINT(ID);
@@ -1267,8 +1269,12 @@ begin
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
- assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio) report "unb2c_test: DDR4 data widths are not an integer ratio" severity FAILURE;
- assert func_tech_ddr_ctlr_data_w(c_ddr_MB_I) = func_tech_ddr_ctlr_data_w(c_ddr_MB_II) report "unb2c_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
+ assert c_ddr_mixed_width_ratio > 0 and is_pow2(c_ddr_mixed_width_ratio)
+ report "unb2c_test: DDR4 data widths are not an integer ratio"
+ severity FAILURE;
+ assert func_tech_ddr_ctlr_data_w(c_ddr_MB_I) = func_tech_ddr_ctlr_data_w(c_ddr_MB_II)
+ report "unb2c_test: DDR4 MB_I and MB_II must have the same ctlr data widths"
+ severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index 83b3b3e514..35dd9ca653 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -201,7 +201,8 @@ package body axi4_stream_pkg is
if rising_edge(clk) then
-- Check DP sink
if sosi.tvalid = '1' and ready_reg(c_ready_latency) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
@@ -232,7 +233,8 @@ package body axi4_stream_pkg is
for i in 0 to sosi_arr'length - 1 loop
-- Check DP sink
if sosi_arr(i).tvalid = '1' and ready_reg(i * (c_ready_latency + 1) + 1) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg(i * (c_ready_latency + 1) + 1 to i * (c_ready_latency + 1) + c_ready_latency) <= ready_reg(i * (c_ready_latency + 1) to i * (c_ready_latency + 1) + c_ready_latency - 1);
end loop;
@@ -253,7 +255,9 @@ package body axi4_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_axi4_sosi;
begin
- assert nof_symbols_from_tail < vN report "func_axi4_data_shift_first : no symbols from head" severity FAILURE;
+ assert nof_symbols_from_tail < vN
+ report "func_axi4_data_shift_first : no symbols from head"
+ severity FAILURE;
-- use the other sosi from head_sosi
v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
for I in 1 to vN - 1 loop -- I > 0
@@ -303,8 +307,12 @@ package body axi4_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_axi4_sosi;
begin
- assert vK > 0 report "func_axi4_data_shift_last : no symbols from tail" severity FAILURE;
- assert vK + vL <= vN report "func_axi4_data_shift_last : impossible shift" severity FAILURE;
+ assert vK > 0
+ report "func_axi4_data_shift_last : no symbols from tail"
+ severity FAILURE;
+ assert vK + vL <= vN
+ report "func_axi4_data_shift_last : impossible shift"
+ severity FAILURE;
v_sosi := tail_sosi;
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
index d4cc4a03cc..f39566bf81 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
@@ -148,7 +148,8 @@ begin
for i in 0 to 10 loop
proc_mem_mm_bus_rd(I, mm_clk, mm_in_cipo, mm_in_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- assert TO_UINT(mm_in_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0)) = (c_offset + I) report
+ assert TO_UINT(mm_in_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0)) = (c_offset + I)
+ report
"Wrong value read from RAM at address " & int_to_str(I) & " expected " & int_to_str(c_offset + I)
& " but received " & int_to_str(TO_UINT(mm_in_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0))) severity ERROR;
end loop;
diff --git a/libraries/base/common/src/vhdl/common_counter.vhd b/libraries/base/common/src/vhdl/common_counter.vhd
index e5a449527e..2342e359b3 100644
--- a/libraries/base/common/src/vhdl/common_counter.vhd
+++ b/libraries/base/common/src/vhdl/common_counter.vhd
@@ -68,7 +68,9 @@ begin
count <= comb_count when g_latency = 0 else reg_count;
- assert g_step_size /= 0 report "common_counter: g_step_size must be /= 0" severity FAILURE;
+ assert g_step_size /= 0
+ report "common_counter: g_step_size must be /= 0"
+ severity FAILURE;
p_clk : process (rst, clk)
begin
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index 39fca484c1..539d11312e 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -150,7 +150,9 @@ package body common_math_pkg is
variable v_hi : std_logic_vector(W - 1 downto 0);
variable v_lo : std_logic_vector(W - 1 downto 0);
begin
- assert W <= 16 report "common_math_concat_look_up_table: width W*2 does not fit in 32 bit VHDL integer." severity FAILURE;
+ assert W <= 16
+ report "common_math_concat_look_up_table: width W*2 does not fit in 32 bit VHDL integer."
+ severity FAILURE;
for I in table_hi'range loop
v_hi := TO_SVEC(table_hi(I), W);
v_lo := TO_SVEC(table_lo(I), W);
diff --git a/libraries/base/common/src/vhdl/common_operation.vhd b/libraries/base/common/src/vhdl/common_operation.vhd
index d807bdcd3f..c42257b846 100644
--- a/libraries/base/common/src/vhdl/common_operation.vhd
+++ b/libraries/base/common/src/vhdl/common_operation.vhd
@@ -58,7 +58,9 @@ architecture rtl of common_operation is
if operation = "MIN" then return c_umax; end if;
if operation = "MAX" then return c_umin; end if;
end if;
- assert true report "Operation not supported" severity FAILURE;
+ assert true
+ report "Operation not supported"
+ severity FAILURE;
return c_umin; -- void return statement to avoid compiler warning on missing return
end;
@@ -71,7 +73,9 @@ architecture rtl of common_operation is
if operation = "MIN" then if unsigned(a) < unsigned(b) then return a; else return b; end if; end if;
if operation = "MAX" then if unsigned(a) > unsigned(b) then return a; else return b; end if; end if;
end if;
- assert true report "Operation not supported" severity FAILURE;
+ assert true
+ report "Operation not supported"
+ severity FAILURE;
return a; -- void return statement to avoid compiler warning on missing return
end;
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 647f701119..c072c8ea51 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -792,7 +792,9 @@ package body common_pkg is
constant c_complex_w : natural := 2 * w;
variable v_complex_slv : std_logic_vector(c_complex_w - 1 downto 0) := TO_SVEC(im, w) & TO_SVEC(re, w);
begin
- assert c_complex_w <= c_word_w report "common_pkg: Complex value to large to pack into 32 bit integer" severity FAILURE;
+ assert c_complex_w <= c_word_w
+ report "common_pkg: Complex value to large to pack into 32 bit integer"
+ severity FAILURE;
if c_complex_w < c_word_w then -- fits in 31 bit unsigned NATURAL
return TO_UINT(v_complex_slv);
else -- need to use 32 bit signed INTEGER
@@ -802,7 +804,9 @@ package body common_pkg is
function unpack_complex_re(data : std_logic_vector; w : natural) return integer is
begin
- assert w <= c_word_w report "common_pkg: Complex value to large to unpack into 32 bit integer parts" severity FAILURE;
+ assert w <= c_word_w
+ report "common_pkg: Complex value to large to unpack into 32 bit integer parts"
+ severity FAILURE;
return TO_SINT(data(w - 1 downto 0)); -- Re in LS part
end;
@@ -815,7 +819,9 @@ package body common_pkg is
function unpack_complex_im(data : std_logic_vector; w : natural) return integer is
begin
- assert w <= c_word_w report "common_pkg: Complex value to large to unpack into 32 bit integer parts" severity FAILURE;
+ assert w <= c_word_w
+ report "common_pkg: Complex value to large to unpack into 32 bit integer parts"
+ severity FAILURE;
return TO_SINT(data(2 * w - 1 downto w)); -- Im in MS part
end;
@@ -937,7 +943,9 @@ package body common_pkg is
elsif operation = "OR" then v_stage_arr := (others => (others => '0'));
elsif operation = "XOR" then v_stage_arr := (others => (others => '0'));
else
- assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
+ assert true
+ report "common_pkg: Unsupported vector_tree operation"
+ severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
@@ -2053,7 +2061,9 @@ package body common_pkg is
end if;
v_ureal := v_floor;
end loop;
- assert v_floor = 0.0 report "Unexpected TO_UVEC real remainder : " & real'image(v_floor) & " /= 0.0" severity FAILURE;
+ assert v_floor = 0.0
+ report "Unexpected TO_UVEC real remainder : " & real'image(v_floor) & " /= 0.0"
+ severity FAILURE;
return v_uvec;
else
report "Positive real clipped to UVEC max : " & real'image(v_ureal) & " -- > " & real'image(c_max) severity WARNING;
@@ -2950,18 +2960,21 @@ package body common_pkg is
--synthesis translate_off
if c_fail_rd_emp then
if rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1' then
- report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
+ report c_fifo_name & " : read from empty fifo occurred!"
+ severity FAILURE;
end if;
end if;
if c_note_is_ful then
if rising_edge(wr_full) and wr_rst = '0' then
- report c_fifo_name & " : fifo is full now" severity NOTE;
+ report c_fifo_name & " : fifo is full now"
+ severity NOTE;
end if;
end if;
if rising_edge(wr_clk) and wr_full = '1' and wr_en = '1' then
- report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+ report c_fifo_name & " : fifo overflow occurred!"
+ severity FAILURE;
end if;
--synthesis translate_on
end procedure proc_common_fifo_asserts;
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index e60f590d78..ccdbce316b 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -90,7 +90,9 @@ architecture str of common_requantize is
signal gain_dat : std_logic_vector(g_out_dat_w + c_gain_w - 1 downto 0) := (others => '0'); -- fill extra LSBits with '0' instead of extending MSbits
begin
- assert g_gain_w = 0 report "common_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w." severity FAILURE;
+ assert g_gain_w = 0
+ report "common_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w."
+ severity FAILURE;
-- Remove LSBits using ROUND or TRUNCATE
u_remove_lsb : entity common_lib.common_round
diff --git a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
index b415d43577..3e6df34f31 100644
--- a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
@@ -164,7 +164,9 @@ begin
begin
if rst = '0' then
if rising_edge(clk) then
- assert result_rtl = result_expected report "Error: wrong RTL result" severity ERROR;
+ assert result_rtl = result_expected
+ report "Error: wrong RTL result"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
index 1686b6f4e3..2104c2fb26 100644
--- a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
@@ -184,7 +184,9 @@ begin
begin
if rst = '0' then
if rising_edge(clk) then
- assert result_dut = result_expected report "Error: wrong result_dut" severity ERROR;
+ assert result_dut = result_expected
+ report "Error: wrong result_dut"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
index c42ebccaee..5b65718bd2 100644
--- a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
@@ -89,33 +89,53 @@ begin
if out_val = '1' then
-- Verify out_eop
if out_val_cnt mod g_nof_clk_per_block = g_nof_clk_per_block - 1 then
- assert out_eop = '1' report "Missing out_eop." severity ERROR;
+ assert out_eop = '1'
+ report "Missing out_eop."
+ severity ERROR;
else
- assert out_eop = '0' report "Unexpected out_eop." severity ERROR;
+ assert out_eop = '0'
+ report "Unexpected out_eop."
+ severity ERROR;
end if;
-- Verify out_sop
if out_val_cnt mod g_nof_clk_per_block = 0 then
- assert out_sop = '1' report "Missing out_sop." severity ERROR;
+ assert out_sop = '1'
+ report "Missing out_sop."
+ severity ERROR;
else
- assert out_sop = '0' report "Unexpected out_sop." severity ERROR;
+ assert out_sop = '0'
+ report "Unexpected out_sop."
+ severity ERROR;
end if;
-- Verify out_sync
if out_val_cnt mod g_nof_clk_per_block = 0 then
if out_val_cnt mod g_nof_clk_per_sync <= g_nof_clk_per_block - 1 then
- assert out_sync = '1' report "Missing out_sync." severity ERROR;
+ assert out_sync = '1'
+ report "Missing out_sync."
+ severity ERROR;
else
- assert out_sync = '0' report "Unexpected out_sync." severity ERROR;
+ assert out_sync = '0'
+ report "Unexpected out_sync."
+ severity ERROR;
end if;
else
- assert out_sync = '0' report "Unexpected out_sync." severity ERROR;
+ assert out_sync = '0'
+ report "Unexpected out_sync."
+ severity ERROR;
end if;
else
-- Illegal strobe when out_val = '0'
- assert out_eop = '0' report "Illegal out_eop." severity ERROR;
- assert out_sop = '0' report "Illegal out_sop." severity ERROR;
- assert out_sync = '0' report "Illegal out_sync." severity ERROR;
+ assert out_eop = '0'
+ report "Illegal out_eop."
+ severity ERROR;
+ assert out_sop = '0'
+ report "Illegal out_sop."
+ severity ERROR;
+ assert out_sync = '0'
+ report "Illegal out_sync."
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
index d5b732914c..85eb1d21ac 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
@@ -144,9 +144,15 @@ begin
begin
if rising_edge(clk) then
if verify_en = '1' then
- assert ref_en_vec(i) = ref_en_vec(0) report "Error: wrong fanout enable result" severity ERROR;
- assert ref_val_vec(i) = ref_val_vec(0) report "Error: wrong fanout valid result" severity ERROR;
- assert ref_dat_arr(i) = ref_dat_arr(0) report "Error: wrong fanout data result" severity ERROR;
+ assert ref_en_vec(i) = ref_en_vec(0)
+ report "Error: wrong fanout enable result"
+ severity ERROR;
+ assert ref_val_vec(i) = ref_val_vec(0)
+ report "Error: wrong fanout valid result"
+ severity ERROR;
+ assert ref_dat_arr(i) = ref_dat_arr(0)
+ report "Error: wrong fanout data result"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
index 2acc79d324..89771b0f72 100644
--- a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
@@ -34,14 +34,34 @@ end tb_common_gcd;
architecture tb of tb_common_gcd is
begin
- assert gcd( 0, 10) = 10 report "Wrong gcd( 0, 10)" severity ERROR;
- assert gcd( 1, 1) = 1 report "Wrong gcd( 1, 1)" severity ERROR;
- assert gcd(10, 1) = 1 report "Wrong gcd(10, 1)" severity ERROR;
- assert gcd(10, 3) = 1 report "Wrong gcd(10, 3)" severity ERROR;
- assert gcd(10, 4) = 2 report "Wrong gcd(10, 4)" severity ERROR;
- assert gcd(10, 5) = 5 report "Wrong gcd(10, 5)" severity ERROR;
- assert gcd(16, 4) = 4 report "Wrong gcd(16, 4)" severity ERROR;
- assert gcd(15, 5) = 5 report "Wrong gcd(15, 5)" severity ERROR;
- assert gcd(17, 17) = 17 report "Wrong gcd(17, 17)" severity ERROR;
- assert gcd(17, 4) = 1 report "Wrong gcd(17, 4)" severity ERROR;
+ assert gcd( 0, 10) = 10
+ report "Wrong gcd( 0, 10)"
+ severity ERROR;
+ assert gcd( 1, 1) = 1
+ report "Wrong gcd( 1, 1)"
+ severity ERROR;
+ assert gcd(10, 1) = 1
+ report "Wrong gcd(10, 1)"
+ severity ERROR;
+ assert gcd(10, 3) = 1
+ report "Wrong gcd(10, 3)"
+ severity ERROR;
+ assert gcd(10, 4) = 2
+ report "Wrong gcd(10, 4)"
+ severity ERROR;
+ assert gcd(10, 5) = 5
+ report "Wrong gcd(10, 5)"
+ severity ERROR;
+ assert gcd(16, 4) = 4
+ report "Wrong gcd(16, 4)"
+ severity ERROR;
+ assert gcd(15, 5) = 5
+ report "Wrong gcd(15, 5)"
+ severity ERROR;
+ assert gcd(17, 17) = 17
+ report "Wrong gcd(17, 17)"
+ severity ERROR;
+ assert gcd(17, 4) = 1
+ report "Wrong gcd(17, 4)"
+ severity ERROR;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
index 76794c62a8..428d9c6a39 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
@@ -79,7 +79,8 @@ begin
proc_common_wait_some_cycles(clk, 1);
temp := TO_UINT(miso.rddata(31 downto 0));
if(temp /= I + J) then
- report "Error! Readvalue is not as expected" severity ERROR;
+ report "Error! Readvalue is not as expected"
+ severity ERROR;
end if;
end loop;
end loop;
diff --git a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
index 255bb24dd4..874b669838 100644
--- a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
@@ -219,7 +219,9 @@ begin
begin
if rst = '0' then
if rising_edge(clk) then
- assert result = expected report "Error: wrong result" severity ERROR;
+ assert result = expected
+ report "Error: wrong result"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
index 57a6912714..46454cd408 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
@@ -221,10 +221,12 @@ begin
begin
if rising_edge(clk) then
if unsigned(mux_rd_dat) /= unsigned(adr_rd_dat) or unsigned(mux_rd_dat) /= unsigned(ofs_rd_dat) then
- report "DUT : read data differs between two implementations" severity ERROR;
+ report "DUT : read data differs between two implementations"
+ severity ERROR;
end if;
if mux_rd_val /= adr_rd_val or mux_rd_val /= ofs_rd_val then
- report "DUT : read valid differs between two implementations" severity ERROR;
+ report "DUT : read valid differs between two implementations"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
index ae4a886e08..4f7203b75c 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
@@ -228,10 +228,12 @@ begin
begin
if rising_edge(clk) then
if unsigned(mux_rd_dat_b) /= unsigned(adr_rd_dat_b) or unsigned(mux_rd_dat_b) /= unsigned(ofs_rd_dat_b) then
- report "DUT : read data differs between two implementations" severity ERROR;
+ report "DUT : read data differs between two implementations"
+ severity ERROR;
end if;
if mux_rd_val_b /= adr_rd_val_b or mux_rd_val_b /= ofs_rd_val_b then
- report "DUT : read valid differs between two implementations" severity ERROR;
+ report "DUT : read valid differs between two implementations"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
index 3527267b3d..261eabcc83 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
@@ -221,10 +221,12 @@ begin
begin
if rising_edge(clk) then
if unsigned(mux_rd_dat_b) /= unsigned(adr_rd_dat_b) or unsigned(mux_rd_dat_b) /= unsigned(ofs_rd_dat_b) then
- report "DUT : read data differs between two implementations" severity ERROR;
+ report "DUT : read data differs between two implementations"
+ severity ERROR;
end if;
if mux_rd_val_b /= adr_rd_val_b or mux_rd_val_b /= ofs_rd_val_b then
- report "DUT : read valid differs between two implementations" severity ERROR;
+ report "DUT : read valid differs between two implementations"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index 8f5c453e31..3c77197b67 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -412,7 +412,8 @@ package body tb_common_pkg is
wait until rising_edge(clk);
v_I := v_I + 1;
if v_I >= c_timeout - 1 then
- report "COMMON : level evt timeout" severity ERROR;
+ report "COMMON : level evt timeout"
+ severity ERROR;
exit;
end if;
end loop;
@@ -441,7 +442,8 @@ package body tb_common_pkg is
exit;
else
if I = c_timeout - 1 then
- report "COMMON : level high timeout" severity ERROR;
+ report "COMMON : level high timeout"
+ severity ERROR;
end if;
wait until rising_edge(clk);
end if;
@@ -471,7 +473,8 @@ package body tb_common_pkg is
exit;
else
if I = c_timeout - 1 then
- report "COMMON : level low timeout" severity ERROR;
+ report "COMMON : level low timeout"
+ severity ERROR;
end if;
wait until rising_edge(clk);
end if;
@@ -544,7 +547,8 @@ package body tb_common_pkg is
exit;
else
if I = c_timeout - 1 then
- report "COMMON : level value timeout" severity ERROR;
+ report "COMMON : level value timeout"
+ severity ERROR;
end if;
wait until rising_edge(clk);
end if;
@@ -563,8 +567,12 @@ package body tb_common_pkg is
signal tb_end : in std_logic) is
begin
while tb_end = '0' loop
- assert NOW < c_timeout report "Test bench timeout." severity ERROR;
- assert NOW < c_timeout report "Test bench timeout." severity FAILURE;
+ assert NOW < c_timeout
+ report "Test bench timeout."
+ severity ERROR;
+ assert NOW < c_timeout
+ report "Test bench timeout."
+ severity FAILURE;
wait for 1 us;
end loop;
end procedure;
@@ -576,7 +584,8 @@ package body tb_common_pkg is
-- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
-- stop the simulation using failure, without causing the test to fail.
wait for 1 ns;
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
wait;
end procedure;
@@ -599,9 +608,11 @@ package body tb_common_pkg is
-- stop the simulation using failure, without causing the test to fail.
wait for 1 ns;
if g_tb_end = false then
- report "Tb Simulation finished." severity NOTE;
+ report "Tb Simulation finished."
+ severity NOTE;
else
- report "Tb Simulation finished." severity FAILURE;
+ report "Tb Simulation finished."
+ severity FAILURE;
end if;
wait;
end procedure;
@@ -901,7 +912,8 @@ package body tb_common_pkg is
prev_out_data <= out_data;
v_exp_data := INCR_UVEC(prev_out_data, 1); -- increment first then compare to also support increment wrap around
if verify_en = '1' and unsigned(out_data) /= unsigned(v_exp_data) then
- report "COMMON : Wrong out_data count" severity ERROR;
+ report "COMMON : Wrong out_data count"
+ severity ERROR;
end if;
end if;
end if;
@@ -927,7 +939,8 @@ package body tb_common_pkg is
prev_ready <= ready;
if verify_en = '1' and out_valid = '1' then
if prev_ready /= '1' then
- report "COMMON : Wrong ready latency between ready and out_valid" severity ERROR;
+ report "COMMON : Wrong ready latency between ready and out_valid"
+ severity ERROR;
end if;
end if;
end if;
@@ -951,11 +964,13 @@ package body tb_common_pkg is
if verify_en = '1' then
if c_latency = 0 then
if in_ctrl /= out_ctrl then
- report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str severity ERROR;
+ report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str
+ severity ERROR;
end if;
else
if pipe_ctrl_vec(c_latency - 1) /= out_ctrl then
- report "COMMON : Wrong latency between input " & c_str & " and output " & c_str severity ERROR;
+ report "COMMON : Wrong latency between input " & c_str & " and output " & c_str
+ severity ERROR;
end if;
end if;
end if;
@@ -978,11 +993,13 @@ package body tb_common_pkg is
if verify_en = '1' then
if c_latency = 0 then
if unsigned(in_data) /= unsigned(out_data) then
- report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str severity ERROR;
+ report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str
+ severity ERROR;
end if;
else
if unsigned(pipe_data_vec(c_data_vec_w - c_data_w - c_data_w to c_data_vec_w - c_data_w - 1)) /= unsigned(out_data) then
- report "COMMON : Wrong latency between input " & c_str & " and output " & c_str severity ERROR;
+ report "COMMON : Wrong latency between input " & c_str & " and output " & c_str
+ severity ERROR;
end if;
end if;
end if;
@@ -1002,10 +1019,12 @@ package body tb_common_pkg is
if rising_edge(clk) then
if en = '1' then
if mode = 0 and unsigned(res) /= unsigned(exp) then
- report "COMMON : Wrong result value" severity ERROR; -- == (equal)
+ report "COMMON : Wrong result value"
+ severity ERROR; -- == (equal)
end if;
if mode = 1 and unsigned(res) < unsigned(exp) then
- report "COMMON : Wrong result value too small" severity ERROR; -- >= (at least)
+ report "COMMON : Wrong result value too small"
+ severity ERROR; -- >= (at least)
end if;
end if;
end if;
@@ -1024,9 +1043,11 @@ package body tb_common_pkg is
end if;
file_open (file_status, in_file, file_name, file_mode);
if file_status = OPEN_OK then
- report "COMMON : file opened " severity NOTE;
+ report "COMMON : file opened "
+ severity NOTE;
else
- report "COMMON : Unable to open file " severity FAILURE;
+ report "COMMON : Unable to open file "
+ severity FAILURE;
end if;
end proc_common_open_file;
@@ -1040,15 +1061,18 @@ package body tb_common_pkg is
variable v_good : boolean;
begin
if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
+ report "COMMON : file is not opened "
+ severity FAILURE;
else
if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ report "COMMON : end of file "
+ severity NOTE;
else
READLINE(in_file, v_line);
READ(v_line, read_value_0, v_good);
if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
+ report "COMMON : Read from line unsuccessful "
+ severity FAILURE;
end if;
end if;
end if;
@@ -1065,19 +1089,23 @@ package body tb_common_pkg is
variable v_good : boolean;
begin
if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
+ report "COMMON : file is not opened "
+ severity FAILURE;
else
if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ report "COMMON : end of file "
+ severity NOTE;
else
READLINE(in_file, v_line);
READ(v_line, read_value_0, v_good);
if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
+ report "COMMON : Read from line unsuccessful "
+ severity FAILURE;
end if;
READ(v_line, read_value_1, v_good);
if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
+ report "COMMON : Read from line unsuccessful "
+ severity FAILURE;
end if;
end if;
end if;
@@ -1094,16 +1122,19 @@ package body tb_common_pkg is
variable v_good : boolean;
begin
if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
+ report "COMMON : file is not opened "
+ severity FAILURE;
else
if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ report "COMMON : end of file "
+ severity NOTE;
else
READLINE(in_file, v_line);
for I in 0 to nof_reads - 1 loop
READ(v_line, value_array(I), v_good);
if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
+ report "COMMON : Read from line unsuccessful "
+ severity FAILURE;
end if;
end loop;
end if;
@@ -1120,15 +1151,18 @@ package body tb_common_pkg is
variable v_good : boolean;
begin
if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
+ report "COMMON : file is not opened "
+ severity FAILURE;
else
if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ report "COMMON : end of file "
+ severity NOTE;
else
READLINE(in_file, v_line);
READ(v_line, read_slv, v_good);
if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
+ report "COMMON : Read from line unsuccessful "
+ severity FAILURE;
end if;
end if;
end if;
@@ -1145,10 +1179,12 @@ package body tb_common_pkg is
variable is_string : boolean;
begin
if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
+ report "COMMON : file is not opened "
+ severity FAILURE;
else
if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ report "COMMON : end of file "
+ severity NOTE;
else
readline(in_file, v_line);
-- clear the contents of the result string
@@ -1175,10 +1211,12 @@ package body tb_common_pkg is
file in_file : TEXT) is
begin
if file_status /= OPEN_OK then
- report "COMMON : file was not opened " severity WARNING;
+ report "COMMON : file was not opened "
+ severity WARNING;
end if;
FILE_CLOSE(in_file);
- report "COMMON : file closed " severity NOTE;
+ report "COMMON : file closed "
+ severity NOTE;
end proc_common_close_file;
------------------------------------------------------------------------------
@@ -1211,7 +1249,8 @@ package body tb_common_pkg is
end loop;
if ENDFILE(v_in_file) then
if J /= nof_row - 1 then
- report "COMMON : Unexpected end of file" severity FAILURE;
+ report "COMMON : Unexpected end of file"
+ severity FAILURE;
end if;
exit;
end if;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
index 5a9bddedde..0bebbe7234 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
@@ -134,11 +134,13 @@ begin
begin
-- input/output pulse delay should match setting
if pulse_out = '1' and pulse_delay_count /= TO_UINT(pulse_delay_reg) then
- report "I/O pulse delay does not match delay setting!" severity FAILURE;
+ report "I/O pulse delay does not match delay setting!"
+ severity FAILURE;
end if;
-- Total number of pulses should be the maximum allowed by common_pulse_delay's interal counter width
if tb_end = '1' and pulse_count /= c_nof_pulses then
- report "Incorrect total number of pulses!" severity FAILURE;
+ report "Incorrect total number of pulses!"
+ severity FAILURE;
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
index 14f400a91f..fbec2c0111 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
@@ -154,7 +154,8 @@ begin
if rising_edge(clk) then
if data_out_val = '1' then
if TO_UINT(data_in) /= TO_UINT(data_out) + c_data_io_delay + TO_UINT(data_out_shift) then
- report "Wrong output data/shift with respect to input data" severity ERROR;
+ report "Wrong output data/shift with respect to input data"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index 30de6415c8..442f05ec9d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -108,11 +108,19 @@ begin
end if;
wait until rising_edge(clk);
-- Verify
- assert a_sint = I report "Wrong real to integer conversion for I = " & integer'image(I) severity ERROR;
- assert a_slv = v_slv report "Wrong real to SLV conversion for I = " & integer'image(I) severity ERROR;
+ assert a_sint = I
+ report "Wrong real to integer conversion for I = " & integer'image(I)
+ severity ERROR;
+ assert a_slv = v_slv
+ report "Wrong real to SLV conversion for I = " & integer'image(I)
+ severity ERROR;
if I >= 0 then
- assert a_uint = I report "Wrong real to natural conversion for I = " & natural'image(I) severity ERROR;
- assert a_ulv = v_slv report "Wrong real to unsigned SLV conversion for I = " & natural'image(I) severity ERROR;
+ assert a_uint = I
+ report "Wrong real to natural conversion for I = " & natural'image(I)
+ severity ERROR;
+ assert a_ulv = v_slv
+ report "Wrong real to unsigned SLV conversion for I = " & natural'image(I)
+ severity ERROR;
end if;
end loop;
proc_wait_some_cycles(clk, 10);
@@ -148,8 +156,12 @@ begin
-- . Negative clip to 0 for unsigned
v_real := -3.0; a_real <= v_real; a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
- assert a_uint = 0 report "Unexpected TO_UINT(< 0) : " & integer'image(a_uint) & " /= 0" severity ERROR;
- assert TO_UINT(a_ulv) = 0 report "Unexpected TO_UVEC(< 0) : " & integer'image(TO_UINT(a_ulv)) & " /= 0" severity ERROR;
+ assert a_uint = 0
+ report "Unexpected TO_UINT(< 0) : " & integer'image(a_uint) & " /= 0"
+ severity ERROR;
+ assert TO_UINT(a_ulv) = 0
+ report "Unexpected TO_UVEC(< 0) : " & integer'image(TO_UINT(a_ulv)) & " /= 0"
+ severity ERROR;
proc_wait_some_cycles(clk, 5);
-- . Large overflow with 4 bit integers for << -16.5 : >> +15.5
@@ -178,10 +190,12 @@ begin
end process;
-- TO_SINT() and TO_SVEC() must always yield same result
- assert a_sint = TO_SINT(a_slv) report "Unexpected difference between TO_SINT() and TO_SVEC() :" &
+ assert a_sint = TO_SINT(a_slv)
+ report "Unexpected difference between TO_SINT() and TO_SVEC() :" &
integer'image(a_sint) & " /= " & integer'image(TO_SINT(a_slv)) severity ERROR;
-- TO_UINT() and TO_UVEC() must always yield same result
- assert a_uint = TO_UINT(a_ulv) report "Unexpected difference between TO_UINT() and TO_UVEC() :" &
+ assert a_uint = TO_UINT(a_ulv)
+ report "Unexpected difference between TO_UINT() and TO_UVEC() :" &
integer'image(a_uint) & " /= " & integer'image(TO_SINT(a_ulv)) severity ERROR;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index e83313ab6c..28da8fcf13 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -88,13 +88,17 @@ begin
proc_common_wait_some_cycles(clk, 1);
end loop;
-- Verify that expected delay was applied
- assert clk_cnt = c_trigger_latency + delay report "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency + delay) severity ERROR;
+ assert clk_cnt = c_trigger_latency + delay
+ report "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency + delay)
+ severity ERROR;
proc_common_wait_some_cycles(clk, 10);
end loop;
enable <= '0';
proc_common_wait_some_cycles(clk, c_trigger_interval * 3);
- assert triggers_cnt = exp_triggers_cnt report "wrong number of trigger_dly." severity ERROR;
+ assert triggers_cnt = exp_triggers_cnt
+ report "wrong number of trigger_dly."
+ severity ERROR;
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index 93022fd6a2..20111c3db6 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -73,7 +73,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
enable <= TO_UINT(mm_miso.rddata(1 downto 0));
proc_common_wait_some_cycles(clk, 1);
- assert enable = 1 report "enable not on" severity ERROR;
+ assert enable = 1
+ report "enable not on"
+ severity ERROR;
proc_mem_mm_bus_wr(c_mm_addr_enable, 0, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
@@ -81,7 +83,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
enable <= TO_UINT(mm_miso.rddata(0 downto 0));
proc_common_wait_some_cycles(clk, 1);
- assert enable = 0 report "enable not off" severity ERROR;
+ assert enable = 0
+ report "enable not off"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
diff --git a/libraries/base/common/tb/vhdl/tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_resize.vhd
index 83d3dbac30..3a4842719a 100644
--- a/libraries/base/common/tb/vhdl/tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_resize.vhd
@@ -200,18 +200,38 @@ begin
if reg_val = '1' then
if g_in_dat_w <= g_out_dat_w then
-- For extended width expected value is same as input value
- assert signed( lowrange_sdat) = signed(reg_dat) report "Wrong extended lowrange_sdat" severity ERROR;
- assert unsigned( lowrange_udat) = unsigned(reg_dat) report "Wrong extended lowrange_udat" severity ERROR;
- assert signed( resize_sdat) = signed(reg_dat) report "Wrong extended resize_sdat" severity ERROR;
- assert unsigned( resize_udat) = unsigned(reg_dat) report "Wrong extended resize_udat" severity ERROR;
- assert signed(resize_num_sdat) = signed(reg_dat) report "Wrong extended resize_num_sdat" severity ERROR;
- assert unsigned(resize_num_udat) = unsigned(reg_dat) report "Wrong extended resize_num_udat" severity ERROR;
- assert signed( out_sdat) = signed(reg_dat) report "Wrong extended out_sdat" severity ERROR;
- assert unsigned( out_udat) = unsigned(reg_dat) report "Wrong extended out_udat" severity ERROR;
+ assert signed( lowrange_sdat) = signed(reg_dat)
+ report "Wrong extended lowrange_sdat"
+ severity ERROR;
+ assert unsigned( lowrange_udat) = unsigned(reg_dat)
+ report "Wrong extended lowrange_udat"
+ severity ERROR;
+ assert signed( resize_sdat) = signed(reg_dat)
+ report "Wrong extended resize_sdat"
+ severity ERROR;
+ assert unsigned( resize_udat) = unsigned(reg_dat)
+ report "Wrong extended resize_udat"
+ severity ERROR;
+ assert signed(resize_num_sdat) = signed(reg_dat)
+ report "Wrong extended resize_num_sdat"
+ severity ERROR;
+ assert unsigned(resize_num_udat) = unsigned(reg_dat)
+ report "Wrong extended resize_num_udat"
+ severity ERROR;
+ assert signed( out_sdat) = signed(reg_dat)
+ report "Wrong extended out_sdat"
+ severity ERROR;
+ assert unsigned( out_udat) = unsigned(reg_dat)
+ report "Wrong extended out_udat"
+ severity ERROR;
else
-- For reduced width compare unsigned with lowrange
- assert unsigned( resize_udat) = unsigned(lowrange_udat) report "Wrong wrapped resize_udat" severity ERROR;
- assert unsigned(resize_num_udat) = unsigned(lowrange_udat) report "Wrong wrapped resize_num_udat" severity ERROR;
+ assert unsigned( resize_udat) = unsigned(lowrange_udat)
+ report "Wrong wrapped resize_udat"
+ severity ERROR;
+ assert unsigned(resize_num_udat) = unsigned(lowrange_udat)
+ report "Wrong wrapped resize_num_udat"
+ severity ERROR;
assert unsigned( out_udat) = unsigned(lowrange_udat) or
unsigned( out_udat) = g_clip_umax report "Wrong clipped out_udat" severity ERROR;
@@ -222,20 +242,27 @@ begin
if g_clip then
if g_clip_symmetric then
assert (signed(out_sdat) = signed(lowrange_sdat) or signed(out_sdat) = -g_clip_smax or signed(out_sdat) = g_clip_smax) and
- signed(out_sdat) /= g_clip_smin and
+ signed(out_sdat) /= g_clip_smin and
signed(out_sdat) /= -g_clip_smin report "Wrong clipped symmetrical out_sdat" severity ERROR;
else
assert (signed(out_sdat) = signed(lowrange_sdat) or signed(out_sdat) = g_clip_smin or signed(out_sdat) = g_clip_smax)
- report "Wrong clipped out_sdat" severity ERROR;
+ report "Wrong clipped out_sdat"
+ severity ERROR;
end if;
else
- assert signed(out_sdat) = signed(lowrange_sdat) report "Wrong wrapped out_sdat" severity ERROR;
+ assert signed(out_sdat) = signed(lowrange_sdat)
+ report "Wrong wrapped out_sdat"
+ severity ERROR;
end if;
end if;
-- RESIZE_NUM() in common_pkg.vhd is always equivalent to lowrange
- assert signed(resize_num_sdat) = signed(lowrange_sdat) report "Wrong resize_num_sdat /= lowrange_sdat" severity ERROR;
- assert unsigned(resize_num_udat) = unsigned(lowrange_udat) report "Wrong resize_num_udat /= lowrange_udat" severity ERROR;
+ assert signed(resize_num_sdat) = signed(lowrange_sdat)
+ report "Wrong resize_num_sdat /= lowrange_sdat"
+ severity ERROR;
+ assert unsigned(resize_num_udat) = unsigned(lowrange_udat)
+ report "Wrong resize_num_udat /= lowrange_udat"
+ severity ERROR;
end if;
end process;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_round.vhd b/libraries/base/common/tb/vhdl/tb_round.vhd
index 59813adae6..3910e10583 100644
--- a/libraries/base/common/tb/vhdl/tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_round.vhd
@@ -538,88 +538,208 @@ begin
if c_round_w <= 0 then
-- Without rounding the expected value is same as input value
-- . signed
- assert signed(fs_signed_truncate ) = signed(reg_dat) report "Wrong wired fs_signed_truncate" severity ERROR;
- assert signed(fs_signed_round_half_away ) = signed(reg_dat) report "Wrong wired fs_signed_round_half_away" severity ERROR;
- assert signed(fs_signed_round_half_away_clip) = signed(reg_dat) report "Wrong wired fs_signed_round_half_away_clip" severity ERROR;
- assert signed(fs_signed_round_half_even ) = signed(reg_dat) report "Wrong wired fs_signed_round_half_even" severity ERROR;
- assert signed(fs_signed_round_half_even_clip) = signed(reg_dat) report "Wrong wired fs_signed_round_half_even_clip" severity ERROR;
+ assert signed(fs_signed_truncate ) = signed(reg_dat)
+ report "Wrong wired fs_signed_truncate"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away ) = signed(reg_dat)
+ report "Wrong wired fs_signed_round_half_away"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away_clip) = signed(reg_dat)
+ report "Wrong wired fs_signed_round_half_away_clip"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even ) = signed(reg_dat)
+ report "Wrong wired fs_signed_round_half_even"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even_clip) = signed(reg_dat)
+ report "Wrong wired fs_signed_round_half_even_clip"
+ severity ERROR;
-- . unsigned
- assert unsigned(fs_unsigned_truncate ) = unsigned(reg_dat) report "Wrong wired fs_unsigned_truncate" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up ) = unsigned(reg_dat) report "Wrong wired fs_unsigned_round_half_up" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up_clip ) = unsigned(reg_dat) report "Wrong wired fs_unsigned_round_half_up_clip" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even ) = unsigned(reg_dat) report "Wrong wired fs_unsigned_round_half_even" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even_clip) = unsigned(reg_dat) report "Wrong wired fs_unsigned_round_half_even_clip" severity ERROR;
+ assert unsigned(fs_unsigned_truncate ) = unsigned(reg_dat)
+ report "Wrong wired fs_unsigned_truncate"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up ) = unsigned(reg_dat)
+ report "Wrong wired fs_unsigned_round_half_up"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up_clip ) = unsigned(reg_dat)
+ report "Wrong wired fs_unsigned_round_half_up_clip"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even ) = unsigned(reg_dat)
+ report "Wrong wired fs_unsigned_round_half_even"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even_clip) = unsigned(reg_dat)
+ report "Wrong wired fs_unsigned_round_half_even_clip"
+ severity ERROR;
else
-- With rounding then compare with expected list of values from common_round_tb.py
if g_in_dat_w = 4 and c_round_w = 1 then
-- . signed
- assert signed(fs_signed_truncate ) = exp_w4_r1_signed_truncate report "Wrong exp_w4_r1_signed_truncate" severity ERROR;
- assert signed(fs_signed_round_half_away ) = exp_w4_r1_signed_round_half_away report "Wrong exp_w4_r1_signed_round_half_away" severity ERROR;
- assert signed(fs_signed_round_half_away_clip) = exp_w4_r1_signed_round_half_away_clip report "Wrong exp_w4_r1_signed_round_half_away_clip" severity ERROR;
- assert signed(fs_signed_round_half_even ) = exp_w4_r1_signed_round_half_even report "Wrong exp_w4_r1_signed_round_half_even" severity ERROR;
- assert signed(fs_signed_round_half_even_clip) = exp_w4_r1_signed_round_half_even_clip report "Wrong exp_w4_r1_signed_round_half_even_clip" severity ERROR;
+ assert signed(fs_signed_truncate ) = exp_w4_r1_signed_truncate
+ report "Wrong exp_w4_r1_signed_truncate"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away ) = exp_w4_r1_signed_round_half_away
+ report "Wrong exp_w4_r1_signed_round_half_away"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away_clip) = exp_w4_r1_signed_round_half_away_clip
+ report "Wrong exp_w4_r1_signed_round_half_away_clip"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even ) = exp_w4_r1_signed_round_half_even
+ report "Wrong exp_w4_r1_signed_round_half_even"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even_clip) = exp_w4_r1_signed_round_half_even_clip
+ report "Wrong exp_w4_r1_signed_round_half_even_clip"
+ severity ERROR;
-- . unsigned
- assert unsigned(fs_unsigned_truncate ) = exp_w4_r1_unsigned_truncate report "Wrong exp_w4_r1_unsigned_truncate" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up ) = exp_w4_r1_unsigned_round_half_up report "Wrong exp_w4_r1_unsigned_round_half_up" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w4_r1_unsigned_round_half_up_clip report "Wrong exp_w4_r1_unsigned_round_half_up_clip" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even ) = exp_w4_r1_unsigned_round_half_even report "Wrong exp_w4_r1_unsigned_round_half_even" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even_clip) = exp_w4_r1_unsigned_round_half_even_clip report "Wrong exp_w4_r1_unsigned_round_half_even_clip" severity ERROR;
+ assert unsigned(fs_unsigned_truncate ) = exp_w4_r1_unsigned_truncate
+ report "Wrong exp_w4_r1_unsigned_truncate"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up ) = exp_w4_r1_unsigned_round_half_up
+ report "Wrong exp_w4_r1_unsigned_round_half_up"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w4_r1_unsigned_round_half_up_clip
+ report "Wrong exp_w4_r1_unsigned_round_half_up_clip"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even ) = exp_w4_r1_unsigned_round_half_even
+ report "Wrong exp_w4_r1_unsigned_round_half_even"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even_clip) = exp_w4_r1_unsigned_round_half_even_clip
+ report "Wrong exp_w4_r1_unsigned_round_half_even_clip"
+ severity ERROR;
end if;
if g_in_dat_w = 4 and c_round_w = 2 then
-- . signed
- assert signed(fs_signed_truncate ) = exp_w4_r2_signed_truncate report "Wrong exp_w4_r2_signed_truncate" severity ERROR;
- assert signed(fs_signed_round_half_away ) = exp_w4_r2_signed_round_half_away report "Wrong exp_w4_r2_signed_round_half_away" severity ERROR;
- assert signed(fs_signed_round_half_away_clip) = exp_w4_r2_signed_round_half_away_clip report "Wrong exp_w4_r2_signed_round_half_away_clip" severity ERROR;
- assert signed(fs_signed_round_half_even ) = exp_w4_r2_signed_round_half_even report "Wrong exp_w4_r2_signed_round_half_even" severity ERROR;
- assert signed(fs_signed_round_half_even_clip) = exp_w4_r2_signed_round_half_even_clip report "Wrong exp_w4_r2_signed_round_half_even_clip" severity ERROR;
+ assert signed(fs_signed_truncate ) = exp_w4_r2_signed_truncate
+ report "Wrong exp_w4_r2_signed_truncate"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away ) = exp_w4_r2_signed_round_half_away
+ report "Wrong exp_w4_r2_signed_round_half_away"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away_clip) = exp_w4_r2_signed_round_half_away_clip
+ report "Wrong exp_w4_r2_signed_round_half_away_clip"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even ) = exp_w4_r2_signed_round_half_even
+ report "Wrong exp_w4_r2_signed_round_half_even"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even_clip) = exp_w4_r2_signed_round_half_even_clip
+ report "Wrong exp_w4_r2_signed_round_half_even_clip"
+ severity ERROR;
-- . unsigned
- assert unsigned(fs_unsigned_truncate ) = exp_w4_r2_unsigned_truncate report "Wrong exp_w4_r2_unsigned_truncate" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up ) = exp_w4_r2_unsigned_round_half_up report "Wrong exp_w4_r2_unsigned_round_half_up" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w4_r2_unsigned_round_half_up_clip report "Wrong exp_w4_r2_unsigned_round_half_up_clip" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even ) = exp_w4_r2_unsigned_round_half_even report "Wrong exp_w4_r2_unsigned_round_half_even" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even_clip) = exp_w4_r2_unsigned_round_half_even_clip report "Wrong exp_w4_r2_unsigned_round_half_even_clip" severity ERROR;
+ assert unsigned(fs_unsigned_truncate ) = exp_w4_r2_unsigned_truncate
+ report "Wrong exp_w4_r2_unsigned_truncate"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up ) = exp_w4_r2_unsigned_round_half_up
+ report "Wrong exp_w4_r2_unsigned_round_half_up"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w4_r2_unsigned_round_half_up_clip
+ report "Wrong exp_w4_r2_unsigned_round_half_up_clip"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even ) = exp_w4_r2_unsigned_round_half_even
+ report "Wrong exp_w4_r2_unsigned_round_half_even"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even_clip) = exp_w4_r2_unsigned_round_half_even_clip
+ report "Wrong exp_w4_r2_unsigned_round_half_even_clip"
+ severity ERROR;
end if;
if g_in_dat_w = 4 and c_round_w = 3 then
-- . signed
- assert signed(fs_signed_truncate ) = exp_w4_r3_signed_truncate report "Wrong exp_w4_r3_signed_truncate" severity ERROR;
- assert signed(fs_signed_round_half_away ) = exp_w4_r3_signed_round_half_away report "Wrong exp_w4_r3_signed_round_half_away" severity ERROR;
- assert signed(fs_signed_round_half_away_clip) = exp_w4_r3_signed_round_half_away_clip report "Wrong exp_w4_r3_signed_round_half_away_clip" severity ERROR;
- assert signed(fs_signed_round_half_even ) = exp_w4_r3_signed_round_half_even report "Wrong exp_w4_r3_signed_round_half_even" severity ERROR;
- assert signed(fs_signed_round_half_even_clip) = exp_w4_r3_signed_round_half_even_clip report "Wrong exp_w4_r3_signed_round_half_even_clip" severity ERROR;
+ assert signed(fs_signed_truncate ) = exp_w4_r3_signed_truncate
+ report "Wrong exp_w4_r3_signed_truncate"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away ) = exp_w4_r3_signed_round_half_away
+ report "Wrong exp_w4_r3_signed_round_half_away"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away_clip) = exp_w4_r3_signed_round_half_away_clip
+ report "Wrong exp_w4_r3_signed_round_half_away_clip"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even ) = exp_w4_r3_signed_round_half_even
+ report "Wrong exp_w4_r3_signed_round_half_even"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even_clip) = exp_w4_r3_signed_round_half_even_clip
+ report "Wrong exp_w4_r3_signed_round_half_even_clip"
+ severity ERROR;
-- . unsigned
- assert unsigned(fs_unsigned_truncate ) = exp_w4_r3_unsigned_truncate report "Wrong exp_w4_r3_unsigned_truncate" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up ) = exp_w4_r3_unsigned_round_half_up report "Wrong exp_w4_r3_unsigned_round_half_up" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w4_r3_unsigned_round_half_up_clip report "Wrong exp_w4_r3_unsigned_round_half_up_clip" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even ) = exp_w4_r3_unsigned_round_half_even report "Wrong exp_w4_r3_unsigned_round_half_even" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even_clip) = exp_w4_r3_unsigned_round_half_even_clip report "Wrong exp_w4_r3_unsigned_round_half_even_clip" severity ERROR;
+ assert unsigned(fs_unsigned_truncate ) = exp_w4_r3_unsigned_truncate
+ report "Wrong exp_w4_r3_unsigned_truncate"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up ) = exp_w4_r3_unsigned_round_half_up
+ report "Wrong exp_w4_r3_unsigned_round_half_up"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w4_r3_unsigned_round_half_up_clip
+ report "Wrong exp_w4_r3_unsigned_round_half_up_clip"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even ) = exp_w4_r3_unsigned_round_half_even
+ report "Wrong exp_w4_r3_unsigned_round_half_even"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even_clip) = exp_w4_r3_unsigned_round_half_even_clip
+ report "Wrong exp_w4_r3_unsigned_round_half_even_clip"
+ severity ERROR;
end if;
if g_in_dat_w = 5 and c_round_w = 2 then
-- . signed
- assert signed(fs_signed_truncate ) = exp_w5_r2_signed_truncate report "Wrong exp_w5_r2_signed_truncate" severity ERROR;
- assert signed(fs_signed_round_half_away ) = exp_w5_r2_signed_round_half_away report "Wrong exp_w5_r2_signed_round_half_away" severity ERROR;
- assert signed(fs_signed_round_half_away_clip) = exp_w5_r2_signed_round_half_away_clip report "Wrong exp_w5_r2_signed_round_half_away_clip" severity ERROR;
- assert signed(fs_signed_round_half_even ) = exp_w5_r2_signed_round_half_even report "Wrong exp_w5_r2_signed_round_half_even" severity ERROR;
- assert signed(fs_signed_round_half_even_clip) = exp_w5_r2_signed_round_half_even_clip report "Wrong exp_w5_r2_signed_round_half_even_clip" severity ERROR;
+ assert signed(fs_signed_truncate ) = exp_w5_r2_signed_truncate
+ report "Wrong exp_w5_r2_signed_truncate"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away ) = exp_w5_r2_signed_round_half_away
+ report "Wrong exp_w5_r2_signed_round_half_away"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away_clip) = exp_w5_r2_signed_round_half_away_clip
+ report "Wrong exp_w5_r2_signed_round_half_away_clip"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even ) = exp_w5_r2_signed_round_half_even
+ report "Wrong exp_w5_r2_signed_round_half_even"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even_clip) = exp_w5_r2_signed_round_half_even_clip
+ report "Wrong exp_w5_r2_signed_round_half_even_clip"
+ severity ERROR;
-- . unsigned
- assert unsigned(fs_unsigned_truncate ) = exp_w5_r2_unsigned_truncate report "Wrong exp_w5_r2_unsigned_truncate" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up ) = exp_w5_r2_unsigned_round_half_up report "Wrong exp_w5_r2_unsigned_round_half_up" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w5_r2_unsigned_round_half_up_clip report "Wrong exp_w5_r2_unsigned_round_half_up_clip" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even ) = exp_w5_r2_unsigned_round_half_even report "Wrong exp_w5_r2_unsigned_round_half_even" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even_clip) = exp_w5_r2_unsigned_round_half_even_clip report "Wrong exp_w5_r2_unsigned_round_half_even_clip" severity ERROR;
+ assert unsigned(fs_unsigned_truncate ) = exp_w5_r2_unsigned_truncate
+ report "Wrong exp_w5_r2_unsigned_truncate"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up ) = exp_w5_r2_unsigned_round_half_up
+ report "Wrong exp_w5_r2_unsigned_round_half_up"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w5_r2_unsigned_round_half_up_clip
+ report "Wrong exp_w5_r2_unsigned_round_half_up_clip"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even ) = exp_w5_r2_unsigned_round_half_even
+ report "Wrong exp_w5_r2_unsigned_round_half_even"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even_clip) = exp_w5_r2_unsigned_round_half_even_clip
+ report "Wrong exp_w5_r2_unsigned_round_half_even_clip"
+ severity ERROR;
end if;
if g_in_dat_w = 5 and c_round_w = 3 then
-- . signed
- assert signed(fs_signed_truncate ) = exp_w5_r3_signed_truncate report "Wrong exp_w5_r3_signed_truncate" severity ERROR;
- assert signed(fs_signed_round_half_away ) = exp_w5_r3_signed_round_half_away report "Wrong exp_w5_r3_signed_round_half_away" severity ERROR;
- assert signed(fs_signed_round_half_away_clip) = exp_w5_r3_signed_round_half_away_clip report "Wrong exp_w5_r3_signed_round_half_away_clip" severity ERROR;
- assert signed(fs_signed_round_half_even ) = exp_w5_r3_signed_round_half_even report "Wrong exp_w5_r3_signed_round_half_even" severity ERROR;
- assert signed(fs_signed_round_half_even_clip) = exp_w5_r3_signed_round_half_even_clip report "Wrong exp_w5_r3_signed_round_half_even_clip" severity ERROR;
+ assert signed(fs_signed_truncate ) = exp_w5_r3_signed_truncate
+ report "Wrong exp_w5_r3_signed_truncate"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away ) = exp_w5_r3_signed_round_half_away
+ report "Wrong exp_w5_r3_signed_round_half_away"
+ severity ERROR;
+ assert signed(fs_signed_round_half_away_clip) = exp_w5_r3_signed_round_half_away_clip
+ report "Wrong exp_w5_r3_signed_round_half_away_clip"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even ) = exp_w5_r3_signed_round_half_even
+ report "Wrong exp_w5_r3_signed_round_half_even"
+ severity ERROR;
+ assert signed(fs_signed_round_half_even_clip) = exp_w5_r3_signed_round_half_even_clip
+ report "Wrong exp_w5_r3_signed_round_half_even_clip"
+ severity ERROR;
-- . unsigned
- assert unsigned(fs_unsigned_truncate ) = exp_w5_r3_unsigned_truncate report "Wrong exp_w5_r3_unsigned_truncate" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up ) = exp_w5_r3_unsigned_round_half_up report "Wrong exp_w5_r3_unsigned_round_half_up" severity ERROR;
- assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w5_r3_unsigned_round_half_up_clip report "Wrong exp_w5_r3_unsigned_round_half_up_clip" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even ) = exp_w5_r3_unsigned_round_half_even report "Wrong exp_w5_r3_unsigned_round_half_even" severity ERROR;
- assert unsigned(fs_unsigned_round_half_even_clip) = exp_w5_r3_unsigned_round_half_even_clip report "Wrong exp_w5_r3_unsigned_round_half_even_clip" severity ERROR;
+ assert unsigned(fs_unsigned_truncate ) = exp_w5_r3_unsigned_truncate
+ report "Wrong exp_w5_r3_unsigned_truncate"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up ) = exp_w5_r3_unsigned_round_half_up
+ report "Wrong exp_w5_r3_unsigned_round_half_up"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_up_clip ) = exp_w5_r3_unsigned_round_half_up_clip
+ report "Wrong exp_w5_r3_unsigned_round_half_up_clip"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even ) = exp_w5_r3_unsigned_round_half_even
+ report "Wrong exp_w5_r3_unsigned_round_half_even"
+ severity ERROR;
+ assert unsigned(fs_unsigned_round_half_even_clip) = exp_w5_r3_unsigned_round_half_even_clip
+ report "Wrong exp_w5_r3_unsigned_round_half_even_clip"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index bd0dec1fcb..38b3cc8d60 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -292,9 +292,15 @@ begin
begin
if rst = '0' then
if rising_edge(clk) then
- assert result_re_dut = result_re_expected report "Error: RE wrong result, " & slv_to_str(result_re_dut) & " /= " & slv_to_str(result_re_expected) severity ERROR;
- assert result_im_dut = result_im_expected report "Error: IM wrong result, " & slv_to_str(result_im_dut) & " /= " & slv_to_str(result_im_expected) severity ERROR;
- assert result_val_dut = result_val_expected report "Error: VAL wrong result" severity ERROR;
+ assert result_re_dut = result_re_expected
+ report "Error: RE wrong result, " & slv_to_str(result_re_dut) & " /= " & slv_to_str(result_re_expected)
+ severity ERROR;
+ assert result_im_dut = result_im_expected
+ report "Error: IM wrong result, " & slv_to_str(result_im_dut) & " /= " & slv_to_str(result_im_expected)
+ severity ERROR;
+ assert result_val_dut = result_val_expected
+ report "Error: VAL wrong result"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
index 811b71ec89..5bc2f5c8d3 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
@@ -335,10 +335,18 @@ begin
if rst = '0' then
if rising_edge(clk) then
-- verify all multipliers in parallel
- assert sresult_arr_rtl = sresult_arr_expected report "Error: wrong signed RTL result" severity ERROR;
- assert uresult_arr_rtl = uresult_arr_expected report "Error: wrong unsigned RTL result" severity ERROR;
- assert sresult_arr_ip = sresult_arr_expected report "Error: wrong signed IP result" severity ERROR;
- assert uresult_arr_ip = uresult_arr_expected report "Error: wrong unsigned IP result" severity ERROR;
+ assert sresult_arr_rtl = sresult_arr_expected
+ report "Error: wrong signed RTL result"
+ severity ERROR;
+ assert uresult_arr_rtl = uresult_arr_expected
+ report "Error: wrong unsigned RTL result"
+ severity ERROR;
+ assert sresult_arr_ip = sresult_arr_expected
+ report "Error: wrong signed IP result"
+ severity ERROR;
+ assert uresult_arr_ip = uresult_arr_expected
+ report "Error: wrong unsigned IP result"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index b2e150e364..51fb11386c 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -216,7 +216,9 @@ begin
begin
if rst = '0' then
if rising_edge(clk) then
- assert result_rtl = result_expected report "Error: wrong RTL result" severity ERROR;
+ assert result_rtl = result_expected
+ report "Error: wrong RTL result"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index f0211b988e..e2f1ab289d 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -125,7 +125,9 @@ architecture rtl of diag_data_buffer is
signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
begin
- assert c_mm_factor = 2**true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
+ assert c_mm_factor = 2**true_log2(c_mm_factor)
+ report "Only support mixed width data that uses a power of 2 multiple."
+ severity FAILURE;
ram_mm_miso <= i_ram_mm_miso;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index 278e607ea2..3ca7bde369 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -163,7 +163,9 @@ architecture rtl of diag_data_buffer_dev is
signal r, rin : reg_type;
begin
- assert c_mm_factor = 2**true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
+ assert c_mm_factor = 2**true_log2(c_mm_factor)
+ report "Only support mixed width data that uses a power of 2 multiple."
+ severity FAILURE;
out_wr_done <= nxt_wr_done;
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 4bf373e254..d858f6d252 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -328,7 +328,8 @@ begin
begin
if rising_edge(clk) then
if diff_dat(I) /= '0' and diff_dat(I) /= '1' then
- report "diag_rx_seq : undefined input" severity FAILURE;
+ report "diag_rx_seq : undefined input"
+ severity FAILURE;
end if;
end if;
end process;
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index 247f6d3def..d3101aa586 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -99,7 +99,9 @@ architecture str of diag_wg_wideband is
signal st_rdval : std_logic_vector(0 to g_wideband_factor - 1);
signal st_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
begin
- assert c_buf_file /= "UNUSED" report "diag_wg_wideband : no buffer waveform file available" severity FAILURE;
+ assert c_buf_file /= "UNUSED"
+ report "diag_wg_wideband : no buffer waveform file available"
+ severity FAILURE;
-- MM write same to all g_wideband_factor waveform buffers
-- MM read only from waveform buffer 0
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index f3c7d79645..5199e8a6db 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -181,7 +181,9 @@ architecture str of mms_diag_rx_seq is
signal stat_res_ok_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal stat_res_val_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
begin
- assert g_data_w >= g_seq_dat_w report "mms_diag_rx_seq: g_data_w < g_seq_dat_w is not allowed." severity FAILURE;
+ assert g_data_w >= g_seq_dat_w
+ report "mms_diag_rx_seq: g_data_w < g_seq_dat_w is not allowed."
+ severity FAILURE;
gen_nof_streams: for I in 0 to g_nof_streams - 1 generate
-- no unreplicate needed
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
index ef5aa9aa48..d38e4c2c7c 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
@@ -93,7 +93,8 @@ begin
gen_diag_en <= '0'; -- Disable frames generator
mon_diag_en <= '0'; -- Disable frames monitor
wait for c_nof_cycles * c_period;
- assert unsigned(gen_diag_frame_cnt) = unsigned(mon_diag_frame_cnt) report "wrong gen or mon count.";
+ assert unsigned(gen_diag_frame_cnt) = unsigned(mon_diag_frame_cnt)
+ report "wrong gen or mon count.";
wait for 10 * c_period;
-- Again
@@ -103,8 +104,10 @@ begin
wait for c_nof_cycles * c_period;
mon_diag_en <= '0'; -- Disable frames monitor
wait for 10 * c_period;
- assert unsigned(mon_diag_frame_cnt) = unsigned(gen_diag_frame_cnt) report "Wrong gen or mon count.";
- assert unsigned(mon_diag_error_cnt) = 0 report "Error count should be 0.";
+ assert unsigned(mon_diag_frame_cnt) = unsigned(gen_diag_frame_cnt)
+ report "Wrong gen or mon count.";
+ assert unsigned(mon_diag_error_cnt) = 0
+ report "Error count should be 0.";
hld_frame_cnt <= TO_UINT(gen_diag_frame_cnt);
mon_diag_en <= '1'; -- Enable frames monitor
wait for 10 * c_period;
@@ -115,8 +118,10 @@ begin
wait for 5 * c_nof_cycles * c_period;
gen_diag_en <= '0'; -- Disable frames generator
mon_diag_en <= '0'; -- Disable frames monitor
- assert unsigned(mon_diag_frame_cnt) = unsigned(gen_diag_frame_cnt) - hld_frame_cnt report "Wrong gen or mon count.";
- assert unsigned(mon_diag_error_cnt) /= 0 report "Error count should be > 0.";
+ assert unsigned(mon_diag_frame_cnt) = unsigned(gen_diag_frame_cnt) - hld_frame_cnt
+ report "Wrong gen or mon count.";
+ assert unsigned(mon_diag_error_cnt) /= 0
+ report "Error count should be > 0.";
wait for 10 * c_period;
wait for c_nof_cycles * c_period;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index 97180e901d..762e182618 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -388,64 +388,83 @@ package body tb_diag_pkg is
-- Verify
if tb_mode = s_expect_ok then
if v_rx_stat(1) /= '0' then
- report "Wrong diag result: no valid result." severity ERROR;
+ report "Wrong diag result: no valid result."
+ severity ERROR;
elsif v_rx_stat(0) /= '0' then
- report "Wrong diag result: one or more data errors." severity ERROR;
+ report "Wrong diag result: one or more data errors."
+ severity ERROR;
end if;
-- Read rx_cnt and tx_cnt again after some cycles
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
proc_common_wait_some_cycles(mm_clk, 1);
if v_rx_cnt = 0 then
- report "Wrong diag result: rx_cnt = 0." severity ERROR;
+ report "Wrong diag result: rx_cnt = 0."
+ severity ERROR;
elsif v_rx_cnt >= TO_UINT(rd_reg.rx_cnt) then
- report "Wrong diag result: rx_cnt did not increase." severity ERROR;
+ report "Wrong diag result: rx_cnt did not increase."
+ severity ERROR;
end if;
if v_tx_cnt = 0 then
- report "Wrong diag result: tx_cnt = 0." severity ERROR;
+ report "Wrong diag result: tx_cnt = 0."
+ severity ERROR;
elsif v_tx_cnt >= TO_UINT(rd_reg.tx_cnt) then
- report "Wrong diag result: tx_cnt did not increase." severity ERROR;
+ report "Wrong diag result: tx_cnt did not increase."
+ severity ERROR;
end if;
-- Read rx_sample again after some cycles
if unsigned(v_rx_sample) = 0 then
- report "Wrong diag sample: no valid sample." severity ERROR;
+ report "Wrong diag sample: no valid sample."
+ severity ERROR;
elsif v_rx_sample = rd_reg.rx_sample then
- report "Wrong diag sample: sample did not change." severity ERROR;
+ report "Wrong diag sample: sample did not change."
+ severity ERROR;
end if;
elsif tb_mode = s_expect_error then
if v_rx_stat(1) /= '0' then
- report "Wrong diag result: no valid result." severity ERROR;
+ report "Wrong diag result: no valid result."
+ severity ERROR;
elsif v_rx_stat(0) /= '1' then
- report "Wrong diag result: must detect data errors." severity ERROR;
+ report "Wrong diag result: must detect data errors."
+ severity ERROR;
end if;
if v_rx_cnt = 0 then
- report "Wrong diag result: rx_cnt = 0." severity ERROR;
+ report "Wrong diag result: rx_cnt = 0."
+ severity ERROR;
end if;
if v_tx_cnt = 0 then
- report "Wrong diag result: tx_cnt = 0." severity ERROR;
+ report "Wrong diag result: tx_cnt = 0."
+ severity ERROR;
end if;
elsif tb_mode = s_expect_no_result then
if v_rx_stat(1) /= '1' then
- report "Wrong diag result: must indicate no valid result." severity ERROR;
+ report "Wrong diag result: must indicate no valid result."
+ severity ERROR;
end if;
if v_rx_cnt /= 0 then
- report "Wrong diag result: rx_cnt /= 0." severity ERROR;
+ report "Wrong diag result: rx_cnt /= 0."
+ severity ERROR;
end if;
if unsigned(v_rx_sample) /= 0 then
- report "Wrong diag sample: rx_sample /= 0." severity ERROR;
+ report "Wrong diag sample: rx_sample /= 0."
+ severity ERROR;
end if;
elsif tb_mode = s_off then
if v_rx_cnt /= 0 then
- report "Wrong diag result: rx_cnt /= 0." severity ERROR;
+ report "Wrong diag result: rx_cnt /= 0."
+ severity ERROR;
end if;
if v_tx_cnt /= 0 then
- report "Wrong diag result: tx_cnt /= 0." severity ERROR;
+ report "Wrong diag result: tx_cnt /= 0."
+ severity ERROR;
end if;
if unsigned(v_rx_sample) /= 0 then
- report "Wrong diag sample: rx_sample /= 0." severity ERROR;
+ report "Wrong diag sample: rx_sample /= 0."
+ severity ERROR;
end if;
else
- report "Unknown verify mode" severity FAILURE;
+ report "Unknown verify mode"
+ severity FAILURE;
end if;
end proc_diag_seq_verify;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 35316f212a..2ac06df08e 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -292,7 +292,8 @@ begin
begin
if rising_edge(clk) then
if diag_res_val = '1' then
- assert unsigned(diag_res) = unsigned(expected_res) report "DIAG sequence mismatch occured.";
+ assert unsigned(diag_res) = unsigned(expected_res)
+ report "DIAG sequence mismatch occured.";
end if;
end if;
end process;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index 8521629f7d..23628a9164 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -163,13 +163,17 @@ begin
-- CALC mode
wg_mode <= c_diag_wg_mode_calc;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected hold OFF)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected hold OFF)"
+ severity ERROR;
restart <= '1';
wait for c_clk_period * 1;
restart <= '0';
cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected new CALC)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected new CALC)"
+ severity ERROR;
wait for c_clk_period * 3000;
@@ -177,14 +181,18 @@ begin
wait for c_clk_period * 1;
cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected new CALC ampl)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected new CALC ampl)"
+ severity ERROR;
wait for c_clk_period * 3000;
wg_phase <= integer(90.0 * c_phase_unit); -- no change phase without restart
wg_freq <= integer(0.5 / 512.0 * c_freq_unit); -- no change freq without restart
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected hold CALC phase and freq)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected hold CALC phase and freq)"
+ severity ERROR;
wait for c_clk_period * 3000;
@@ -193,7 +201,9 @@ begin
restart <= '0';
cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected new CALC phase and freq)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected new CALC phase and freq)"
+ severity ERROR;
wait for c_clk_period * 3000;
@@ -202,26 +212,34 @@ begin
wait for c_clk_period * 1;
cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected immediately OFF)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected immediately OFF)"
+ severity ERROR;
restart <= '1';
wait for c_clk_period * 1;
restart <= '0';
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected still OFF)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected still OFF)"
+ severity ERROR;
wait for c_clk_period * 200;
-- SINGLE mode
wg_mode <= c_diag_wg_mode_single;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected hold OFF)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected hold OFF)"
+ severity ERROR;
for I in 0 to 3 loop
restart <= '1';
wait for c_clk_period * 1;
restart <= '0';
cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected new SINGLE)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected new SINGLE)"
+ severity ERROR;
wait for c_clk_period * c_buf_nof_dat;
wait for c_clk_period * 300;
end loop;
@@ -229,14 +247,18 @@ begin
-- REPEAT mode
wg_mode <= c_diag_wg_mode_repeat;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected hold SINGLE)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected hold SINGLE)"
+ severity ERROR;
for I in 0 to 1 loop
restart <= '1';
wait for c_clk_period * 1;
restart <= '0';
cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected new REPEAT)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected new REPEAT)"
+ severity ERROR;
wait for c_clk_period * c_buf_nof_dat * 5;
wait for c_clk_period * 200;
end loop;
@@ -246,12 +268,16 @@ begin
wait for c_clk_period * 1;
cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately, no need for restart
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected immediately OFF)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected immediately OFF)"
+ severity ERROR;
restart <= '1';
wait for c_clk_period * 1;
restart <= '0';
wait for c_clk_period * 10;
- assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected still OFF)" severity ERROR;
+ assert mon_ctrl = cur_ctrl
+ report "Wrong mon_ctrl (expected still OFF)"
+ severity ERROR;
wait for c_clk_period * 200;
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
index f18f50f775..0ecc88cfff 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
@@ -358,18 +358,26 @@ begin
if verify_sosi_arr_en = '1' then
for I in 0 to g_nof_streams - 1 loop
-- All outputs have the same framing
- assert out_sosi_0.sync = out_sosi_arr(I).sync report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sync";
- assert out_sosi_0.bsn = out_sosi_arr(I).bsn report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).bsn";
- assert out_sosi_0.im = out_sosi_arr(I).im report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
- assert out_sosi_0.valid = out_sosi_arr(I).valid report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).valid";
- assert out_sosi_0.sop = out_sosi_arr(I).sop report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sop";
- assert out_sosi_0.eop = out_sosi_arr(I).eop report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).eop";
+ assert out_sosi_0.sync = out_sosi_arr(I).sync
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sync";
+ assert out_sosi_0.bsn = out_sosi_arr(I).bsn
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).bsn";
+ assert out_sosi_0.im = out_sosi_arr(I).im
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
+ assert out_sosi_0.valid = out_sosi_arr(I).valid
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).valid";
+ assert out_sosi_0.sop = out_sosi_arr(I).sop
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sop";
+ assert out_sosi_0.eop = out_sosi_arr(I).eop
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).eop";
if g_use_bg_buffer_ram = true then
-- Only the re part differs per output given the BG buffer data from c_file_name_prefix = "data/bf_in_data"
- assert TO_UINT(out_sosi_0.re) = TO_UINT(out_sosi_arr(I).re) - I * 4 report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).re";
+ assert TO_UINT(out_sosi_0.re) = TO_UINT(out_sosi_arr(I).re) - I * 4
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).re";
else
- assert out_sosi_0.im = out_sosi_arr(I).im report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
+ assert out_sosi_0.im = out_sosi_arr(I).im
+ report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
end if;
end loop;
end if;
@@ -431,8 +439,10 @@ begin
begin
if g_use_usr_input = true and g_use_bg = false and g_use_tx_seq = false then
if rising_edge(clk) then
- assert out_sosi_arr = usr_fifo_src_out_arr report "tb_mms_diag_block_gen: out_sosi_arr /= usr_src_out_arr";
- assert usr_fifo_src_in_arr = out_siso_arr report "tb_mms_diag_block_gen: usr_src_in_arr /= out_siso_arr";
+ assert out_sosi_arr = usr_fifo_src_out_arr
+ report "tb_mms_diag_block_gen: out_sosi_arr /= usr_src_out_arr";
+ assert usr_fifo_src_in_arr = out_siso_arr
+ report "tb_mms_diag_block_gen: usr_src_in_arr /= out_siso_arr";
end if;
end if;
end process;
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 57222de7e0..e75665ffc8 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -128,13 +128,17 @@ begin
-- . write some arbitrary integer values
proc_diag_seq_rx_write_steps(c_st_0, c_rx_steps_arr_access, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
for I in 0 to c_diag_seq_rx_reg_nof_steps - 1 loop
- assert rd_reg_arr(c_st_0).rx_steps(I) = c_rx_steps_arr_access(I) report "Wrong diag rx_steps read back." severity ERROR;
+ assert rd_reg_arr(c_st_0).rx_steps(I) = c_rx_steps_arr_access(I)
+ report "Wrong diag rx_steps read back."
+ severity ERROR;
end loop;
-- . write default increment +1 to have same behaviour as with g_use_steps=FALSE and diag_sel = "CNTR"
proc_diag_seq_rx_write_steps(c_st_0, c_rx_steps_arr_ones, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
for I in 0 to c_diag_seq_rx_reg_nof_steps - 1 loop
- assert rd_reg_arr(c_st_0).rx_steps(I) = c_rx_steps_arr_ones(I) report "Wrong diag rx_steps read back." severity ERROR;
+ assert rd_reg_arr(c_st_0).rx_steps(I) = c_rx_steps_arr_ones(I)
+ report "Wrong diag rx_steps read back."
+ severity ERROR;
end loop;
-------------------------------------------------------------------------
@@ -162,7 +166,9 @@ begin
-- Check that there is valid data
if g_flow_control_verify = e_active then
- assert rx_snk_in_arr(0).valid = '1' report "Wrong diag result: no valid data at rx_snk_in_arr(0)." severity ERROR;
+ assert rx_snk_in_arr(0).valid = '1'
+ report "Wrong diag result: no valid data at rx_snk_in_arr(0)."
+ severity ERROR;
end if;
-------------------------------------------------------------------------
@@ -248,7 +254,9 @@ begin
-- Check that there is valid data
if g_flow_control_verify = e_active then
- assert rx_snk_in_arr(1).valid = '1' report "Wrong diag result: no valid data at rx_snk_in_arr(1)." severity ERROR;
+ assert rx_snk_in_arr(1).valid = '1'
+ report "Wrong diag result: no valid data at rx_snk_in_arr(1)."
+ severity ERROR;
end if;
stream_index <= 0; -- back to stream 0
end if;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
index 8b9d74a9f1..cb60d9daf0 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
@@ -133,7 +133,9 @@ package body tb_diagnostics_trnb_pkg is
proc_common_wait_some_cycles(mm_clk, 1);
-- Verify results
- assert TO_UINT(v_diag_results_valid) = c_nof_gx_mask and TO_UINT(v_diag_results) = 0 report "proc_diagnostics_trnb_run_and_verify: TRNB diagnostics on went wrong on node " & natural'image(c_chip_id) severity ERROR;
+ assert TO_UINT(v_diag_results_valid) = c_nof_gx_mask and TO_UINT(v_diag_results) = 0
+ report "proc_diagnostics_trnb_run_and_verify: TRNB diagnostics on went wrong on node " & natural'image(c_chip_id)
+ severity ERROR;
-- Disable diagnostics
proc_mem_mm_bus_wr(19, 0, mm_clk, mm_mosi); -- set sink disable
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
index 0abb80fa52..66bfd15bf9 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
@@ -172,11 +172,15 @@ architecture rtl of dp_block_gen_valid_arr is
function parameter_asserts(g_check_input_sync : boolean; g_nof_pages_bsn : natural) return boolean is
begin
if g_check_input_sync = true then
- assert g_nof_pages_bsn = 0 report "When g_check_input_sync=TRUE then g_nof_pages_bsn must be 0." severity FAILURE;
+ assert g_nof_pages_bsn = 0
+ report "When g_check_input_sync=TRUE then g_nof_pages_bsn must be 0."
+ severity FAILURE;
-- because snk_in.sync and snk_in.bsn are then already aligned with the first snk_in.valid
end if;
if g_nof_pages_bsn > 0 then
- assert g_check_input_sync = false report "When g_nof_pages_bsn>0 then g_check_input_sync must be false." severity FAILURE;
+ assert g_check_input_sync = false
+ report "When g_nof_pages_bsn>0 then g_check_input_sync must be false."
+ severity FAILURE;
-- because snk_in.sync and snk_in.bsn are then NOT aligned with the first snk_in.valid
end if;
return true;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
index 32c4a07830..eab7a8aeec 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
@@ -62,7 +62,9 @@ architecture rtl of dp_block_validate_channel is
signal remove_sosi : t_dp_sosi;
signal keep_sosi : t_dp_sosi;
begin
- assert g_mode = "=" or g_mode = "<" or g_mode = ">" report "g_mode must be one of three options: '=', '<' or '>'" severity ERROR;
+ assert g_mode = "=" or g_mode = "<" or g_mode = ">"
+ report "g_mode must be one of three options: '=', '<' or '>'"
+ severity ERROR;
gen_equal : if g_mode = "=" generate -- remove all blocks with ch = remove_channel
remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
'1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index f92809dc54..f8dec4c6da 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -180,7 +180,9 @@ architecture rtl of dp_bsn_sync_scheduler is
signal output_sync : std_logic;
signal output_sosi : t_dp_sosi;
begin
- assert g_block_size >= 2 report "g_block_size must be >= 2." severity FAILURE;
+ assert g_block_size >= 2
+ report "g_block_size must be >= 2."
+ severity FAILURE;
-- Capture monitoring info
mon_current_input_bsn <= in_sosi.bsn(g_bsn_w - 1 downto 0) when rising_edge(clk) and in_sosi.sop = '1';
diff --git a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
index 0326cf2138..f0137e9809 100644
--- a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
@@ -62,7 +62,8 @@ architecture rtl of dp_calculate_crc is
elsif g_data_w = 32 and g_crc_w = 32 then v_crc := nextCRC32_D32(data, crc);
elsif g_data_w = 64 and g_crc_w = 32 then v_crc := nextCRC32_D64(data, crc);
else
- report "Data width and CRC width combination not supported (yet)" severity FAILURE;
+ report "Data width and CRC width combination not supported (yet)"
+ severity FAILURE;
end if;
return v_crc;
end func_next_crc;
diff --git a/libraries/base/dp/src/vhdl/dp_concat.vhd b/libraries/base/dp/src/vhdl/dp_concat.vhd
index 27cdc9c281..b9c16a034a 100644
--- a/libraries/base/dp/src/vhdl/dp_concat.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat.vhd
@@ -122,7 +122,9 @@ architecture rtl of dp_concat is
signal i_src_out : t_dp_sosi;
signal nxt_src_out : t_dp_sosi;
begin
- assert (g_data_w mod g_symbol_w) = 0 report "dp_concat : g_data_w/g_symbol_w must be an integer" severity FAILURE;
+ assert (g_data_w mod g_symbol_w) = 0
+ report "dp_concat : g_data_w/g_symbol_w must be an integer"
+ severity FAILURE;
snk_out_arr <= i_snk_out_arr;
src_out <= i_src_out;
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index dfc63459ff..8b5478abeb 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -92,7 +92,9 @@ architecture str of dp_concat_field_blk is
signal reg_hdr_dat_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
- assert c_dp_field_blk_snk_data_w <= c_dp_stream_data_w report "Number of header bits must fit in t_dp_sosi data field." severity FAILURE;
+ assert c_dp_field_blk_snk_data_w <= c_dp_stream_data_w
+ report "Number of header bits must fit in t_dp_sosi data field."
+ severity FAILURE;
---------------------------------------------------------------------------------------
-- Create header block & concatenate header to offload stream.
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
index 0ee926636d..c50beb43bd 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
@@ -71,7 +71,9 @@ architecture str of dp_fifo_from_mm is
signal availw : std_logic_vector(c_usedw_w - 1 downto 0); -- no need to use ceil_log2(g_fifo_size+1), because availw = g_fifo_size - g_fifo_af_margin < g_fifo_size when the FIFO is empty
begin
- assert g_fifo_af_margin /= 0 report "dp_fifo_from_mm.vhd : the g_fifo_af_margin must be > 0" severity FAILURE;
+ assert g_fifo_af_margin /= 0
+ report "dp_fifo_from_mm.vhd : the g_fifo_af_margin must be > 0"
+ severity FAILURE;
-- Combinatorial logic
availw <= std_logic_vector(to_unsigned(c_fifo_almost_full, c_usedw_w) - unsigned(usedw)); -- No danger for underflow (< 0) because usedw will always be <= c_fifo_almost_full
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
index 58b3a482af..85d1906175 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
@@ -224,7 +224,9 @@ begin
timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
- assert not(rising_edge(clk) and timeout_evt = '1') report "rad_frame_rx timeout occurred!" severity WARNING;
+ assert not(rising_edge(clk) and timeout_evt = '1')
+ report "rad_frame_rx timeout occurred!"
+ severity WARNING;
-- define flush_val to prepare for throttle support of out_val during flush, default no throttle support yet
flush_val <= flush_en;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
index 032a348855..df7fbd0603 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
@@ -100,7 +100,9 @@ architecture str of dp_offload_tx_v3 is
signal mm_fields_slv_out_arr : t_slv_1024_arr(g_nof_streams - 1 downto 0);
signal field_override_arr : std_logic_vector(g_hdr_field_arr'range) := g_hdr_field_sel; -- 1 override bit per field
begin
- assert c_dp_field_blk_snk_data_w <= c_dp_stream_data_w report "Number of header bits must fit in t_dp_sosi data field." severity FAILURE;
+ assert c_dp_field_blk_snk_data_w <= c_dp_stream_data_w
+ report "Number of header bits must fit in t_dp_sosi data field."
+ severity FAILURE;
---------------------------------------------------------------------------------------
-- Create header block & concatenate header to offload stream.
---------------------------------------------------------------------------------------
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
index 2fe927abf4..96d5e27e40 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
@@ -58,7 +58,9 @@ architecture rtl of dp_packet_dec_channel_lo is
signal channel_lo_hold : std_logic_vector(g_channel_lo - 1 downto 0);
signal nxt_channel_lo_hold : std_logic_vector(g_channel_lo - 1 downto 0);
begin
- assert g_channel_lo + 1 <= g_data_w report "dp_packet_dec_channel_lo : g_channel_lo does not fit in g_data_w" severity FAILURE;
+ assert g_channel_lo + 1 <= g_data_w
+ report "dp_packet_dec_channel_lo : g_channel_lo does not fit in g_data_w"
+ severity FAILURE;
-- Pass on the flow control
snk_out <= src_in;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
index 9ce09443d7..480d880a0e 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
@@ -65,7 +65,9 @@ end dp_packet_enc_channel_lo;
architecture rtl of dp_packet_enc_channel_lo is
begin
- assert g_channel_lo + 1 <= g_data_w report "dp_packet_enc_channel_lo : g_channel_lo does not fit in g_data_w" severity FAILURE;
+ assert g_channel_lo + 1 <= g_data_w
+ report "dp_packet_enc_channel_lo : g_channel_lo does not fit in g_data_w"
+ severity FAILURE;
-- Pass on the flow control
snk_out <= src_in;
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index c063da2ad8..50ab2e3f24 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -74,7 +74,9 @@ architecture str of dp_requantize is
signal out_ovr_re : std_logic;
signal out_ovr_im : std_logic;
begin
- assert g_gain_w = 0 report "dp_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w." severity FAILURE;
+ assert g_gain_w = 0
+ report "dp_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w."
+ severity FAILURE;
---------------------------------------------------------------
-- Requantize the sosi data field
diff --git a/libraries/base/dp/src/vhdl/dp_split.vhd b/libraries/base/dp/src/vhdl/dp_split.vhd
index 14f0547efc..ea938e437f 100644
--- a/libraries/base/dp/src/vhdl/dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split.vhd
@@ -145,7 +145,9 @@ architecture rtl of dp_split is
signal nof_remain_reg : std_logic_vector(c_empty_w - 1 downto 0);
signal nxt_nof_remain_reg : std_logic_vector(c_empty_w - 1 downto 0);
begin
- assert (g_data_w mod g_symbol_w) = 0 report "dp_split : g_data_w/g_symbol_w must be an integer" severity FAILURE;
+ assert (g_data_w mod g_symbol_w) = 0
+ report "dp_split : g_data_w/g_symbol_w must be an integer"
+ severity FAILURE;
snk_out <= i_snk_out;
src_out_arr <= i_src_out_arr;
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index 634513a77a..785cc98b9e 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -422,7 +422,8 @@ package body dp_stream_pkg is
if rising_edge(clk) then
-- Check DP sink
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
@@ -453,7 +454,8 @@ package body dp_stream_pkg is
for i in 0 to sosi_arr'length - 1 loop
-- Check DP sink
if sosi_arr(i).valid = '1' and ready_reg(i * (c_ready_latency + 1) + 1) = '0' then
- report "RL ERROR" severity FAILURE;
+ report "RL ERROR"
+ severity FAILURE;
end if;
ready_reg(i * (c_ready_latency + 1) + 1 to i * (c_ready_latency + 1) + c_ready_latency) <= ready_reg(i * (c_ready_latency + 1) to i * (c_ready_latency + 1) + c_ready_latency - 1);
end loop;
@@ -674,7 +676,9 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
+ assert nof_symbols_from_tail < vN
+ report "func_dp_data_shift_first : no symbols from head"
+ severity FAILURE;
-- use the other sosi from head_sosi
v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
for I in 1 to vN - 1 loop -- I > 0
@@ -724,8 +728,12 @@ package body dp_stream_pkg is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
- assert vK > 0 report "func_dp_data_shift_last : no symbols from tail" severity FAILURE;
- assert vK + vL <= vN report "func_dp_data_shift_last : impossible shift" severity FAILURE;
+ assert vK > 0
+ report "func_dp_data_shift_last : no symbols from tail"
+ severity FAILURE;
+ assert vK + vL <= vN
+ report "func_dp_data_shift_last : impossible shift"
+ severity FAILURE;
v_sosi := tail_sosi;
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 82eb03aa00..f8ff959eb6 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -134,8 +134,12 @@ architecture rtl of dp_strobe_total_count is
signal cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0);
signal hold_cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0) := (others => (others => '0'));
begin
- assert g_nof_counts <= c_nof_counts_max report "Too many counters to fit REGMAP." severity FAILURE;
- assert g_count_w <= g_mm_w * 2 report "Too wide counter to fit REGMAP." severity FAILURE;
+ assert g_nof_counts <= c_nof_counts_max
+ report "Too many counters to fit REGMAP."
+ severity FAILURE;
+ assert g_count_w <= g_mm_w * 2
+ report "Too wide counter to fit REGMAP."
+ severity FAILURE;
-- Only clear on MM write, to allow MM read of all register fields without clear
mm_cnt_clear <= reg_mosi.wr when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0';
diff --git a/libraries/base/dp/src/vhdl/dp_unframe.vhd b/libraries/base/dp/src/vhdl/dp_unframe.vhd
index 0178a44fe4..68a6490842 100644
--- a/libraries/base/dp/src/vhdl/dp_unframe.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unframe.vhd
@@ -77,7 +77,7 @@ begin
-- synthesis translate_off
assert g_fsn_w <= g_dat_w
report "g_fsn_w must be smaller than or equal to g_dat_w"
- severity ERROR;
+ severity ERROR;
-- synthesis translate_on
end dp_unframe;
diff --git a/libraries/base/dp/tb/vhdl/dp_statistics.vhd b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
index bdbbbc7a7f..31463af70d 100644
--- a/libraries/base/dp/tb/vhdl/dp_statistics.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
@@ -102,16 +102,20 @@ begin
p_dp_done_check: process(dp_clk)
begin
if timeout = '1' and dp_done = '0' then
- report "[dp_statistics] Timeout occured!" severity ERROR; -- report ERROR to have Error in log
- report "[dp_statistics] Timeout occured!" severity FAILURE; -- report FAILURE to stop simulation
+ report "[dp_statistics] Timeout occured!"
+ severity ERROR; -- report ERROR to have Error in log
+ report "[dp_statistics] Timeout occured!"
+ severity FAILURE; -- report FAILURE to stop simulation
elsif dp_done = '1' then
if rising_edge(dp_clk) then
-- report valid count
if g_check_nof_valid = true then
if valid_count /= g_check_nof_valid_ref then
- report "[dp_statistics] Valid count " & integer'image(valid_count) & " does not match reference " & integer'image(g_check_nof_valid_ref) severity ERROR;
+ report "[dp_statistics] Valid count " & integer'image(valid_count) & " does not match reference " & integer'image(g_check_nof_valid_ref)
+ severity ERROR;
else
- report "[dp_statistics] Valid count " & integer'image(valid_count) & " is OK" severity NOTE; -- Note to show that the check indeed did happen
+ report "[dp_statistics] Valid count " & integer'image(valid_count) & " is OK"
+ severity NOTE; -- Note to show that the check indeed did happen
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index b874761a17..4f99257868 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -154,7 +154,9 @@ begin
while tb_end = '0' loop
wait until rising_edge(clk);
if block_done = '1' then
- assert stop_address = TO_UINT(wr_mosi.wrdata(c_ram.dat_w - 1 downto 0)) - c_init report "wrong data at mm_done signal, must be same as stop_address + c_init" severity ERROR;
+ assert stop_address = TO_UINT(wr_mosi.wrdata(c_ram.dat_w - 1 downto 0)) - c_init
+ report "wrong data at mm_done signal, must be same as stop_address + c_init"
+ severity ERROR;
end if;
end loop;
wait;
@@ -187,12 +189,18 @@ begin
while tb_end = '0' loop
wait until rising_edge(clk);
if ram_rd_val = '1' then
- assert rd_data = rd_nxt_data report "wrong order of RAM values" severity ERROR;
- assert rd_data - c_init <= stop_address report "wrong RAM values, greater than block size" severity ERROR;
+ assert rd_data = rd_nxt_data
+ report "wrong order of RAM values"
+ severity ERROR;
+ assert rd_data - c_init <= stop_address
+ report "wrong RAM values, greater than block size"
+ severity ERROR;
rd_nxt_data <= rd_nxt_data + 1;
end if;
if ram_rd_val = '0' and ram_prev_rd_val = '1' then -- If ram_rd_val goes from hi tot lo.
- assert rd_data - c_init = stop_address report "wrong last RAM values, not same as block size" severity ERROR;
+ assert rd_data - c_init = stop_address
+ report "wrong last RAM values, not same as block size"
+ severity ERROR;
end if;
end loop;
wait;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
index 91d7db7738..1698d4de7d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
@@ -179,7 +179,9 @@ begin
p_verify : process(clk)
begin
if rising_edge(clk) then
- assert verify_sosi = pipeline_sosi report "Wrong sosi" severity ERROR;
+ assert verify_sosi = pipeline_sosi
+ report "Wrong sosi"
+ severity ERROR;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
index d03c07a6ad..777cdbb295 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
@@ -202,31 +202,55 @@ begin
begin
if rising_edge(clk) then
-- verify all sosi fields
- assert verify_sosi.data = pipeline_total_sosi.data report "Wrong sosi.data " severity ERROR;
- assert verify_sosi.re = pipeline_total_sosi.re report "Wrong sosi.re " severity ERROR;
- assert verify_sosi.im = pipeline_total_sosi.im report "Wrong sosi.im " severity ERROR;
- assert verify_sosi.sync = pipeline_total_sosi.sync report "Wrong sosi.sync " severity ERROR;
- assert verify_sosi.valid = pipeline_total_sosi.valid report "Wrong sosi.valid " severity ERROR;
- assert verify_sosi.sop = pipeline_total_sosi.sop report "Wrong sosi.sop " severity ERROR;
- assert verify_sosi.eop = pipeline_total_sosi.eop report "Wrong sosi.eop " severity ERROR;
+ assert verify_sosi.data = pipeline_total_sosi.data
+ report "Wrong sosi.data "
+ severity ERROR;
+ assert verify_sosi.re = pipeline_total_sosi.re
+ report "Wrong sosi.re "
+ severity ERROR;
+ assert verify_sosi.im = pipeline_total_sosi.im
+ report "Wrong sosi.im "
+ severity ERROR;
+ assert verify_sosi.sync = pipeline_total_sosi.sync
+ report "Wrong sosi.sync "
+ severity ERROR;
+ assert verify_sosi.valid = pipeline_total_sosi.valid
+ report "Wrong sosi.valid "
+ severity ERROR;
+ assert verify_sosi.sop = pipeline_total_sosi.sop
+ report "Wrong sosi.sop "
+ severity ERROR;
+ assert verify_sosi.eop = pipeline_total_sosi.eop
+ report "Wrong sosi.eop "
+ severity ERROR;
if g_reshape_bsn = false then
- assert verify_sosi.bsn = pipeline_total_sosi.bsn report "Wrong sosi.bsn" severity ERROR;
+ assert verify_sosi.bsn = pipeline_total_sosi.bsn
+ report "Wrong sosi.bsn"
+ severity ERROR;
else
if pipeline_dut_sosi.sync = '1' then
v_global_bsn := TO_UINT(pipeline_dut_sosi.bsn);
end if;
if reshape_sosi.sync = '1' then
- assert TO_UINT(reshape_sosi.bsn) = v_global_bsn report "Wrong global sosi.bsn at sync" severity ERROR;
+ assert TO_UINT(reshape_sosi.bsn) = v_global_bsn
+ report "Wrong global sosi.bsn at sync"
+ severity ERROR;
v_local_bsn := 0;
elsif reshape_sosi.sop = '1' then
v_local_bsn := v_local_bsn + 1;
- assert TO_UINT(reshape_sosi.bsn) = v_local_bsn report "Wrong local sosi.bsn increment at sop" severity ERROR;
+ assert TO_UINT(reshape_sosi.bsn) = v_local_bsn
+ report "Wrong local sosi.bsn increment at sop"
+ severity ERROR;
end if;
end if;
- assert verify_sosi.empty = pipeline_total_sosi.empty report "Wrong sosi.empty" severity ERROR;
- assert verify_sosi.err = pipeline_total_sosi.err report "Wrong sosi.err" severity ERROR;
+ assert verify_sosi.empty = pipeline_total_sosi.empty
+ report "Wrong sosi.empty"
+ severity ERROR;
+ assert verify_sosi.err = pipeline_total_sosi.err
+ report "Wrong sosi.err"
+ severity ERROR;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
index 1162980ee8..b9c38accd3 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
@@ -176,40 +176,74 @@ begin
---------------------------------------------------------------------
if g_index_lo = 0 then
-- Direct sosi verification because sync and BSN are not moved when g_index_lo=0
- assert verify_sosi = reference_sosi report "Wrong selected subsequent blocks" severity ERROR;
+ assert verify_sosi = reference_sosi
+ report "Wrong selected subsequent blocks"
+ severity ERROR;
else
-- Account for that sync and BSN of first block are moved to g_index_lo>0
if reference_blk_cnt = g_index_lo then
-- First block
-- . verify moved sync and bsn
if reference_sosi.sop = '1' then
- assert verify_sosi.sync = sync_sosi.sync report "Missing selected first block sync" severity ERROR;
- assert verify_sosi.bsn = sync_sosi.bsn report "Wrong selected first block bsn" severity ERROR;
+ assert verify_sosi.sync = sync_sosi.sync
+ report "Missing selected first block sync"
+ severity ERROR;
+ assert verify_sosi.bsn = sync_sosi.bsn
+ report "Wrong selected first block bsn"
+ severity ERROR;
else
- assert verify_sosi.sync = '0' report "Unexpected selected first block sync" severity ERROR;
+ assert verify_sosi.sync = '0'
+ report "Unexpected selected first block sync"
+ severity ERROR;
end if;
-- . verify other sosi fields
- assert verify_sosi.data = reference_sosi.data report "Wrong selected first block data" severity ERROR;
- assert verify_sosi.re = reference_sosi.re report "Wrong selected first block re" severity ERROR;
- assert verify_sosi.im = reference_sosi.im report "Wrong selected first block im" severity ERROR;
- assert verify_sosi.channel = reference_sosi.channel report "Wrong selected first block channel" severity ERROR;
- assert verify_sosi.empty = reference_sosi.empty report "Wrong selected first block empty" severity ERROR;
- assert verify_sosi.valid = reference_sosi.valid report "Wrong selected first block valid" severity ERROR;
- assert verify_sosi.sop = reference_sosi.sop report "Wrong selected first block sop" severity ERROR;
- assert verify_sosi.eop = reference_sosi.eop report "Wrong selected first block eop" severity ERROR;
+ assert verify_sosi.data = reference_sosi.data
+ report "Wrong selected first block data"
+ severity ERROR;
+ assert verify_sosi.re = reference_sosi.re
+ report "Wrong selected first block re"
+ severity ERROR;
+ assert verify_sosi.im = reference_sosi.im
+ report "Wrong selected first block im"
+ severity ERROR;
+ assert verify_sosi.channel = reference_sosi.channel
+ report "Wrong selected first block channel"
+ severity ERROR;
+ assert verify_sosi.empty = reference_sosi.empty
+ report "Wrong selected first block empty"
+ severity ERROR;
+ assert verify_sosi.valid = reference_sosi.valid
+ report "Wrong selected first block valid"
+ severity ERROR;
+ assert verify_sosi.sop = reference_sosi.sop
+ report "Wrong selected first block sop"
+ severity ERROR;
+ assert verify_sosi.eop = reference_sosi.eop
+ report "Wrong selected first block eop"
+ severity ERROR;
else
-- Subsequent blocks
- assert verify_sosi = reference_sosi report "Wrong selected subsequent blocks" severity ERROR;
+ assert verify_sosi = reference_sosi
+ report "Wrong selected subsequent blocks"
+ severity ERROR;
end if;
end if;
else
---------------------------------------------------------------------
-- Skipped blocks
---------------------------------------------------------------------
- assert verify_sosi.sync = '0' report "Wrong skipped sync" severity ERROR;
- assert verify_sosi.valid = '0' report "Wrong skipped valid" severity ERROR;
- assert verify_sosi.sop = '0' report "Wrong skipped sop" severity ERROR;
- assert verify_sosi.eop = '0' report "Wrong skipped eop" severity ERROR;
+ assert verify_sosi.sync = '0'
+ report "Wrong skipped sync"
+ severity ERROR;
+ assert verify_sosi.valid = '0'
+ report "Wrong skipped valid"
+ severity ERROR;
+ assert verify_sosi.sop = '0'
+ report "Wrong skipped sop"
+ severity ERROR;
+ assert verify_sosi.eop = '0'
+ report "Wrong skipped eop"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
index 9ec17af29e..d8dd2f04cf 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
@@ -202,11 +202,19 @@ begin
end if;
if v_valid_blk then -- we expect a block
- assert verify_sosi = reference_sosi report "Unexpected difference between in / out sosi" severity ERROR;
+ assert verify_sosi = reference_sosi
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
else -- we expect no block
- assert verify_sosi.valid = '0' report "Wrong, valid is not '0' which is unexpected." severity ERROR;
- assert verify_sosi.sop = '0' report "Wrong, sop is not '0' which is unexpected." severity ERROR;
- assert verify_sosi.eop = '0' report "Wrong, eop is not '0' which is unexpected." severity ERROR;
+ assert verify_sosi.valid = '0'
+ report "Wrong, valid is not '0' which is unexpected."
+ severity ERROR;
+ assert verify_sosi.sop = '0'
+ report "Wrong, sop is not '0' which is unexpected."
+ severity ERROR;
+ assert verify_sosi.eop = '0'
+ report "Wrong, eop is not '0' which is unexpected."
+ severity ERROR;
end if;
end if;
end process;
@@ -218,14 +226,20 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- assert c_nof_sync = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong total sync count" severity ERROR;
+ assert c_nof_sync = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong total sync count"
+ severity ERROR;
proc_mem_mm_bus_rd(0, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
if g_bsn_init >= g_nof_blocks_per_sync then -- should have 1 discarded sync
- assert 1 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong discarded sync count" severity ERROR;
+ assert 1 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong discarded sync count"
+ severity ERROR;
else -- 0 discarded sync
- assert 0 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong discarded sync count" severity ERROR;
+ assert 0 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong discarded sync count"
+ severity ERROR;
end if;
proc_common_wait_some_cycles(dp_clk, 100);
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
index d6ba2d4592..812c644fbc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
@@ -148,41 +148,101 @@ begin
if rising_edge(dp_clk) then
if reference_sosi.valid = '1' then
if TO_UINT(reference_sosi.channel) = g_remove_channel and g_mode = "=" then
- assert remove_sosi = reference_sosi report "remove_sosi does not contain removed block!" severity ERROR;
- assert keep_sosi.valid = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.sop = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.eop = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.sync = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
+ assert remove_sosi = reference_sosi
+ report "remove_sosi does not contain removed block!"
+ severity ERROR;
+ assert keep_sosi.valid = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.sop = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.eop = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.sync = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
elsif g_mode = "=" then
- assert keep_sosi = reference_sosi report "No block in keep_sosi" severity ERROR;
- assert remove_sosi.valid = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.sop = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.eop = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.sync = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
+ assert keep_sosi = reference_sosi
+ report "No block in keep_sosi"
+ severity ERROR;
+ assert remove_sosi.valid = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.sop = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.eop = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.sync = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
elsif TO_UINT(reference_sosi.channel) < g_remove_channel and g_mode = "<" then
- assert remove_sosi = reference_sosi report "remove_sosi does not contain removed block!" severity ERROR;
- assert keep_sosi.valid = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.sop = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.eop = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.sync = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
+ assert remove_sosi = reference_sosi
+ report "remove_sosi does not contain removed block!"
+ severity ERROR;
+ assert keep_sosi.valid = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.sop = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.eop = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.sync = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
elsif g_mode = "<" then
- assert keep_sosi = reference_sosi report "No block in keep_sosi" severity ERROR;
- assert remove_sosi.valid = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.sop = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.eop = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.sync = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
+ assert keep_sosi = reference_sosi
+ report "No block in keep_sosi"
+ severity ERROR;
+ assert remove_sosi.valid = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.sop = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.eop = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.sync = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
elsif TO_UINT(reference_sosi.channel) > g_remove_channel and g_mode = ">" then
- assert remove_sosi = reference_sosi report "remove_sosi does not contain removed block!" severity ERROR;
- assert keep_sosi.valid = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.sop = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.eop = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
- assert keep_sosi.sync = '0' report "Wrong, removed block occurs in keep_sosi!" severity ERROR;
+ assert remove_sosi = reference_sosi
+ report "remove_sosi does not contain removed block!"
+ severity ERROR;
+ assert keep_sosi.valid = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.sop = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.eop = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
+ assert keep_sosi.sync = '0'
+ report "Wrong, removed block occurs in keep_sosi!"
+ severity ERROR;
elsif g_mode = ">" then
- assert keep_sosi = reference_sosi report "No block in keep_sosi" severity ERROR;
- assert remove_sosi.valid = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.sop = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.eop = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
- assert remove_sosi.sync = '0' report "Wrong, block occurs in remove_sosi which is unexpected!" severity ERROR;
+ assert keep_sosi = reference_sosi
+ report "No block in keep_sosi"
+ severity ERROR;
+ assert remove_sosi.valid = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.sop = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.eop = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
+ assert remove_sosi.sync = '0'
+ report "Wrong, block occurs in remove_sosi which is unexpected!"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index fd24928a06..edc8d0ad16 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -200,18 +200,40 @@ begin
begin
if rising_edge(dp_clk) then
if reference_cnt_reg = 0 then -- no errors so we expect a block
- assert verify_sosi.valid = reference_sosi.valid report "Unexpected difference between in / out sosi" severity ERROR;
- assert verify_sosi.sop = reference_sosi.sop report "Unexpected difference between in / out sosi" severity ERROR;
- assert verify_sosi.eop = reference_sosi.eop report "Unexpected difference between in / out sosi" severity ERROR;
- assert verify_sosi.data = reference_sosi.data report "Unexpected difference between in / out sosi" severity ERROR;
- assert verify_sosi.channel = reference_sosi.channel report "Unexpected difference between in / out sosi" severity ERROR;
- assert verify_sosi.bsn = reference_sosi.bsn report "Unexpected difference between in / out sosi" severity ERROR;
- assert verify_sosi.empty = reference_sosi.empty report "Unexpected difference between in / out sosi" severity ERROR;
- assert verify_sosi.sync = reference_sosi.sync report "Unexpected difference between in / out sosi" severity ERROR;
+ assert verify_sosi.valid = reference_sosi.valid
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
+ assert verify_sosi.sop = reference_sosi.sop
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
+ assert verify_sosi.eop = reference_sosi.eop
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
+ assert verify_sosi.data = reference_sosi.data
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
+ assert verify_sosi.channel = reference_sosi.channel
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
+ assert verify_sosi.bsn = reference_sosi.bsn
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
+ assert verify_sosi.empty = reference_sosi.empty
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
+ assert verify_sosi.sync = reference_sosi.sync
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
else -- we expect no block as there are errors
- assert verify_sosi.valid = '0' report "Wrong, valid is not '0' which is unexpected." severity ERROR;
- assert verify_sosi.sop = '0' report "Wrong, sop is not '0' which is unexpected." severity ERROR;
- assert verify_sosi.eop = '0' report "Wrong, eop is not '0' which is unexpected." severity ERROR;
+ assert verify_sosi.valid = '0'
+ report "Wrong, valid is not '0' which is unexpected."
+ severity ERROR;
+ assert verify_sosi.sop = '0'
+ report "Wrong, sop is not '0' which is unexpected."
+ severity ERROR;
+ assert verify_sosi.eop = '0'
+ report "Wrong, eop is not '0' which is unexpected."
+ severity ERROR;
end if;
end if;
end process;
@@ -232,11 +254,15 @@ begin
proc_mem_mm_bus_rd(c_mm_addr_dp_discarded_cnt, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_discarded_cnt <= TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0));
- assert c_exp_discarded_cnt = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong total discarded block count" severity ERROR;
+ assert c_exp_discarded_cnt = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong total discarded block count"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_dp_blk_cnt, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_blk_cnt <= TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0));
- assert c_exp_blk_cnt = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong total block count" severity ERROR;
+ assert c_exp_blk_cnt = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong total block count"
+ severity ERROR;
for I in 0 to g_nof_err_counts - 1 loop
v_X := 2**I * ((c_nof_blk - 1) / 2**(I + 1));
v_Y := c_nof_blk - 2 * v_X - 2**I;
@@ -253,7 +279,9 @@ begin
proc_mem_mm_bus_rd(I, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_err_cnt_arr(I) <= TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0));
- assert v_N = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong error count" severity ERROR;
+ assert v_N = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong error count"
+ severity ERROR;
end loop;
proc_common_wait_some_cycles(dp_clk, 10);
@@ -263,10 +291,14 @@ begin
proc_mem_mm_bus_rd(c_mm_addr_dp_discarded_cnt, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- assert 0 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong cleared total discarded block count" severity ERROR;
+ assert 0 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong cleared total discarded block count"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_dp_blk_cnt, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- assert 0 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong cleared total block count" severity ERROR;
+ assert 0 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0))
+ report "Wrong cleared total block count"
+ severity ERROR;
proc_common_wait_some_cycles(dp_clk, 10);
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
index 2ecc70415e..74e5171f22 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
@@ -155,37 +155,77 @@ begin
if rising_edge(clk) then
if reference_sosi.valid = '1' then
if g_expected_length = g_nof_data_per_blk then -- in sosi should be identical to out sosi
- assert verify_sosi = reference_sosi report "Unexpected difference between in / out sosi" severity ERROR;
+ assert verify_sosi = reference_sosi
+ report "Unexpected difference between in / out sosi"
+ severity ERROR;
elsif g_expected_length < g_nof_data_per_blk then -- expect an err bit to be set and the block length to be limited to g_expected_length
if reference_cnt < g_expected_length - 1 then
- assert verify_sosi = reference_sosi report "Wrong block while reference_cnt < g_expected_length-1" severity ERROR;
+ assert verify_sosi = reference_sosi
+ report "Wrong block while reference_cnt < g_expected_length-1"
+ severity ERROR;
elsif reference_cnt = g_expected_length - 1 then
- assert verify_sosi.sync = reference_sosi.sync report "Wrong sync, while reference_cnt = g_expected_length-1" severity ERROR;
- assert verify_sosi.bsn = reference_sosi.bsn report "Wrong bsn, while reference_cnt = g_expected_length-1" severity ERROR;
- assert verify_sosi.channel = reference_sosi.channel report "Wrong valid, while reference_cnt = g_expected_length-1" severity ERROR;
- assert verify_sosi.data = reference_sosi.data report "Wrong data, while reference_cnt = g_expected_length-1" severity ERROR;
- assert verify_sosi.valid = reference_sosi.valid report "Wrong valid, while reference_cnt = g_expected_length-1" severity ERROR;
- assert verify_sosi.sop = reference_sosi.sop report "Wrong sop, while reference_cnt = g_expected_length-1" severity ERROR;
- assert verify_sosi.eop = '1' report "Wrong eop, while reference_cnt = g_expected_length-1" severity ERROR;
- assert verify_sosi.err = c_exp_err report "Wrong err, while reference_cnt = g_expected_length-1" severity ERROR;
+ assert verify_sosi.sync = reference_sosi.sync
+ report "Wrong sync, while reference_cnt = g_expected_length-1"
+ severity ERROR;
+ assert verify_sosi.bsn = reference_sosi.bsn
+ report "Wrong bsn, while reference_cnt = g_expected_length-1"
+ severity ERROR;
+ assert verify_sosi.channel = reference_sosi.channel
+ report "Wrong valid, while reference_cnt = g_expected_length-1"
+ severity ERROR;
+ assert verify_sosi.data = reference_sosi.data
+ report "Wrong data, while reference_cnt = g_expected_length-1"
+ severity ERROR;
+ assert verify_sosi.valid = reference_sosi.valid
+ report "Wrong valid, while reference_cnt = g_expected_length-1"
+ severity ERROR;
+ assert verify_sosi.sop = reference_sosi.sop
+ report "Wrong sop, while reference_cnt = g_expected_length-1"
+ severity ERROR;
+ assert verify_sosi.eop = '1'
+ report "Wrong eop, while reference_cnt = g_expected_length-1"
+ severity ERROR;
+ assert verify_sosi.err = c_exp_err
+ report "Wrong err, while reference_cnt = g_expected_length-1"
+ severity ERROR;
else -- reference_cnt > g_expected_length-1
- assert verify_sosi.valid = '0' report "Wrong, valid should be '0' when reference_cnt > g_expected_length-1" severity ERROR;
+ assert verify_sosi.valid = '0'
+ report "Wrong, valid should be '0' when reference_cnt > g_expected_length-1"
+ severity ERROR;
end if;
else -- g_expected_length > g_nof_data_per_blk
-- Expected an err bit to be set at eop
if reference_cnt = g_nof_data_per_blk - 1 then
- assert verify_sosi.sync = reference_sosi.sync report "Wrong sync, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
- assert verify_sosi.bsn = reference_sosi.bsn report "Wrong bsn, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
- assert verify_sosi.channel = reference_sosi.channel report "Wrong valid, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
- assert verify_sosi.data = reference_sosi.data report "Wrong data, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
- assert verify_sosi.valid = reference_sosi.valid report "Wrong valid, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
- assert verify_sosi.sop = reference_sosi.sop report "Wrong sop, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
- assert verify_sosi.eop = reference_sosi.eop report "Wrong eop, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
- assert verify_sosi.err = c_exp_err report "Wrong err, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
+ assert verify_sosi.sync = reference_sosi.sync
+ report "Wrong sync, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
+ assert verify_sosi.bsn = reference_sosi.bsn
+ report "Wrong bsn, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
+ assert verify_sosi.channel = reference_sosi.channel
+ report "Wrong valid, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
+ assert verify_sosi.data = reference_sosi.data
+ report "Wrong data, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
+ assert verify_sosi.valid = reference_sosi.valid
+ report "Wrong valid, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
+ assert verify_sosi.sop = reference_sosi.sop
+ report "Wrong sop, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
+ assert verify_sosi.eop = reference_sosi.eop
+ report "Wrong eop, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
+ assert verify_sosi.err = c_exp_err
+ report "Wrong err, while reference_cnt = g_nof_data_per_blk-1"
+ severity ERROR;
else
- assert verify_sosi = reference_sosi report "Wrong block while g_expected_length > g_nof_data_per_blk" severity ERROR;
+ assert verify_sosi = reference_sosi
+ report "Wrong block while g_expected_length > g_nof_data_per_blk"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
index 7d5f7e3d69..6556d300e3 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
@@ -456,23 +456,33 @@ begin
if verify_sosi_en_arr(I) = '1' and out_sosi_arr_exp(I).valid = '1' then
-- Verify sosi control fields
dbg_verify_sosi_control_arr(I) <= '1';
- assert out_sosi_arr(I).sync = out_sosi_arr_exp(I).sync report "Wrong sync for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).sop = out_sosi_arr_exp(I).sop report "Wrong sop for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).eop = out_sosi_arr_exp(I).eop report "Wrong eop for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid report "Wrong valid for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).sync = out_sosi_arr_exp(I).sync
+ report "Wrong sync for output " & int_to_str(I)
+ severity ERROR;
+ assert out_sosi_arr(I).sop = out_sosi_arr_exp(I).sop
+ report "Wrong sop for output " & int_to_str(I)
+ severity ERROR;
+ assert out_sosi_arr(I).eop = out_sosi_arr_exp(I).eop
+ report "Wrong eop for output " & int_to_str(I)
+ severity ERROR;
+ assert out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid
+ report "Wrong valid for output " & int_to_str(I)
+ severity ERROR;
-- Verify data field
if stream_en_arr(I) = '1' and stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
-- verify passed on data
dbg_verify_passed_on_data_arr(I) <= '1';
- assert out_sosi_arr(I).data = out_sosi_arr_exp(I).data report "Wrong data for output stream " & int_to_str(I) & " : "
- & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
+ assert out_sosi_arr(I).data = out_sosi_arr_exp(I).data
+ report "Wrong data for output stream " & int_to_str(I) & " : "
+ & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
& int_to_str(TO_UINT(out_sosi_arr_exp(I).data)) severity ERROR;
else
-- verify lost data stream at g_disable_stream_id or g_lost_stream_id or g_lost_bsn_id
dbg_verify_replaced_data_arr(I) <= '1';
- assert TO_UINT(out_sosi_arr(I).data) = g_data_replacement_value report "Wrong replacement data for output stream " & int_to_str(I) & " : "
- & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
+ assert TO_UINT(out_sosi_arr(I).data) = g_data_replacement_value
+ report "Wrong replacement data for output stream " & int_to_str(I) & " : "
+ & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
& int_to_str(g_data_replacement_value) severity ERROR;
end if;
@@ -480,17 +490,23 @@ begin
if out_sosi_arr_exp(I).sop = '1' then
-- bsn field
dbg_verify_bsn_arr(I) <= '1';
- assert out_sosi_arr(I).bsn = out_sosi_arr_exp(I).bsn report "Wrong bsn for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).bsn = out_sosi_arr_exp(I).bsn
+ report "Wrong bsn for output " & int_to_str(I)
+ severity ERROR;
-- channel field with lost flag bit 0
if stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
-- verify no lost stream
dbg_verify_no_lost_flag_arr(I) <= '1';
- assert out_sosi_arr(I).channel = TO_DP_CHANNEL(0) report "Wrong lost flag bit in channel /= 0 for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).channel = TO_DP_CHANNEL(0)
+ report "Wrong lost flag bit in channel /= 0 for output " & int_to_str(I)
+ severity ERROR;
else
-- verify lost stream g_lost_stream_id or lost block g_lost_bsn_id
dbg_verify_lost_flag_arr(I) <= '1';
- assert out_sosi_arr(I).channel = TO_DP_CHANNEL(1) report "Wrong lost flag bit channel /= 1 for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).channel = TO_DP_CHANNEL(1)
+ report "Wrong lost flag bit channel /= 1 for output " & int_to_str(I)
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
index 2003d4327f..a2adfb4c0b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -227,23 +227,47 @@ begin
begin
-- The assert conditions must manually be set such to fit the stimuli from p_siso_stimuli
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '0' report "Wrong mon_ready_stable at sync 1" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 1" severity ERROR;
+ assert mon_ready_stable = '0'
+ report "Wrong mon_ready_stable at sync 1"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 1"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '0' report "Wrong mon_ready_stable at sync 2" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 2" severity ERROR;
+ assert mon_ready_stable = '0'
+ report "Wrong mon_ready_stable at sync 2"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 2"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 3" severity ERROR;
- assert mon_xon_stable = '1' report "Wrong mon_xon_stable at sync 3" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 3"
+ severity ERROR;
+ assert mon_xon_stable = '1'
+ report "Wrong mon_xon_stable at sync 3"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 4" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 4" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 4"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 4"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 5" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 5" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 5"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 5"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 6" severity ERROR;
- assert mon_xon_stable = '1' report "Wrong mon_xon_stable at sync 6" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 6"
+ severity ERROR;
+ assert mon_xon_stable = '1'
+ report "Wrong mon_xon_stable at sync 6"
+ severity ERROR;
wait;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
index 8f76b0058e..00dafb1884 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
@@ -231,23 +231,47 @@ begin
begin
-- The assert conditions must manually be set such to fit the stimuli from p_siso_stimuli
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '0' report "Wrong mon_ready_stable at sync 1" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 1" severity ERROR;
+ assert mon_ready_stable = '0'
+ report "Wrong mon_ready_stable at sync 1"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 1"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '0' report "Wrong mon_ready_stable at sync 2" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 2" severity ERROR;
+ assert mon_ready_stable = '0'
+ report "Wrong mon_ready_stable at sync 2"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 2"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 3" severity ERROR;
- assert mon_xon_stable = '1' report "Wrong mon_xon_stable at sync 3" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 3"
+ severity ERROR;
+ assert mon_xon_stable = '1'
+ report "Wrong mon_xon_stable at sync 3"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 4" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 4" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 4"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 4"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 5" severity ERROR;
- assert mon_xon_stable = '0' report "Wrong mon_xon_stable at sync 5" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 5"
+ severity ERROR;
+ assert mon_xon_stable = '0'
+ report "Wrong mon_xon_stable at sync 5"
+ severity ERROR;
proc_common_wait_until_hi_lo(clk, mon_sync);
- assert mon_ready_stable = '1' report "Wrong mon_ready_stable at sync 6" severity ERROR;
- assert mon_xon_stable = '1' report "Wrong mon_xon_stable at sync 6" severity ERROR;
+ assert mon_ready_stable = '1'
+ report "Wrong mon_ready_stable at sync 6"
+ severity ERROR;
+ assert mon_xon_stable = '1'
+ report "Wrong mon_xon_stable at sync 6"
+ severity ERROR;
wait;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
index d8de93d613..aafadd7f05 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -240,7 +240,9 @@ begin
end loop;
proc_common_wait_some_cycles(clk, 10);
- assert bs_starts_cnt = 1 + c_nof_repeat report "Wrong number of BSN source starts." severity ERROR;
+ assert bs_starts_cnt = 1 + c_nof_repeat
+ report "Wrong number of BSN source starts."
+ severity ERROR;
tb_end <= '1';
wait;
@@ -276,10 +278,18 @@ begin
if rising_edge(clk) then
unexpected_bs_sync <= '0';
if verify_en = '1' and bs_sosi.valid = '1' then
- assert TO_UINT(bs_sosi.bsn) = exp_grid.bsn report "Wrong bs_sosi.bsn /= exp_grid.bsn" severity ERROR;
- assert bs_sosi.sync = exp_grid.sync report "Wrong bs_sosi.sync /= exp_grid.sync" severity ERROR;
- assert bs_sosi.sop = exp_grid.sop report "Wrong bs_sosi.sop /= exp_grid.sop" severity ERROR;
- assert bs_sosi.eop = exp_grid.eop report "Wrong bs_sosi.eop /= exp_grid.eop" severity ERROR;
+ assert TO_UINT(bs_sosi.bsn) = exp_grid.bsn
+ report "Wrong bs_sosi.bsn /= exp_grid.bsn"
+ severity ERROR;
+ assert bs_sosi.sync = exp_grid.sync
+ report "Wrong bs_sosi.sync /= exp_grid.sync"
+ severity ERROR;
+ assert bs_sosi.sop = exp_grid.sop
+ report "Wrong bs_sosi.sop /= exp_grid.sop"
+ severity ERROR;
+ assert bs_sosi.eop = exp_grid.eop
+ report "Wrong bs_sosi.eop /= exp_grid.eop"
+ severity ERROR;
-- Mark error in Wave window
if bs_sosi.sync = '1' and bs_sosi.sync /= exp_grid.sync then
unexpected_bs_sync <= '1';
@@ -296,8 +306,12 @@ begin
begin
if rising_edge(clk) then
if bs_restart = '1' then
- assert bs_sosi.sync = '1' report "Unexpected bs_start while bs_sosi.sync /= 1" severity ERROR;
- assert prev_bs_valid = '0' report "Unexpected bs_start while prev_bs_valid /= 0" severity ERROR;
+ assert bs_sosi.sync = '1'
+ report "Unexpected bs_start while bs_sosi.sync /= 1"
+ severity ERROR;
+ assert prev_bs_valid = '0'
+ report "Unexpected bs_start while prev_bs_valid /= 0"
+ severity ERROR;
end if;
end if;
end process;
@@ -306,15 +320,23 @@ begin
begin
if rising_edge(clk) then
if bs_restart = '1' then
- assert bs_new_interval = '1' report "Wrong begin of bs_new_interval" severity ERROR;
+ assert bs_new_interval = '1'
+ report "Wrong begin of bs_new_interval"
+ severity ERROR;
tb_new_interval <= '1';
elsif bs_sosi.sync = '1' then
- assert bs_new_interval = '0' report "Wrong end of bs_new_interval" severity ERROR;
+ assert bs_new_interval = '0'
+ report "Wrong end of bs_new_interval"
+ severity ERROR;
tb_new_interval <= '0';
elsif tb_new_interval = '1' then
- assert bs_new_interval = '1' report "Wrong level during bs_new_interval" severity ERROR;
+ assert bs_new_interval = '1'
+ report "Wrong level during bs_new_interval"
+ severity ERROR;
else
- assert bs_new_interval = '0' report "Unexpected bs_new_interval" severity ERROR;
+ assert bs_new_interval = '0'
+ report "Unexpected bs_new_interval"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
index 5a8bde3e86..b5692167dc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
@@ -402,9 +402,13 @@ begin
begin
if rising_edge(clk) then
if expected_out_enable = '1' then
- assert out_enable = '1' report "Wrong out_enable, should be active" severity ERROR;
+ assert out_enable = '1'
+ report "Wrong out_enable, should be active"
+ severity ERROR;
elsif expected_out_enable = '0' then
- assert out_enable = '0' report "Wrong out_enable, should be inactive" severity ERROR;
+ assert out_enable = '0'
+ report "Wrong out_enable, should be inactive"
+ severity ERROR;
end if;
end if;
end process;
@@ -418,7 +422,9 @@ begin
p_verify_output : process
begin
wait until tb_end = '1';
- assert out_sop_cnt > 0 report "There was no output." severity ERROR;
+ assert out_sop_cnt > 0
+ report "There was no output."
+ severity ERROR;
wait;
end process;
@@ -445,18 +451,21 @@ begin
-- Check that out_sync is active at out_start
if out_start = '1' then
if out_sync = '0' then
- report "Missing out_sync at out_start" severity ERROR;
+ report "Missing out_sync at out_start"
+ severity ERROR;
end if;
end if;
-- Check unexpected out_start
if out_start = '1' and expecting_out_start = '0' then
- report "Unexpected out_start" severity ERROR;
+ report "Unexpected out_start"
+ severity ERROR;
end if;
-- Check that out_start is active when out_enable goes high
if out_start = '0' and out_enable = '1' and prev_out_enable = '0' then
- report "Missed out_start" severity ERROR;
+ report "Missed out_start"
+ severity ERROR;
end if;
end if;
end process;
@@ -474,7 +483,9 @@ begin
end if;
-- Verify exp_start_interval
- assert exp_start_interval = out_start_interval report "Wrong out_start_interval" severity ERROR;
+ assert exp_start_interval = out_start_interval
+ report "Wrong out_start_interval"
+ severity ERROR;
end if;
end process;
@@ -551,9 +562,11 @@ begin
v_bsn_max := TO_UINT(mon_current_input_bsn) + c_output_nof_blocks_min + 1;
assert TO_UINT(mon_output_sync_bsn) >= v_bsn_min
- report "Wrong: mon_output_sync_bsn is behind (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " < " & int_to_str(v_bsn_min) & ")" severity ERROR;
+ report "Wrong: mon_output_sync_bsn is behind (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " < " & int_to_str(v_bsn_min) & ")"
+ severity ERROR;
assert TO_UINT(mon_output_sync_bsn) <= v_bsn_max
- report "Wrong: mon_output_sync_bsn is too far ahead (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " > " & int_to_str(v_bsn_max) & ")" severity ERROR;
+ report "Wrong: mon_output_sync_bsn is too far ahead (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " > " & int_to_str(v_bsn_max) & ")"
+ severity ERROR;
--Debug report used to investigate v_bsn_min and v_bsn_max assert conditions
--REPORT int_to_str(TO_UINT(mon_output_sync_bsn)) & " : " & int_to_str(TO_UINT(mon_current_input_bsn)) SEVERITY NOTE;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
index 9506ca762c..7f3a7efd80 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
@@ -136,9 +136,11 @@ begin
if new_crc = '1' then
--IF g_data_w = 28 AND g_crc_w = 28 AND c_nof_data_per_blk = 9 THEN
if blk_crc = exp_crc_28 then
- report "OK CRC value." severity NOTE;
+ report "OK CRC value."
+ severity NOTE;
else
- report "Wrong CRC value." severity ERROR;
+ report "Wrong CRC value."
+ severity ERROR;
end if;
--END IF;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
index 3d341e7d60..820f20ed96 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
@@ -204,12 +204,18 @@ begin
period <= c_period; -- to view c_period in wave window
if rising_edge(clk) then
if count_src_out_arr(g_nof_counters - 1).valid = '1' then
- assert v_cnt = TO_UINT(src_out.data) report "Wrong cnt at valid : " & int_to_str(v_cnt) severity ERROR;
+ assert v_cnt = TO_UINT(src_out.data)
+ report "Wrong cnt at valid : " & int_to_str(v_cnt)
+ severity ERROR;
if count_src_out_arr(g_nof_counters - 1).sop = '1' then
- assert v_cnt mod c_period = 0 report "Wrong cnt at sop : " & int_to_str(v_cnt) severity ERROR;
+ assert v_cnt mod c_period = 0
+ report "Wrong cnt at sop : " & int_to_str(v_cnt)
+ severity ERROR;
end if;
if count_src_out_arr(g_nof_counters - 1).eop = '1' then
- assert v_cnt mod c_period = c_period - 1 report "Wrong cnt at eop : " & int_to_str(v_cnt) severity ERROR;
+ assert v_cnt mod c_period = c_period - 1
+ report "Wrong cnt at eop : " & int_to_str(v_cnt)
+ severity ERROR;
end if;
v_cnt := v_cnt + 1;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
index 0212988e86..e35ef3b40b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
@@ -172,7 +172,8 @@ architecture tb of tb_dp_counter_func is
if tb_start_en = '1' then
for I in 0 to g_nof_counters - 1 loop
assert tb_count_arr(I) = g_range_start(I)
- report "DP : Wrong start of counter " & int_to_str(I) severity ERROR;
+ report "DP : Wrong start of counter " & int_to_str(I)
+ severity ERROR;
end loop;
end if;
@@ -180,7 +181,8 @@ architecture tb of tb_dp_counter_func is
if tb_stopped_en = '1' then
for I in 0 to g_nof_counters - 1 loop
assert tb_count_arr(I) = TO_UINT(dp_counter_func_count_src_out_arr(I).data(c_max_count_w - 1 downto 0))
- report "DP : Counter " & int_to_str(I) & " not stopped after dp_counter_func_count_en <= 0" severity ERROR;
+ report "DP : Counter " & int_to_str(I) & " not stopped after dp_counter_func_count_en <= 0"
+ severity ERROR;
end loop;
end if;
@@ -189,11 +191,13 @@ architecture tb of tb_dp_counter_func is
-- all counters except the last one should hold the start value
for I in 0 to g_nof_counters - 2 loop
assert tb_count_arr(I) = g_range_start(I)
- report "DP : Wrong carryover, counter:" & int_to_str(I) severity ERROR;
+ report "DP : Wrong carryover, counter:" & int_to_str(I)
+ severity ERROR;
end loop;
-- the last counter should hold the start value + step
assert tb_count_arr(g_nof_counters - 1) = g_range_start(g_nof_counters - 1) + g_range_step(g_nof_counters - 1)
- report "DP : Wrong carryover, counter:" & int_to_str(g_nof_counters - 1) severity ERROR;
+ report "DP : Wrong carryover, counter:" & int_to_str(g_nof_counters - 1)
+ severity ERROR;
end if;
-- check counter values on sop and eop
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
index 4c0d3633c2..1a23af3abe 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
@@ -209,12 +209,18 @@ begin
period <= c_period; -- to view c_period in wave window
if rising_edge(clk) then
if count_src_out_arr(g_nof_counters - 1).valid = '1' then
- assert v_cnt = TO_UINT(src_out.data) report "Wrong cnt at valid : " & int_to_str(v_cnt) severity ERROR;
+ assert v_cnt = TO_UINT(src_out.data)
+ report "Wrong cnt at valid : " & int_to_str(v_cnt)
+ severity ERROR;
if count_src_out_arr(g_nof_counters - 1).sop = '1' then
- assert v_cnt mod c_period = 0 report "Wrong cnt at sop : " & int_to_str(v_cnt) severity ERROR;
+ assert v_cnt mod c_period = 0
+ report "Wrong cnt at sop : " & int_to_str(v_cnt)
+ severity ERROR;
end if;
if count_src_out_arr(g_nof_counters - 1).eop = '1' then
- assert v_cnt mod c_period = c_period - 1 report "Wrong cnt at eop : " & int_to_str(v_cnt) severity ERROR;
+ assert v_cnt mod c_period = c_period - 1
+ report "Wrong cnt at eop : " & int_to_str(v_cnt)
+ severity ERROR;
end if;
v_cnt := v_cnt + 1;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
index d6ad771c2a..4156d49eaa 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
@@ -159,7 +159,9 @@ begin
proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end generate;
- assert c_verify_data_en = true report "proc_dp_verify_data() can not verify the data if it is not continuous" severity WARNING;
+ assert c_verify_data_en = true
+ report "proc_dp_verify_data() can not verify the data if it is not continuous"
+ severity WARNING;
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index aeceefb25f..16ee99c83d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -200,7 +200,9 @@ begin
proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end generate;
- assert c_verify_data_en = true report "proc_dp_verify_data() can not verify the data if it is not continuous" severity WARNING;
+ assert c_verify_data_en = true
+ report "proc_dp_verify_data() can not verify the data if it is not continuous"
+ severity WARNING;
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
index bd1ccdaaa0..915b9babdc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -165,7 +165,9 @@ begin
proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end generate;
- assert c_verify_data_en = true report "proc_dp_verify_data() can not verify the data if it is not continuous" severity WARNING;
+ assert c_verify_data_en = true
+ report "proc_dp_verify_data() can not verify the data if it is not continuous"
+ severity WARNING;
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
@@ -201,12 +203,16 @@ begin
-- Check fill level at first output
proc_common_wait_until_high(clk, out_val);
- assert unsigned(rd_usedw) = unsigned(rd_fill_32b) report "Usedw is not equal to fill level at start" severity ERROR;
+ assert unsigned(rd_usedw) = unsigned(rd_fill_32b)
+ report "Usedw is not equal to fill level at start"
+ severity ERROR;
-- Check fill level after last output (account for block length given by c_tx_period_sop)
proc_common_wait_until_high(clk, verify_done);
proc_common_wait_some_cycles(clk, g_dut_fifo_size);
- assert unsigned(rd_usedw) >= unsigned(rd_fill_32b) - c_tx_period_sop report "Usedw does not match fill level at end" severity ERROR;
+ assert unsigned(rd_usedw) >= unsigned(rd_fill_32b) - c_tx_period_sop
+ report "Usedw does not match fill level at end"
+ severity ERROR;
end if;
proc_common_wait_until_high(clk, tb_done);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
index 141127e58c..ae9aeaf325 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
@@ -262,10 +262,14 @@ begin
begin
if rising_edge(clk) then
-- Verify that FIFO never runs full
- assert fifo_full = '0' report "TB : FIFO full must not occur" severity ERROR;
+ assert fifo_full = '0'
+ report "TB : FIFO full must not occur"
+ severity ERROR;
-- Verify that the read data is in not too much behind the write data
- assert unsigned(mm_wrdata) <= unsigned(mm_rddata) + c_fifo_size report "TB : Too large difference value" severity ERROR;
+ assert unsigned(mm_wrdata) <= unsigned(mm_rddata) + c_fifo_size
+ report "TB : Too large difference value"
+ severity ERROR;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
index bb5e1dce66..44772baf42 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
@@ -222,29 +222,37 @@ begin
if verify_en = '1' then
if reg_mode_flush_en = '1' then
if reg_m.src_out_sync = '1' then
- report "DP : Wrong sync, should have been flushed" severity ERROR;
+ report "DP : Wrong sync, should have been flushed"
+ severity ERROR;
end if;
if reg_m.src_out_valid = '1' then
- report "DP : Wrong valid, should have been flushed" severity ERROR;
+ report "DP : Wrong valid, should have been flushed"
+ severity ERROR;
end if;
if reg_m.src_out_sop = '1' then
- report "DP : Wrong sop, should have been flushed" severity ERROR;
+ report "DP : Wrong sop, should have been flushed"
+ severity ERROR;
end if;
if reg_m.src_out_eop = '1' then
- report "DP : Wrong eop, should have been flushed" severity ERROR;
+ report "DP : Wrong eop, should have been flushed"
+ severity ERROR;
end if;
else
if reg_m.snk_in_sync /= reg_m.src_out_sync then
- report "DP : Missing sync, should not have been flushed" severity ERROR;
+ report "DP : Missing sync, should not have been flushed"
+ severity ERROR;
end if;
if reg_m.snk_in_valid /= reg_m.src_out_valid then
- report "DP : Missing valid, should not have been flushed" severity ERROR;
+ report "DP : Missing valid, should not have been flushed"
+ severity ERROR;
end if;
if reg_m.snk_in_sop /= reg_m.src_out_sop then
- report "DP : Missing sop, should not have been flushed" severity ERROR;
+ report "DP : Missing sop, should not have been flushed"
+ severity ERROR;
end if;
if reg_m.snk_in_eop /= reg_m.src_out_eop then
- report "DP : Missing eop, should not have been flushed" severity ERROR;
+ report "DP : Missing eop, should not have been flushed"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
index 8b0d02b22b..d6cf2dee2b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
@@ -281,7 +281,8 @@ begin
state <= s_request;
end if;
when others => -- s_err
- report "Frame with valid data but no sof" severity WARNING;
+ report "Frame with valid data but no sof"
+ severity WARNING;
state <= s_request;
end case;
wait until rising_edge(clk);
@@ -294,7 +295,8 @@ begin
if out_val = '1' then
prev_out_data <= out_data;
if verify_en = '1' and unsigned(out_data) /= unsigned(prev_out_data) + 1 then
- report "Wrong out_data count" severity ERROR;
+ report "Wrong out_data count"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
index 3030dbaa28..54a0d0dceb 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
@@ -416,7 +416,8 @@ begin
expected_dat <= 0;
if mark_out_data = '1' then
if unsigned(lane_tx_dat) /= expected_dat then
- report "Scheduler out_dat error" severity FAILURE;
+ report "Scheduler out_dat error"
+ severity FAILURE;
end if;
expected_dat <= expected_dat + 1;
end if;
@@ -431,13 +432,15 @@ begin
elsif rising_edge(clk) then
if mark_out_fsn_x = '1' then
if unsigned(lane_tx_dat) /= expected_fsn_x then
- report "Scheduler crosslet out_fsn error" severity FAILURE;
+ report "Scheduler crosslet out_fsn error"
+ severity FAILURE;
end if;
proc_cnt(c_fsn_max, rst, expected_fsn_x); -- increment for next packet
end if;
if mark_out_fsn_b = '1' then
if unsigned(lane_tx_dat) /= expected_fsn_b then
- report "Scheduler beamlet out_fsn error" severity FAILURE;
+ report "Scheduler beamlet out_fsn error"
+ severity FAILURE;
end if;
proc_cnt(c_fsn_max, rst, expected_fsn_b); -- increment for next packet
end if;
@@ -450,12 +453,14 @@ begin
if mark_out_frame = '1' then
if lane_tx_val /= '1' then
if c_dut_fifo_rl = 1 then
- report "Scheduler out_val missing error" severity FAILURE;
+ report "Scheduler out_val missing error"
+ severity FAILURE;
end if;
end if;
else
if lane_tx_val /= '0' then
- report "Scheduler out_val unexpected error" severity FAILURE;
+ report "Scheduler out_val unexpected error"
+ severity FAILURE;
end if;
end if;
end if;
@@ -466,11 +471,13 @@ begin
if rising_edge(clk) then
if mark_out_eof = '1' then
if lane_tx_eof /= '1' then
- report "Scheduler out_eof missing error" severity FAILURE;
+ report "Scheduler out_eof missing error"
+ severity FAILURE;
end if;
else
if lane_tx_eof /= '0' then
- report "Scheduler out_eof unexpected error" severity FAILURE;
+ report "Scheduler out_eof unexpected error"
+ severity FAILURE;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index 41811773fe..cbac338cde 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -535,9 +535,13 @@ begin
tx_hdr_word <= v_word;
-- Verify expected word
if c_use_shortened_header then
- assert c_expected_tx_hdr_word_arr_shortened(I) = v_word report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_shortened(I)) severity ERROR;
+ assert c_expected_tx_hdr_word_arr_shortened(I) = v_word
+ report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_shortened(I))
+ severity ERROR;
else
- assert c_expected_tx_hdr_word_arr_default(I) = v_word report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_default(I)) severity ERROR;
+ assert c_expected_tx_hdr_word_arr_default(I) = v_word
+ report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_default(I))
+ severity ERROR;
end if;
end loop;
print_str("", g_print_en);
@@ -631,9 +635,13 @@ begin
rx_hdr_word <= v_word;
-- Verify expected word
if c_use_shortened_header then
- assert v_word = c_expected_rx_hdr_word_arr_shortened(I) report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_shortened(I)) severity ERROR;
+ assert v_word = c_expected_rx_hdr_word_arr_shortened(I)
+ report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_shortened(I))
+ severity ERROR;
else
- assert v_word = c_expected_rx_hdr_word_arr_default(I) report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_default(I)) severity ERROR;
+ assert v_word = c_expected_rx_hdr_word_arr_default(I)
+ report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_default(I))
+ severity ERROR;
end if;
end loop;
print_str("", g_print_en);
@@ -648,9 +656,13 @@ begin
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
rx_hdr_word <= v_word; -- View word in wave window
if c_use_shortened_header then
- assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_shortened(0), 1) report "Unexpected dp_bsn from MM" severity ERROR;
+ assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_shortened(0), 1)
+ report "Unexpected dp_bsn from MM"
+ severity ERROR;
else
- assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_default(0), 1) report "Unexpected dp_bsn from MM" severity ERROR;
+ assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_default(0), 1)
+ report "Unexpected dp_bsn from MM"
+ severity ERROR;
end if;
-- dp_sync
if c_use_shortened_header then
@@ -661,7 +673,9 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
rx_hdr_word <= v_word; -- View word in wave window
- assert v_word = TO_UVEC(0, 32) report "Unexpected dp_sync from MM" severity ERROR;
+ assert v_word = TO_UVEC(0, 32)
+ report "Unexpected dp_sync from MM"
+ severity ERROR;
wait;
end process;
@@ -674,11 +688,17 @@ begin
prev_verify_snk_in_data <= verify_snk_in.data(g_data_w - 1 downto 0);
v_data := TO_UINT(verify_snk_in.data) - c_data_init;
if verify_snk_in.sop = '1' then
- assert v_data mod g_pkt_len = 0 report "Wrong decoded data at sop." severity ERROR;
+ assert v_data mod g_pkt_len = 0
+ report "Wrong decoded data at sop."
+ severity ERROR;
elsif verify_snk_in.eop = '1' then
- assert v_data mod g_pkt_len = g_pkt_len - 1 report "Wrong decoded data at eop." severity ERROR;
+ assert v_data mod g_pkt_len = g_pkt_len - 1
+ report "Wrong decoded data at eop."
+ severity ERROR;
elsif verify_snk_in.valid = '1' then
- assert v_data = TO_UINT(prev_verify_snk_in_data) - c_data_init + 1 report "Wrong decoded data at valid." severity ERROR;
+ assert v_data = TO_UINT(prev_verify_snk_in_data) - c_data_init + 1
+ report "Wrong decoded data at valid."
+ severity ERROR;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index 2adb0cb2d7..3df6e561d7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -275,9 +275,13 @@ begin
-- verify err field for merged packet with input bsn error
if verify_snk_in.sop = '1' then
if merged_pkt_cnt = c_exp_err_at_pkt_index + 1 and g_bsn_increment > 0 then
- assert merged_pkt_err = '1' report "Unexpected sosi.err = 0" severity ERROR;
+ assert merged_pkt_err = '1'
+ report "Unexpected sosi.err = 0"
+ severity ERROR;
else
- assert merged_pkt_err = '0' report "Unexpected sosi.err = 1" severity ERROR;
+ assert merged_pkt_err = '0'
+ report "Unexpected sosi.err = 1"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
index 7046fe0e48..13297f3804 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
@@ -183,7 +183,9 @@ begin
prev_rcv_dat);
-- Verify the data path output CRC (avoid error message at initialisation)
- assert NOW = 0 ps or rcv_err = '0' report "rcv_err = '1' indicating CRC error" severity ERROR;
+ assert NOW = 0 ps or rcv_err = '0'
+ report "rcv_err = '1' indicating CRC error"
+ severity ERROR;
------------------------------------------------------------------------------
-- TRANSMITTER
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
index 6353df4b08..7b47af5b42 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
@@ -1783,10 +1783,12 @@ package body tb_dp_pkg is
if rising_edge(clk) then
if en = '1' then
if mode = e_equal and unsigned(res) /= unsigned(exp) then
- report "DP : Wrong " & c_str & " result value" severity ERROR;
+ report "DP : Wrong " & c_str & " result value"
+ severity ERROR;
end if;
if mode = e_at_least and unsigned(res) < unsigned(exp) then
- report "DP : Wrong " & c_str & " result value too small" severity ERROR;
+ report "DP : Wrong " & c_str & " result value too small"
+ severity ERROR;
end if;
end if;
end if;
@@ -1810,7 +1812,8 @@ package body tb_dp_pkg is
if rising_edge(clk) then
if en = '1' then
if res /= exp then
- report "DP : Wrong " & c_str & " result value" severity ERROR;
+ report "DP : Wrong " & c_str & " result value"
+ severity ERROR;
end if;
end if;
end if;
@@ -1869,7 +1872,9 @@ package body tb_dp_pkg is
verify_en <= '1';
end if;
if verify_en = '1' then
- assert unsigned(out_bsn) = unsigned(prev_out_bsn_global) + c_global_bsn_increment report "DP : Wrong BSN increment" severity ERROR;
+ assert unsigned(out_bsn) = unsigned(prev_out_bsn_global) + c_global_bsn_increment
+ report "DP : Wrong BSN increment"
+ severity ERROR;
end if;
else
------------------------------------------------------------------
@@ -1891,14 +1896,24 @@ package body tb_dp_pkg is
if verify_en = '1' then
if out_sync = '1' then
if unsigned(out_bsn) /= unsigned(prev_out_bsn_global) then
- assert cnt_replicated_global_bsn = c_nof_replicated_global_bsn - 1 report "DP : Wrong number of replicated global BSN" severity ERROR;
- assert unsigned(out_bsn) = unsigned(prev_out_bsn_global) + c_global_bsn_increment report "DP : Wrong global BSN increment" severity ERROR;
+ assert cnt_replicated_global_bsn = c_nof_replicated_global_bsn - 1
+ report "DP : Wrong number of replicated global BSN"
+ severity ERROR;
+ assert unsigned(out_bsn) = unsigned(prev_out_bsn_global) + c_global_bsn_increment
+ report "DP : Wrong global BSN increment"
+ severity ERROR;
else
- assert unsigned(out_bsn) = unsigned(prev_out_bsn_global) report "DP : Wrong replicated global BSN" severity ERROR;
+ assert unsigned(out_bsn) = unsigned(prev_out_bsn_global)
+ report "DP : Wrong replicated global BSN"
+ severity ERROR;
end if;
- assert unsigned(prev_out_bsn_local) = c_block_per_sync - 1 report "DP : Wrong last local BSN in sync interval" severity ERROR;
+ assert unsigned(prev_out_bsn_local) = c_block_per_sync - 1
+ report "DP : Wrong last local BSN in sync interval"
+ severity ERROR;
else
- assert unsigned(out_bsn) = unsigned(prev_out_bsn_local) + 1 report "DP : Wrong local BSN increment" severity ERROR;
+ assert unsigned(out_bsn) = unsigned(prev_out_bsn_local) + 1
+ report "DP : Wrong local BSN increment"
+ severity ERROR;
end if;
end if;
end if;
@@ -1948,8 +1963,8 @@ package body tb_dp_pkg is
unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap2 and
unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap - c_out_data_max then
report "DP : Wrong out_data " & c_str & " count (" &
- natural'image(to_uint(out_data)) & ", " &
- natural'image(to_uint(prev_out_data)) & ")"
+ natural'image(to_uint(out_data)) & ", " &
+ natural'image(to_uint(prev_out_data)) & ")"
severity ERROR;
end if;
end if;
@@ -2130,12 +2145,14 @@ package body tb_dp_pkg is
end loop;
if out_eop = '0' then
if unsigned(out_data) /= unsigned(v_data) then
- report "DP : Wrong out_data symbols count" severity ERROR;
+ report "DP : Wrong out_data symbols count"
+ severity ERROR;
end if;
else
v_empty := TO_UINT(out_empty(c_empty_w - 1 downto 0));
if unsigned(out_data(c_data_w - 1 downto v_empty * c_symbol_w)) /= unsigned(v_data(c_data_w - 1 downto v_empty * c_symbol_w)) then
- report "DP : Wrong out_data symbols count at eop" severity ERROR;
+ report "DP : Wrong out_data symbols count at eop"
+ severity ERROR;
end if;
if v_empty > 0 then
-- adjust prev_out_data for potentially undefined empty symbols in out_data
@@ -2197,7 +2214,8 @@ package body tb_dp_pkg is
-- verify out_data from eop-n to eop-2 and from eop+1 to eop+n, n>2
v_ref_data := INCR_UVEC(out_data_2, 1);
if unsigned(out_data_1) /= unsigned(v_ref_data) then
- report "DP : Wrong out_data count" severity ERROR;
+ report "DP : Wrong out_data count"
+ severity ERROR;
end if;
else
-- the empty and crc replace affect data at eop_1 and eop, so need to check data from eop-2 to eop-1 to eop to eop+1
@@ -2212,7 +2230,8 @@ package body tb_dp_pkg is
when others => null;
end case;
if unsigned(out_data) /= unsigned(v_empty_data) then
- report "DP : Wrong out_data count at eop" severity ERROR;
+ report "DP : Wrong out_data count at eop"
+ severity ERROR;
end if;
elsif out_eop_1 = '1' then
-- verify out_data from eop-2 to eop-1
@@ -2225,12 +2244,14 @@ package body tb_dp_pkg is
when others => null;
end case;
if unsigned(out_data_2) /= unsigned(v_empty_data) then
- report "DP : Wrong out_data count at eop-1" severity ERROR;
+ report "DP : Wrong out_data count at eop-1"
+ severity ERROR;
end if;
-- verify out_data from eop-2 to eop+1
v_ref_data := INCR_UVEC(out_data_3, 3);
if unsigned(out_data) /= unsigned(v_ref_data) then
- report "DP : Wrong out_data count at eop+1" severity ERROR;
+ report "DP : Wrong out_data count at eop+1"
+ severity ERROR;
end if;
end if;
end if;
@@ -2255,22 +2276,27 @@ package body tb_dp_pkg is
if verify_en = '1' then
if c_str = "bsn" then
if unsigned(c_exp_data(c_dp_bsn_w - 1 downto 0)) /= unsigned(res_data(c_dp_bsn_w - 1 downto 0)) then
- report "DP : Wrong sosi.bsn value" severity ERROR;
+ report "DP : Wrong sosi.bsn value"
+ severity ERROR;
end if;
elsif c_str = "empty" then
if unsigned(c_exp_data(c_dp_empty_w - 1 downto 0)) /= unsigned(res_data(c_dp_empty_w - 1 downto 0)) then
- report "DP : Wrong sosi.empty value" severity ERROR;
+ report "DP : Wrong sosi.empty value"
+ severity ERROR;
end if;
elsif c_str = "channel" then
if unsigned(c_exp_data(c_dp_channel_user_w - 1 downto 0)) /= unsigned(res_data(c_dp_channel_user_w - 1 downto 0)) then
- report "DP : Wrong sosi.channel value" severity ERROR;
+ report "DP : Wrong sosi.channel value"
+ severity ERROR;
end if;
elsif c_str = "error" then
if unsigned(c_exp_data(c_dp_error_w - 1 downto 0)) /= unsigned(res_data(c_dp_error_w - 1 downto 0)) then
- report "DP : Wrong sosi.error value" severity ERROR;
+ report "DP : Wrong sosi.error value"
+ severity ERROR;
end if;
else
- report "proc_dp_verify_other_sosi : Unknown sosi." & c_str & "field" severity FAILURE;
+ report "proc_dp_verify_other_sosi : Unknown sosi." & c_str & "field"
+ severity FAILURE;
end if;
end if;
end if;
@@ -2294,56 +2320,68 @@ package body tb_dp_pkg is
-- sosi ctrl fields
if c_str = "sync" then
if dut_sosi.sync /= exp_sosi.sync then
- report "DP : Wrong dut_sosi.sync (" & sl_to_str(dut_sosi.sync) & " /= " & sl_to_str(exp_sosi.sync) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.sync (" & sl_to_str(dut_sosi.sync) & " /= " & sl_to_str(exp_sosi.sync) & ")"
+ severity ERROR;
end if;
elsif c_str = "sop" then
if dut_sosi.sop /= exp_sosi.sop then
- report "DP : Wrong dut_sosi.sop (" & sl_to_str(dut_sosi.sop) & " /= " & sl_to_str(exp_sosi.sop) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.sop (" & sl_to_str(dut_sosi.sop) & " /= " & sl_to_str(exp_sosi.sop) & ")"
+ severity ERROR;
end if;
elsif c_str = "eop" then
if dut_sosi.eop /= exp_sosi.eop then
- report "DP : Wrong dut_sosi.eop (" & sl_to_str(dut_sosi.eop) & " /= " & sl_to_str(exp_sosi.eop) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.eop (" & sl_to_str(dut_sosi.eop) & " /= " & sl_to_str(exp_sosi.eop) & ")"
+ severity ERROR;
end if;
elsif c_str = "valid" then
if dut_sosi.valid /= exp_sosi.valid then
- report "DP : Wrong dut_sosi.valid (" & sl_to_str(dut_sosi.valid) & " /= " & sl_to_str(exp_sosi.valid) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.valid (" & sl_to_str(dut_sosi.valid) & " /= " & sl_to_str(exp_sosi.valid) & ")"
+ severity ERROR;
end if;
-- sosi info fields
elsif c_str = "bsn" then
if dut_sosi.bsn /= exp_sosi.bsn then
- report "DP : Wrong dut_sosi.bsn (" & int_to_str(dut_sosi.bsn) & " /= " & int_to_str(exp_sosi.bsn) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.bsn (" & int_to_str(dut_sosi.bsn) & " /= " & int_to_str(exp_sosi.bsn) & ")"
+ severity ERROR;
end if;
elsif c_str = "empty" then
if dut_sosi.empty /= exp_sosi.empty then
- report "DP : Wrong dut_sosi.empty (" & int_to_str(dut_sosi.empty) & " /= " & int_to_str(exp_sosi.empty) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.empty (" & int_to_str(dut_sosi.empty) & " /= " & int_to_str(exp_sosi.empty) & ")"
+ severity ERROR;
end if;
elsif c_str = "channel" then
if dut_sosi.channel /= exp_sosi.channel then
- report "DP : Wrong dut_sosi.channel (" & int_to_str(dut_sosi.channel) & " /= " & int_to_str(exp_sosi.channel) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.channel (" & int_to_str(dut_sosi.channel) & " /= " & int_to_str(exp_sosi.channel) & ")"
+ severity ERROR;
end if;
elsif c_str = "err" then
if dut_sosi.err /= exp_sosi.err then
- report "DP : Wrong dut_sosi.err (" & int_to_str(dut_sosi.err) & " /= " & int_to_str(exp_sosi.err) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.err (" & int_to_str(dut_sosi.err) & " /= " & int_to_str(exp_sosi.err) & ")"
+ severity ERROR;
end if;
-- sosi data fields
elsif c_str = "data" then
if dut_sosi.data /= exp_sosi.data then
- report "DP : Wrong dut_sosi.data (" & int_to_str(dut_sosi.data) & " /= " & int_to_str(exp_sosi.data) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.data (" & int_to_str(dut_sosi.data) & " /= " & int_to_str(exp_sosi.data) & ")"
+ severity ERROR;
end if;
elsif c_str = "re" then
if dut_sosi.re /= exp_sosi.re then
- report "DP : Wrong dut_sosi.re (" & int_to_str(dut_sosi.re) & " /= " & int_to_str(exp_sosi.re) & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.re (" & int_to_str(dut_sosi.re) & " /= " & int_to_str(exp_sosi.re) & ")"
+ severity ERROR;
end if;
elsif c_str = "im" then
if dut_sosi.im /= exp_sosi.im then
- report "DP : Wrong dut_sosi.im (" & int_to_str(dut_sosi.im) & " /= " & int_to_str(exp_sosi.im) & ")" & ")" severity ERROR;
+ report "DP : Wrong dut_sosi.im (" & int_to_str(dut_sosi.im) & " /= " & int_to_str(exp_sosi.im) & ")" & ")"
+ severity ERROR;
end if;
-- unknown sosi field
else
- report "proc_dp_verify_sosi_equal : Unknown sosi." & c_str & "field" severity FAILURE;
+ report "proc_dp_verify_sosi_equal : Unknown sosi." & c_str & "field"
+ severity FAILURE;
end if;
end if;
end if;
@@ -2353,24 +2391,46 @@ package body tb_dp_pkg is
signal dut_sosi : in t_dp_sosi;
signal exp_sosi : in t_dp_sosi) is
begin
- assert dut_sosi.sync = exp_sosi.sync report "Wrong dut_sosi.sync" severity ERROR;
- assert dut_sosi.sop = exp_sosi.sop report "Wrong dut_sosi.sop" severity ERROR;
- assert dut_sosi.eop = exp_sosi.eop report "Wrong dut_sosi.eop" severity ERROR;
- assert dut_sosi.valid = exp_sosi.valid report "Wrong dut_sosi.valid" severity ERROR;
+ assert dut_sosi.sync = exp_sosi.sync
+ report "Wrong dut_sosi.sync"
+ severity ERROR;
+ assert dut_sosi.sop = exp_sosi.sop
+ report "Wrong dut_sosi.sop"
+ severity ERROR;
+ assert dut_sosi.eop = exp_sosi.eop
+ report "Wrong dut_sosi.eop"
+ severity ERROR;
+ assert dut_sosi.valid = exp_sosi.valid
+ report "Wrong dut_sosi.valid"
+ severity ERROR;
if exp_sosi.sop = '1' then
- assert dut_sosi.bsn = exp_sosi.bsn report "Wrong dut_sosi.bsn" severity ERROR;
- assert dut_sosi.channel = exp_sosi.channel report "Wrong dut_sosi.channel" severity ERROR;
+ assert dut_sosi.bsn = exp_sosi.bsn
+ report "Wrong dut_sosi.bsn"
+ severity ERROR;
+ assert dut_sosi.channel = exp_sosi.channel
+ report "Wrong dut_sosi.channel"
+ severity ERROR;
end if;
if exp_sosi.eop = '1' then
- assert dut_sosi.empty = exp_sosi.empty report "Wrong dut_sosi.empty" severity ERROR;
- assert dut_sosi.err = exp_sosi.err report "Wrong dut_sosi.err" severity ERROR;
+ assert dut_sosi.empty = exp_sosi.empty
+ report "Wrong dut_sosi.empty"
+ severity ERROR;
+ assert dut_sosi.err = exp_sosi.err
+ report "Wrong dut_sosi.err"
+ severity ERROR;
end if;
if exp_sosi.valid = '1' then
if c_use_complex then
- assert dut_sosi.re = exp_sosi.re report "Wrong dut_sosi.re" severity ERROR;
- assert dut_sosi.im = exp_sosi.im report "Wrong dut_sosi.im" severity ERROR;
+ assert dut_sosi.re = exp_sosi.re
+ report "Wrong dut_sosi.re"
+ severity ERROR;
+ assert dut_sosi.im = exp_sosi.im
+ report "Wrong dut_sosi.im"
+ severity ERROR;
else
- assert dut_sosi.data = exp_sosi.data report "Wrong dut_sosi.data" severity ERROR;
+ assert dut_sosi.data = exp_sosi.data
+ report "Wrong dut_sosi.data"
+ severity ERROR;
end if;
end if;
end proc_dp_verify_sosi_equal;
@@ -2397,7 +2457,8 @@ package body tb_dp_pkg is
end if;
if verify_en = '1' and out_val = '1' then
if prev_out_ready(c_ready_latency - 1) /= '1' then
- report "DP : Wrong ready latency between out_ready and out_val" severity ERROR;
+ report "DP : Wrong ready latency between out_ready and out_val"
+ severity ERROR;
end if;
end if;
end if;
@@ -2418,7 +2479,8 @@ package body tb_dp_pkg is
prev_out_ready <= out_ready;
if verify_en = '1' and out_val = '1' then
if prev_out_ready /= '1' then
- report "DP : Wrong ready latency between out_ready and out_val" severity ERROR;
+ report "DP : Wrong ready latency between out_ready and out_val"
+ severity ERROR;
end if;
end if;
end if;
@@ -2440,14 +2502,17 @@ package body tb_dp_pkg is
-- Check for unexpected sync
if sync = '1' then
assert expected_sync = '1'
- report "Error: Unexpected sync at BSN" severity ERROR;
+ report "Error: Unexpected sync at BSN"
+ severity ERROR;
assert sop = '1'
- report "Error: Unexpected sync at inactive sop" severity ERROR;
+ report "Error: Unexpected sync at inactive sop"
+ severity ERROR;
end if;
-- Check for missing sync
if sop = '1' and expected_sync = '1' then
assert sync = '1'
- report "Error: Missing sync" severity ERROR;
+ report "Error: Missing sync"
+ severity ERROR;
end if;
end if;
end if;
@@ -2466,14 +2531,17 @@ package body tb_dp_pkg is
-- Check for unexpected sync
if sync = '1' then
assert expected_sync = '1'
- report "Error: Unexpected sync at BSN (" & int_to_str(bsn) & " /= " & int_to_str(expected_bsn) & ")" severity ERROR;
+ report "Error: Unexpected sync at BSN (" & int_to_str(bsn) & " /= " & int_to_str(expected_bsn) & ")"
+ severity ERROR;
assert sop = '1'
- report "Error: Unexpected sync at inactive sop" severity ERROR;
+ report "Error: Unexpected sync at inactive sop"
+ severity ERROR;
end if;
-- Check for missing sync
if sop = '1' and expected_sync = '1' then
assert sync = '1'
- report "Error: Missing sync" severity ERROR;
+ report "Error: Missing sync"
+ severity ERROR;
end if;
end if;
end if;
@@ -2632,18 +2700,21 @@ package body tb_dp_pkg is
if out_sop = '1' then
hold_sop <= '1';
if hold_sop = '1' then
- report "DP : Unexpected sop without eop" severity ERROR;
+ report "DP : Unexpected sop without eop"
+ severity ERROR;
end if;
end if;
if out_eop = '1' then
hold_sop <= '0';
if hold_sop = '0' and out_sop = '0' then
- report "DP : Unexpected eop without sop" severity ERROR;
+ report "DP : Unexpected eop without sop"
+ severity ERROR;
end if;
end if;
-- out_val='1'
if c_verify_valid = true and out_sop = '0' and hold_sop = '0' then
- report "DP : Unexpected valid in gap between eop and sop" severity ERROR;
+ report "DP : Unexpected valid in gap between eop and sop"
+ severity ERROR;
end if;
end if;
end if;
@@ -2691,7 +2762,8 @@ package body tb_dp_pkg is
elsif out_eop = '1' then
cnt_size <= 0;
if cnt_size /= alt_size-1 and cnt_size /= exp_size-1 then
- report "DP : Unexpected block size" severity ERROR;
+ report "DP : Unexpected block size"
+ severity ERROR;
end if;
else
cnt_size <= cnt_size+1;
@@ -2751,7 +2823,8 @@ package body tb_dp_pkg is
elsif in_sop = '1' then
out_gap <= '0';
elsif in_val = '1' and out_gap = '1' then
- report "DP : Wrong valid in gap between eop and sop" severity ERROR;
+ report "DP : Wrong valid in gap between eop and sop"
+ severity ERROR;
end if;
end if;
end proc_dp_verify_gap_invalid;
@@ -2774,11 +2847,13 @@ package body tb_dp_pkg is
v_data := TO_UINT(data);
if ((v_data - c_offset) mod c_period) = 0 then
if valid = '1' and ctrl /= '1' then
- report "DP : Wrong data control, missing " & c_str severity ERROR;
+ report "DP : Wrong data control, missing " & c_str
+ severity ERROR;
end if;
else
if ctrl = '1' then
- report "DP : Wrong data control, unexpected " & c_str severity ERROR;
+ report "DP : Wrong data control, unexpected " & c_str
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
index 163c4635bf..f932d26f10 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
@@ -294,7 +294,9 @@ begin
begin
if rising_edge(clk) then
if verify_snk_in.valid = '1' then
- assert verify_snk_in = verify_fc_snk_in report "Unexpected verify_fc_snk_in at " & time'image(NOW) severity ERROR;
+ assert verify_snk_in = verify_fc_snk_in
+ report "Unexpected verify_fc_snk_in at " & time'image(NOW)
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
index 2079df7627..fc14e58787 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
@@ -305,7 +305,9 @@ begin
end loop;
proc_common_wait_some_cycles(clk, 10);
- assert rs_starts_cnt = 1 + c_nof_repeat report "Wrong number of BSN source starts." severity ERROR;
+ assert rs_starts_cnt = 1 + c_nof_repeat
+ report "Wrong number of BSN source starts."
+ severity ERROR;
tb_end <= '1';
wait;
@@ -342,10 +344,18 @@ begin
if rising_edge(clk) then
unexpected_rs_sync <= '0';
if verify_en = '1' and rs_sosi.valid = '1' then
- assert TO_UINT(rs_sosi.bsn) = exp_grid_rs.bsn report "Wrong rs_sosi.bsn /= exp_grid_rs.bsn" severity ERROR;
- assert rs_sosi.sync = exp_grid_rs.sync report "Wrong rs_sosi.sync /= exp_grid_rs.sync" severity ERROR;
- assert rs_sosi.sop = exp_grid_rs.sop report "Wrong rs_sosi.sop /= exp_grid_rs.sop" severity ERROR;
- assert rs_sosi.eop = exp_grid_rs.eop report "Wrong rs_sosi.eop /= exp_grid_rs.eop" severity ERROR;
+ assert TO_UINT(rs_sosi.bsn) = exp_grid_rs.bsn
+ report "Wrong rs_sosi.bsn /= exp_grid_rs.bsn"
+ severity ERROR;
+ assert rs_sosi.sync = exp_grid_rs.sync
+ report "Wrong rs_sosi.sync /= exp_grid_rs.sync"
+ severity ERROR;
+ assert rs_sosi.sop = exp_grid_rs.sop
+ report "Wrong rs_sosi.sop /= exp_grid_rs.sop"
+ severity ERROR;
+ assert rs_sosi.eop = exp_grid_rs.eop
+ report "Wrong rs_sosi.eop /= exp_grid_rs.eop"
+ severity ERROR;
-- Mark error in Wave window
if rs_sosi.sync = '1' and rs_sosi.sync /= exp_grid_rs.sync then
unexpected_rs_sync <= '1';
@@ -362,8 +372,12 @@ begin
begin
if rising_edge(clk) then
if rs_restart = '1' then
- assert rs_sosi.sync = '1' report "Unexpected rs_start while rs_sosi.sync /= 1" severity ERROR;
- assert prev_rs_valid = '0' report "Unexpected rs_start while prev_rs_valid /= 0" severity ERROR;
+ assert rs_sosi.sync = '1'
+ report "Unexpected rs_start while rs_sosi.sync /= 1"
+ severity ERROR;
+ assert prev_rs_valid = '0'
+ report "Unexpected rs_start while prev_rs_valid /= 0"
+ severity ERROR;
end if;
end if;
end process;
@@ -372,15 +386,23 @@ begin
begin
if rising_edge(clk) then
if rs_restart = '1' then
- assert rs_new_interval = '1' report "Wrong begin of rs_new_interval" severity ERROR;
+ assert rs_new_interval = '1'
+ report "Wrong begin of rs_new_interval"
+ severity ERROR;
tb_new_interval <= '1';
elsif rs_sosi.sync = '1' then
- assert rs_new_interval = '0' report "Wrong end of rs_new_interval" severity ERROR;
+ assert rs_new_interval = '0'
+ report "Wrong end of rs_new_interval"
+ severity ERROR;
tb_new_interval <= '0';
elsif tb_new_interval = '1' then
- assert rs_new_interval = '1' report "Wrong level during rs_new_interval" severity ERROR;
+ assert rs_new_interval = '1'
+ report "Wrong level during rs_new_interval"
+ severity ERROR;
else
- assert rs_new_interval = '0' report "Unexpected rs_new_interval" severity ERROR;
+ assert rs_new_interval = '0'
+ report "Unexpected rs_new_interval"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
index 2801b29fc2..59e3e5c263 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
@@ -152,14 +152,30 @@ begin
proc_common_wait_some_cycles(clk, g_nof_repeat * (g_pkt_gap + g_pkt_len)); -- Wait until end of simulation.
proc_common_wait_some_cycles(clk, 50); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
for I in 0 to c_nof_streams - 1 loop
- assert signed(verify_sosi.channel) = signed(out_ref_sosi_arr(I).channel) report "Unexpected channel from dut_ref output." severity ERROR;
- assert signed(verify_sosi.channel) = signed(out_pipe_sosi_arr(I).channel) report "Unexpected channel from dut_pipe output." severity ERROR;
- assert signed(verify_sosi.err) = signed(out_ref_sosi_arr(I).err) report "Unexpected err from dut_ref output." severity ERROR;
- assert signed(verify_sosi.err) = signed(out_pipe_sosi_arr(I).err) report "Unexpected err from dut_pipe output." severity ERROR;
- assert signed(verify_sosi.bsn) = signed(out_ref_sosi_arr(I).bsn) report "Unexpected bsn from dut_ref output." severity ERROR;
- assert signed(verify_sosi.bsn) = signed(out_pipe_sosi_arr(I).bsn) report "Unexpected bsn from dut_pipe output." severity ERROR;
- assert signed(verify_sosi.data) = signed(out_ref_sosi_arr(I).data) report "Unexpected data from dut_ref output." severity ERROR;
- assert signed(verify_sosi.data) + c_pipe_data_offset = signed(out_pipe_sosi_arr(I).data) report "Unexpected data from dut_pipe output." severity ERROR;
+ assert signed(verify_sosi.channel) = signed(out_ref_sosi_arr(I).channel)
+ report "Unexpected channel from dut_ref output."
+ severity ERROR;
+ assert signed(verify_sosi.channel) = signed(out_pipe_sosi_arr(I).channel)
+ report "Unexpected channel from dut_pipe output."
+ severity ERROR;
+ assert signed(verify_sosi.err) = signed(out_ref_sosi_arr(I).err)
+ report "Unexpected err from dut_ref output."
+ severity ERROR;
+ assert signed(verify_sosi.err) = signed(out_pipe_sosi_arr(I).err)
+ report "Unexpected err from dut_pipe output."
+ severity ERROR;
+ assert signed(verify_sosi.bsn) = signed(out_ref_sosi_arr(I).bsn)
+ report "Unexpected bsn from dut_ref output."
+ severity ERROR;
+ assert signed(verify_sosi.bsn) = signed(out_pipe_sosi_arr(I).bsn)
+ report "Unexpected bsn from dut_pipe output."
+ severity ERROR;
+ assert signed(verify_sosi.data) = signed(out_ref_sosi_arr(I).data)
+ report "Unexpected data from dut_ref output."
+ severity ERROR;
+ assert signed(verify_sosi.data) + c_pipe_data_offset = signed(out_pipe_sosi_arr(I).data)
+ report "Unexpected data from dut_pipe output."
+ severity ERROR;
end loop;
wait;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
index 55c713be62..cd99122a28 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
@@ -187,7 +187,9 @@ begin
v_rd_data := reg_miso.rddata(g_mm_w - 1 downto 0);
v_rd_count := v_rd_count + TO_UINT(v_rd_data) * 2**g_mm_w;
rd_count_arr(I) <= v_rd_count;
- assert exp_count_arr(I) = v_rd_count report "Wrong total block count(" & natural'image(I) & ")" severity ERROR;
+ assert exp_count_arr(I) = v_rd_count
+ report "Wrong total block count(" & natural'image(I) & ")"
+ severity ERROR;
end loop;
proc_common_wait_some_cycles(dp_clk, 100);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
index 83b91d5114..f61abbd26b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
@@ -137,13 +137,15 @@ begin
dp_switch_src_in <= c_dp_siso_hold;
proc_common_wait_some_cycles(mm_clk, 50);
assert dp_switch_src_out.valid = '0'
- report "Still data on output after setting hold command" severity ERROR;
+ report "Still data on output after setting hold command"
+ severity ERROR;
-- check if output data flows again if output send flush signal
dp_switch_src_in <= c_dp_siso_rdy;
proc_common_wait_some_cycles(mm_clk, 50);
assert dp_switch_src_out.valid = '1'
- report "No data on output after setting flush command" severity ERROR;
+ report "No data on output after setting flush command"
+ severity ERROR;
tb_end <= '1';
wait;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
index 22cf16f4c6..82aa00eedf 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
@@ -229,14 +229,26 @@ begin
begin
proc_common_wait_until_high(clk, verify_done);
if g_sync_period < g_nof_blk_per_sync then
- assert unsigned(dut_nof_early_syncs) > 0 report "No early syncs detected" severity ERROR;
- assert unsigned(dut_nof_late_syncs) = 0 report "Unexpected late syncs detected" severity ERROR;
+ assert unsigned(dut_nof_early_syncs) > 0
+ report "No early syncs detected"
+ severity ERROR;
+ assert unsigned(dut_nof_late_syncs) = 0
+ report "Unexpected late syncs detected"
+ severity ERROR;
elsif g_sync_period > g_nof_blk_per_sync then
- assert unsigned(dut_nof_early_syncs) = 0 report "Unexpected early syncs detected" severity ERROR;
- assert unsigned(dut_nof_late_syncs) > 0 report "No late syncs detected" severity ERROR;
+ assert unsigned(dut_nof_early_syncs) = 0
+ report "Unexpected early syncs detected"
+ severity ERROR;
+ assert unsigned(dut_nof_late_syncs) > 0
+ report "No late syncs detected"
+ severity ERROR;
else
- assert unsigned(dut_nof_early_syncs) = 0 report "Unexpected early syncs detected" severity ERROR;
- assert unsigned(dut_nof_late_syncs) = 0 report "Unexpected late syncs detected" severity ERROR;
+ assert unsigned(dut_nof_early_syncs) = 0
+ report "Unexpected early syncs detected"
+ severity ERROR;
+ assert unsigned(dut_nof_late_syncs) = 0
+ report "Unexpected late syncs detected"
+ severity ERROR;
end if;
wait;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
index d11d579d64..70e98806d7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
@@ -172,14 +172,18 @@ begin
p_verify_valid : process(clk)
begin
if rising_edge(clk) then
- assert out_sosi.valid = dly_valid_arr(c_dut_latency) report "Wrong out_sosi.valid" severity ERROR;
+ assert out_sosi.valid = dly_valid_arr(c_dut_latency)
+ report "Wrong out_sosi.valid"
+ severity ERROR;
end if;
end process;
p_verify_bsn_en : process
begin
wait for clk_period * 20;
- assert verify_bsn_en = '1' report "DP : BSN verification did not start in time." severity ERROR;
+ assert verify_bsn_en = '1'
+ report "DP : BSN verification did not start in time."
+ severity ERROR;
wait;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
index 599f8d615b..73570acdcf 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
@@ -213,11 +213,21 @@ begin
begin
if rising_edge(dp_clk) then
for I in 0 to g_nof_streams - 1 loop
- assert out_sosi_arr(I).valid = dly_ref_sosi_arr(c_dut_latency).valid report "Wrong out_sosi.valid" severity ERROR;
- assert out_sosi_arr(I).sop = dly_ref_sosi_arr(c_dut_latency).sop report "Wrong out_sosi.sop" severity ERROR;
- assert out_sosi_arr(I).eop = dly_ref_sosi_arr(c_dut_latency).eop report "Wrong out_sosi.eop" severity ERROR;
- assert out_sosi_arr(I).bsn = dly_ref_sosi_arr(c_dut_latency).bsn report "Wrong out_sosi.bsn" severity ERROR;
- assert out_sosi_arr(I).sync = exp_sync report "Wrong out_sosi.sync" severity ERROR;
+ assert out_sosi_arr(I).valid = dly_ref_sosi_arr(c_dut_latency).valid
+ report "Wrong out_sosi.valid"
+ severity ERROR;
+ assert out_sosi_arr(I).sop = dly_ref_sosi_arr(c_dut_latency).sop
+ report "Wrong out_sosi.sop"
+ severity ERROR;
+ assert out_sosi_arr(I).eop = dly_ref_sosi_arr(c_dut_latency).eop
+ report "Wrong out_sosi.eop"
+ severity ERROR;
+ assert out_sosi_arr(I).bsn = dly_ref_sosi_arr(c_dut_latency).bsn
+ report "Wrong out_sosi.bsn"
+ severity ERROR;
+ assert out_sosi_arr(I).sync = exp_sync
+ report "Wrong out_sosi.sync"
+ severity ERROR;
end loop;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
index 3ec876e8a3..2ae5541c0d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -212,11 +212,21 @@ begin
p_verify_out_sosi : process(dp_clk)
begin
if rising_edge(dp_clk) then
- assert out_sosi.valid = dly_ref_sosi_arr(g_dut_latency).valid report "Wrong out_sosi.valid" severity ERROR;
- assert out_sosi.sop = dly_ref_sosi_arr(g_dut_latency).sop report "Wrong out_sosi.sop" severity ERROR;
- assert out_sosi.eop = dly_ref_sosi_arr(g_dut_latency).eop report "Wrong out_sosi.eop" severity ERROR;
- assert out_sosi.bsn = dly_ref_sosi_arr(g_dut_latency).bsn report "Wrong out_sosi.bsn" severity ERROR;
- assert out_sosi.sync = dly_ref_sosi_arr(g_dut_latency).sync report "Wrong out_sosi.sync" severity ERROR;
+ assert out_sosi.valid = dly_ref_sosi_arr(g_dut_latency).valid
+ report "Wrong out_sosi.valid"
+ severity ERROR;
+ assert out_sosi.sop = dly_ref_sosi_arr(g_dut_latency).sop
+ report "Wrong out_sosi.sop"
+ severity ERROR;
+ assert out_sosi.eop = dly_ref_sosi_arr(g_dut_latency).eop
+ report "Wrong out_sosi.eop"
+ severity ERROR;
+ assert out_sosi.bsn = dly_ref_sosi_arr(g_dut_latency).bsn
+ report "Wrong out_sosi.bsn"
+ severity ERROR;
+ assert out_sosi.sync = dly_ref_sosi_arr(g_dut_latency).sync
+ report "Wrong out_sosi.sync"
+ severity ERROR;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
index f9587df95d..dc61d3a7ef 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
@@ -191,10 +191,14 @@ begin
if g_restart_at_sync = false then
if verify_en_sop = '1' and tb_stimuli_end = '0' then
if prev_verify_snk_in.valid = '1' and verify_snk_in.valid = '0' then
- assert xon_cnt = c_nof_valid_on report "Wrong XON time" severity ERROR;
+ assert xon_cnt = c_nof_valid_on
+ report "Wrong XON time"
+ severity ERROR;
end if;
if prev_verify_snk_in.valid = '0' and verify_snk_in.valid = '1' then
- assert xoff_cnt = c_exp_nof_clk_off report "Wrong XOFF time" severity ERROR;
+ assert xoff_cnt = c_exp_nof_clk_off
+ report "Wrong XOFF time"
+ severity ERROR;
end if;
end if;
else
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
index 46d08b2d87..d3afbf6c33 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
@@ -71,7 +71,9 @@ begin
sla_in_mosi.wrdata(0) <= '0';
sla_in_mosi.wr <= '0';
for I in 0 to c_500ns_latency - 1 loop wait until rising_edge(clk); end loop;
- assert xonoff_reg(0) = '1' report "xonoff_reg was not set correctly" severity ERROR;
+ assert xonoff_reg(0) = '1'
+ report "xonoff_reg was not set correctly"
+ severity ERROR;
sla_in_mosi.wrdata(0) <= '1';
sla_in_mosi.wr <= '1';
@@ -79,7 +81,9 @@ begin
sla_in_mosi.wrdata(0) <= '0';
sla_in_mosi.wr <= '0';
for I in 0 to c_timeout_2us - 1 loop wait until rising_edge(clk); end loop;
- assert xonoff_reg(0) = '0' report "Timeout did not work" severity ERROR;
+ assert xonoff_reg(0) = '0'
+ report "Timeout did not work"
+ severity ERROR;
sla_in_mosi.wrdata(0) <= '1';
sla_in_mosi.wr <= '1';
@@ -87,9 +91,13 @@ begin
sla_in_mosi.wrdata(0) <= '0';
sla_in_mosi.wr <= '0';
for I in 0 to c_500ns_latency - 1 loop wait until rising_edge(clk); end loop;
- assert xonoff_reg(0) = '1' report "xonoff_reg was not set correctly after recovering from timeout" severity ERROR;
+ assert xonoff_reg(0) = '1'
+ report "xonoff_reg was not set correctly after recovering from timeout"
+ severity ERROR;
tb_end <= '1';
- assert false report "Simulation tb_dp_xonoff_reg_timeout finished." severity NOTE;
+ assert false
+ report "Simulation tb_dp_xonoff_reg_timeout finished."
+ severity NOTE;
wait;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index 79f281d6e3..37421f738c 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -216,7 +216,8 @@ begin
for I in 0 to c_nof_streams - 1 loop
proc_mem_mm_bus_rd(2 * I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- assert reg_bsn_align_cipo.rddata(0) = '1' report
+ assert reg_bsn_align_cipo.rddata(0) = '1'
+ report
"Wrong stream disable for output " & int_to_str(I) severity ERROR;
end loop;
@@ -231,7 +232,8 @@ begin
for I in 0 to c_nof_streams - 1 loop
proc_mem_mm_bus_rd(2 * I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- assert reg_bsn_align_cipo.rddata(0) = '0' report
+ assert reg_bsn_align_cipo.rddata(0) = '0'
+ report
"Wrong BSN align stream enable for output " & int_to_str(I) severity ERROR;
end loop;
@@ -246,7 +248,8 @@ begin
for I in 0 to c_nof_streams - 1 loop
proc_mem_mm_bus_rd(2 * I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- assert reg_bsn_align_cipo.rddata(0) = '1' report
+ assert reg_bsn_align_cipo.rddata(0) = '1'
+ report
"Wrong BSN align stream enable for output " & int_to_str(I) severity ERROR;
end loop;
@@ -268,17 +271,19 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
if g_lost_input = true and I = c_nof_streams - 1 then
v_exp_latency := -1; -- -1 for BSN monitor timeout due to lost input
- assert mon_latency_input_arr(I) = v_exp_latency report
- "Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
- " (" & int_to_str(mon_latency_input_arr(I)) &
- " /= " & int_to_str(v_exp_latency) &
+ assert mon_latency_input_arr(I) = v_exp_latency
+ report
+ "Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
+ " (" & int_to_str(mon_latency_input_arr(I)) &
+ " /= " & int_to_str(v_exp_latency) &
")" severity ERROR;
else
v_exp_latency := c_mon_sync_latency + func_input_delay(I);
- assert mon_latency_input_arr(I) = v_exp_latency report
- "Wrong input BSN monitor latency for input " & int_to_str(I) &
- " (" & int_to_str(mon_latency_input_arr(I)) &
- " /= " & int_to_str(v_exp_latency) &
+ assert mon_latency_input_arr(I) = v_exp_latency
+ report
+ "Wrong input BSN monitor latency for input " & int_to_str(I) &
+ " (" & int_to_str(mon_latency_input_arr(I)) &
+ " /= " & int_to_str(v_exp_latency) &
")" severity ERROR;
end if;
end loop;
@@ -290,9 +295,10 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
v_exp_latency := c_mon_sync_latency + c_total_latency;
- assert mon_latency_output = v_exp_latency report
- "Wrong output BSN monitor latency (" & int_to_str(mon_latency_output) &
- " /= " & int_to_str(v_exp_latency) &
+ assert mon_latency_output = v_exp_latency
+ report
+ "Wrong output BSN monitor latency (" & int_to_str(mon_latency_output) &
+ " /= " & int_to_str(v_exp_latency) &
")" severity ERROR;
-- End of MM test
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index 20d75a9e96..f35a8bd290 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -114,14 +114,18 @@ begin
-- . Verify mon_block_size
proc_common_wait_some_cycles(mm_clk, 1);
- assert mon_block_size = c_block_size report "Wrong block_size." severity ERROR;
+ assert mon_block_size = c_block_size
+ report "Wrong block_size."
+ severity ERROR;
-- . Read mon_output_interval_size
proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_output_interval_size <= TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
- assert mon_output_interval_size = c_ctrl_interval_size_min report "Wrong minimum output interval_size." severity ERROR;
+ assert mon_output_interval_size = c_ctrl_interval_size_min
+ report "Wrong minimum output interval_size."
+ severity ERROR;
-- . Read mon_output_enable
proc_mem_mm_bus_rd(8, mm_clk, reg_miso, reg_mosi);
@@ -130,7 +134,9 @@ begin
-- . Verify output is off
proc_common_wait_some_cycles(mm_clk, 1);
- assert mon_output_enable = '0' report "DUT output is enabled." severity ERROR;
+ assert mon_output_enable = '0'
+ report "DUT output is enabled."
+ severity ERROR;
---------------------------------------------------------------------------
-- Verify c_ctrl_start_bsn_hi
@@ -151,8 +157,12 @@ begin
ctrl_start_bsn_64(2 * c_word_w - 1 downto c_word_w) <= reg_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
- assert c_ctrl_start_bsn_lo = TO_UINT(ctrl_start_bsn_64( c_word_w - 1 downto 0)) report "Wrong ctrl_start_bsn low word." severity ERROR;
- assert c_ctrl_start_bsn_hi = TO_UINT(ctrl_start_bsn_64(2 * c_word_w - 1 downto c_word_w)) report "Wrong ctrl_start_bsn high word." severity ERROR;
+ assert c_ctrl_start_bsn_lo = TO_UINT(ctrl_start_bsn_64( c_word_w - 1 downto 0))
+ report "Wrong ctrl_start_bsn low word."
+ severity ERROR;
+ assert c_ctrl_start_bsn_hi = TO_UINT(ctrl_start_bsn_64(2 * c_word_w - 1 downto c_word_w))
+ report "Wrong ctrl_start_bsn high word."
+ severity ERROR;
---------------------------------------------------------------------------
-- Setup, enable and verify DUT output
@@ -226,9 +236,15 @@ begin
-- Verify output is on and running
proc_common_wait_some_cycles(mm_clk, 1);
- assert mon_output_enable = '1' report "mon_output_enable is not enabled." severity ERROR;
- assert out_enable = '1' report "output_enable is not enabled." severity ERROR;
- assert mon_output_interval_size = c_ctrl_interval_size report "mon_output_interval_size is not ctrl_interval_size." severity ERROR;
+ assert mon_output_enable = '1'
+ report "mon_output_enable is not enabled."
+ severity ERROR;
+ assert out_enable = '1'
+ report "output_enable is not enabled."
+ severity ERROR;
+ assert mon_output_interval_size = c_ctrl_interval_size
+ report "mon_output_interval_size is not ctrl_interval_size."
+ severity ERROR;
---------------------------------------------------------------------------
-- Check that monitor BSN are incrementing
@@ -245,9 +261,12 @@ begin
mon_current_input_bsn_64(2 * c_word_w - 1 downto c_word_w) <= reg_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
if c_report_note then
- report "mon_current_input_bsn : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_current_input_bsn_64)) severity NOTE;
+ report "mon_current_input_bsn : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_current_input_bsn_64))
+ severity NOTE;
end if;
- assert v_bsn < TO_UINT(mon_current_input_bsn_64) report "DUT mon_current_input_bsn is not incrementing." severity ERROR;
+ assert v_bsn < TO_UINT(mon_current_input_bsn_64)
+ report "DUT mon_current_input_bsn is not incrementing."
+ severity ERROR;
-- . Check mon_input_bsn_at_sync_64
v_bsn := TO_UINT(mon_input_bsn_at_sync_64);
@@ -259,10 +278,15 @@ begin
mon_input_bsn_at_sync_64(2 * c_word_w - 1 downto c_word_w) <= reg_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
if c_report_note then
- report "mon_input_bsn_at_sync : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_input_bsn_at_sync_64)) severity NOTE;
+ report "mon_input_bsn_at_sync : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_input_bsn_at_sync_64))
+ severity NOTE;
end if;
- assert v_bsn < TO_UINT(mon_input_bsn_at_sync_64) report "DUT mon_input_bsn_at_sync is not incrementing." severity ERROR;
- assert (TO_UINT(mon_input_bsn_at_sync_64) - v_bsn) mod c_nof_block_per_input_sync = 0 report "TB input_sync interval is not correct." severity ERROR;
+ assert v_bsn < TO_UINT(mon_input_bsn_at_sync_64)
+ report "DUT mon_input_bsn_at_sync is not incrementing."
+ severity ERROR;
+ assert (TO_UINT(mon_input_bsn_at_sync_64) - v_bsn) mod c_nof_block_per_input_sync = 0
+ report "TB input_sync interval is not correct."
+ severity ERROR;
-- . Check mon_output_sync_bsn_64
v_bsn := TO_UINT(mon_output_sync_bsn_64);
@@ -274,10 +298,15 @@ begin
mon_output_sync_bsn_64(2 * c_word_w - 1 downto c_word_w) <= reg_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
if c_report_note then
- report "mon_output_sync_bsn : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_output_sync_bsn_64)) severity NOTE;
+ report "mon_output_sync_bsn : " & int_to_str(v_bsn) & ", " & int_to_str(TO_UINT(mon_output_sync_bsn_64))
+ severity NOTE;
end if;
- assert v_bsn < TO_UINT(mon_output_sync_bsn_64) report "DUT mon_output_sync_bsn is not incrementing." severity ERROR;
- assert (TO_UINT(mon_output_sync_bsn_64) - v_bsn) mod c_nof_block_per_output_sync = 0 report "DUT output_sync interval is not correct." severity ERROR;
+ assert v_bsn < TO_UINT(mon_output_sync_bsn_64)
+ report "DUT mon_output_sync_bsn is not incrementing."
+ severity ERROR;
+ assert (TO_UINT(mon_output_sync_bsn_64) - v_bsn) mod c_nof_block_per_output_sync = 0
+ report "DUT output_sync interval is not correct."
+ severity ERROR;
---------------------------------------------------------------------------
-- Verify BSN hi word
@@ -316,9 +345,15 @@ begin
-- dp_bsn_sync_scheduler will be busy trying to catch up, see
-- nxt_r.update_bsn = '1' in dp_bsn_sync_scheduler.vhd. Therefore
-- expected mon_output_sync_bsn_64 hi value is still 0.
- assert c_bsn_hi_value = TO_UINT(mon_current_input_bsn_64(2 * c_word_w - 1 downto c_word_w)) report "Wrong mon_current_input_bsn high word." severity ERROR;
- assert c_bsn_hi_value = TO_UINT(mon_input_bsn_at_sync_64(2 * c_word_w - 1 downto c_word_w)) report "Wrong mon_input_bsn_at_sync high word." severity ERROR;
- assert 0 = TO_UINT(mon_output_sync_bsn_64( 2 * c_word_w - 1 downto c_word_w)) report "Wrong mon_output_sync_bsn high word." severity ERROR;
+ assert c_bsn_hi_value = TO_UINT(mon_current_input_bsn_64(2 * c_word_w - 1 downto c_word_w))
+ report "Wrong mon_current_input_bsn high word."
+ severity ERROR;
+ assert c_bsn_hi_value = TO_UINT(mon_input_bsn_at_sync_64(2 * c_word_w - 1 downto c_word_w))
+ report "Wrong mon_input_bsn_at_sync high word."
+ severity ERROR;
+ assert 0 = TO_UINT(mon_output_sync_bsn_64( 2 * c_word_w - 1 downto c_word_w))
+ report "Wrong mon_output_sync_bsn high word."
+ severity ERROR;
---------------------------------------------------------------------------
-- Disable and verify DUT output
@@ -338,8 +373,12 @@ begin
-- Verify output is on and running
proc_common_wait_some_cycles(mm_clk, 1);
- assert mon_output_enable = '0' report "DUT mon_output_enable is not diabled." severity ERROR;
- assert out_enable = '0' report "DUT output_enable is not enabled." severity ERROR;
+ assert mon_output_enable = '0'
+ report "DUT mon_output_enable is not diabled."
+ severity ERROR;
+ assert out_enable = '0'
+ report "DUT output_enable is not enabled."
+ severity ERROR;
---------------------------------------------------------------------------
-- End of test
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
index 13cb45b509..557ccb6d05 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
@@ -108,7 +108,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
+ assert mm_dp_on_status = c_mm_dp_on_immediate
+ report "Wrong DP on status, expected DP on immediate."
+ severity ERROR;
-- Read BSN twice in same PPS interval
proc_common_wait_some_cycles(clk, 3 * c_block_size);
@@ -133,7 +135,9 @@ begin
-- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
--ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
- assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
+ assert mm_bsn_prev = mm_bsn
+ report "Wrong BSN, expected constant BSN during PPS or sync interval."
+ severity ERROR;
-- Run few sync intervals
proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
@@ -147,7 +151,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
+ assert mm_dp_on_status = c_mm_dp_off
+ report "Wrong DP on status, expected DP off."
+ severity ERROR;
proc_common_wait_some_cycles(clk, c_sync_interval);
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
index a17112b675..bd571b81e9 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
@@ -114,7 +114,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
+ assert mm_dp_on_status = c_mm_dp_on_immediate
+ report "Wrong DP on status, expected DP on immediate."
+ severity ERROR;
-- Read BSN twice in same PPS interval
proc_common_wait_some_cycles(clk, c_block_size);
@@ -139,7 +141,9 @@ begin
-- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
--ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
- assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
+ assert mm_bsn_prev = mm_bsn
+ report "Wrong BSN, expected constant BSN during PPS or sync interval."
+ severity ERROR;
-- Run few sync intervals
proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
@@ -153,7 +157,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
+ assert mm_dp_on_status = c_mm_dp_off
+ report "Wrong DP on status, expected DP off."
+ severity ERROR;
-- Set bsn_time_offset and read back 2 times 0 and 5
proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 0, clk, mm_miso, mm_mosi);
@@ -163,7 +169,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0) <= mm_miso.rddata(c_bsn_time_offset_w - 1 downto 0);
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 0 report "Wrong offset, expected 0" severity ERROR;
+ assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 0
+ report "Wrong offset, expected 0"
+ severity ERROR;
proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 5, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, 2 * c_cross_clock_domain_latency);
@@ -172,7 +180,9 @@ begin
proc_mem_mm_bus_rd_latency(1, clk);
mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0) <= mm_miso.rddata(c_bsn_time_offset_w - 1 downto 0);
proc_common_wait_some_cycles(clk, 1);
- assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 5 report "Wrong offset, expected 5" severity ERROR;
+ assert TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w - 1 downto 0)) = 5
+ report "Wrong offset, expected 5"
+ severity ERROR;
proc_common_wait_some_cycles(clk, c_sync_interval);
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
index 4a405507f7..1ccbe5f325 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
@@ -222,19 +222,39 @@ begin
if verify_en = '1' and snk_in_complex_dly.valid = '1' then
for I in 0 to g_nof_streams - 1 loop
-- verify unchanged sosi fields (= pipeline)
- assert src_out_arr(I).sync = snk_in_complex_dly.sync report "Unexpected sync" severity ERROR;
- assert src_out_arr(I).sop = snk_in_complex_dly.sop report "Unexpected sop" severity ERROR;
- assert src_out_arr(I).eop = snk_in_complex_dly.eop report "Unexpected eop" severity ERROR;
- assert src_out_arr(I).valid = snk_in_complex_dly.valid report "Unexpected valid" severity ERROR;
- assert signed(src_out_arr(I).bsn) = signed(snk_in_complex_dly.bsn) report "Unexpected bsn" severity ERROR;
- assert signed(src_out_arr(I).channel) = signed(snk_in_complex_dly.channel) report "Unexpected channel" severity ERROR;
- assert signed(src_out_arr(I).err) = signed(snk_in_complex_dly.err) report "Unexpected err" severity ERROR;
+ assert src_out_arr(I).sync = snk_in_complex_dly.sync
+ report "Unexpected sync"
+ severity ERROR;
+ assert src_out_arr(I).sop = snk_in_complex_dly.sop
+ report "Unexpected sop"
+ severity ERROR;
+ assert src_out_arr(I).eop = snk_in_complex_dly.eop
+ report "Unexpected eop"
+ severity ERROR;
+ assert src_out_arr(I).valid = snk_in_complex_dly.valid
+ report "Unexpected valid"
+ severity ERROR;
+ assert signed(src_out_arr(I).bsn) = signed(snk_in_complex_dly.bsn)
+ report "Unexpected bsn"
+ severity ERROR;
+ assert signed(src_out_arr(I).channel) = signed(snk_in_complex_dly.channel)
+ report "Unexpected channel"
+ severity ERROR;
+ assert signed(src_out_arr(I).err) = signed(snk_in_complex_dly.err)
+ report "Unexpected err"
+ severity ERROR;
if force_en = '0' or I /= g_force_stream then
-- verify default data pass on (= pipeline)
- assert signed(src_out_arr(I).data) = signed(snk_in_complex_dly.data) report "Unexpected data" severity ERROR;
- assert signed(src_out_arr(I).re) = signed(snk_in_complex_dly.re) report "Unexpected real" severity ERROR;
- assert signed(src_out_arr(I).im) = signed(snk_in_complex_dly.im) report "Unexpected imag" severity ERROR;
+ assert signed(src_out_arr(I).data) = signed(snk_in_complex_dly.data)
+ report "Unexpected data"
+ severity ERROR;
+ assert signed(src_out_arr(I).re) = signed(snk_in_complex_dly.re)
+ report "Unexpected real"
+ severity ERROR;
+ assert signed(src_out_arr(I).im) = signed(snk_in_complex_dly.im)
+ report "Unexpected imag"
+ severity ERROR;
else
-- verify default force data on stream I=g_force_stream
v_exp_data := TO_SINT(INCR_DP_SDATA( prev_src_out_arr(I).data, g_increment_data, g_dat_w));
@@ -248,40 +268,64 @@ begin
-- .data
if g_increment_data = 0 then
- assert TO_SINT(src_out_arr(I).data) = g_force_data report "Unexpected force data" severity ERROR;
+ assert TO_SINT(src_out_arr(I).data) = g_force_data
+ report "Unexpected force data"
+ severity ERROR;
else
if g_restart_on_sync = true and snk_in_complex_dly.sync = '1' then
- assert TO_SINT(src_out_arr(I).data) = g_force_data report "Unexpected restart force data at sync" severity ERROR;
+ assert TO_SINT(src_out_arr(I).data) = g_force_data
+ report "Unexpected restart force data at sync"
+ severity ERROR;
elsif g_restart_on_sop = true and snk_in_complex_dly.sop = '1' then
- assert TO_SINT(src_out_arr(I).data) = g_force_data report "Unexpected restart force data at sop" severity ERROR;
+ assert TO_SINT(src_out_arr(I).data) = g_force_data
+ report "Unexpected restart force data at sop"
+ severity ERROR;
else
- assert TO_SINT(src_out_arr(I).data) = v_exp_data report "Unexpected increment data" severity ERROR;
+ assert TO_SINT(src_out_arr(I).data) = v_exp_data
+ report "Unexpected increment data"
+ severity ERROR;
end if;
end if;
-- .re
if g_increment_re = 0 then
- assert TO_SINT(src_out_arr(I).re) = g_force_re report "Unexpected force re" severity ERROR;
+ assert TO_SINT(src_out_arr(I).re) = g_force_re
+ report "Unexpected force re"
+ severity ERROR;
else
if g_restart_on_sync = true and snk_in_complex_dly.sync = '1' then
- assert TO_SINT(src_out_arr(I).re) = g_force_re report "Unexpected restart force re at sync" severity ERROR;
+ assert TO_SINT(src_out_arr(I).re) = g_force_re
+ report "Unexpected restart force re at sync"
+ severity ERROR;
elsif g_restart_on_sop = true and snk_in_complex_dly.sop = '1' then
- assert TO_SINT(src_out_arr(I).re) = g_force_re report "Unexpected restart force re at sop" severity ERROR;
+ assert TO_SINT(src_out_arr(I).re) = g_force_re
+ report "Unexpected restart force re at sop"
+ severity ERROR;
else
- assert TO_SINT(src_out_arr(I).re) = v_exp_re report "Unexpected increment re" severity ERROR;
+ assert TO_SINT(src_out_arr(I).re) = v_exp_re
+ report "Unexpected increment re"
+ severity ERROR;
end if;
end if;
-- .im
if g_increment_im = 0 then
- assert TO_SINT(src_out_arr(I).im) = g_force_im report "Unexpected force im" severity ERROR;
+ assert TO_SINT(src_out_arr(I).im) = g_force_im
+ report "Unexpected force im"
+ severity ERROR;
else
if g_restart_on_sync = true and snk_in_complex_dly.sync = '1' then
- assert TO_SINT(src_out_arr(I).im) = g_force_im report "Unexpected restart force im at sync" severity ERROR;
+ assert TO_SINT(src_out_arr(I).im) = g_force_im
+ report "Unexpected restart force im at sync"
+ severity ERROR;
elsif g_restart_on_sop = true and snk_in_complex_dly.sop = '1' then
- assert TO_SINT(src_out_arr(I).im) = g_force_im report "Unexpected restart force im at sop" severity ERROR;
+ assert TO_SINT(src_out_arr(I).im) = g_force_im
+ report "Unexpected restart force im at sop"
+ severity ERROR;
else
- assert TO_SINT(src_out_arr(I).im) = v_exp_im report "Unexpected increment im" severity ERROR;
+ assert TO_SINT(src_out_arr(I).im) = v_exp_im
+ report "Unexpected increment im"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
index 4925844ae7..99b7c900a8 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
@@ -239,35 +239,73 @@ begin
if verify_en = '1' and snk_in_complex_dly.valid = '1' then
for I in 0 to g_nof_streams - 1 loop
-- verify unchanged sosi fields (= pipeline)
- assert src_out_arr(I).sync = snk_in_complex_dly.sync report "Unexpected sync" severity ERROR;
- assert src_out_arr(I).sop = snk_in_complex_dly.sop report "Unexpected sop" severity ERROR;
- assert src_out_arr(I).eop = snk_in_complex_dly.eop report "Unexpected eop" severity ERROR;
- assert src_out_arr(I).valid = snk_in_complex_dly.valid report "Unexpected valid" severity ERROR;
- assert signed(src_out_arr(I).bsn) = signed(snk_in_complex_dly.bsn) report "Unexpected bsn" severity ERROR;
- assert signed(src_out_arr(I).channel) = signed(snk_in_complex_dly.channel) report "Unexpected channel" severity ERROR;
- assert signed(src_out_arr(I).err) = signed(snk_in_complex_dly.err) report "Unexpected err" severity ERROR;
+ assert src_out_arr(I).sync = snk_in_complex_dly.sync
+ report "Unexpected sync"
+ severity ERROR;
+ assert src_out_arr(I).sop = snk_in_complex_dly.sop
+ report "Unexpected sop"
+ severity ERROR;
+ assert src_out_arr(I).eop = snk_in_complex_dly.eop
+ report "Unexpected eop"
+ severity ERROR;
+ assert src_out_arr(I).valid = snk_in_complex_dly.valid
+ report "Unexpected valid"
+ severity ERROR;
+ assert signed(src_out_arr(I).bsn) = signed(snk_in_complex_dly.bsn)
+ report "Unexpected bsn"
+ severity ERROR;
+ assert signed(src_out_arr(I).channel) = signed(snk_in_complex_dly.channel)
+ report "Unexpected channel"
+ severity ERROR;
+ assert signed(src_out_arr(I).err) = signed(snk_in_complex_dly.err)
+ report "Unexpected err"
+ severity ERROR;
if force_en = '0' or I /= g_force_stream then
-- verify default data pass on (= pipeline)
- assert signed(src_out_arr(I).data) = signed(snk_in_complex_dly.data) report "Unexpected data" severity ERROR;
- assert signed(src_out_arr(I).re) = signed(snk_in_complex_dly.re) report "Unexpected real" severity ERROR;
- assert signed(src_out_arr(I).im) = signed(snk_in_complex_dly.im) report "Unexpected imag" severity ERROR;
+ assert signed(src_out_arr(I).data) = signed(snk_in_complex_dly.data)
+ report "Unexpected data"
+ severity ERROR;
+ assert signed(src_out_arr(I).re) = signed(snk_in_complex_dly.re)
+ report "Unexpected real"
+ severity ERROR;
+ assert signed(src_out_arr(I).im) = signed(snk_in_complex_dly.im)
+ report "Unexpected imag"
+ severity ERROR;
else
-- verify force data, re, im on stream I=g_force_stream
if v_index = g_force_index then
if force_value = '1' then
- assert TO_SINT(src_out_arr(I).data) = g_force_data report "Unexpected force data at index" severity ERROR;
- assert TO_SINT(src_out_arr(I).re) = g_force_re report "Unexpected force real at index" severity ERROR;
- assert TO_SINT(src_out_arr(I).im) = g_force_im report "Unexpected force imag at index" severity ERROR;
+ assert TO_SINT(src_out_arr(I).data) = g_force_data
+ report "Unexpected force data at index"
+ severity ERROR;
+ assert TO_SINT(src_out_arr(I).re) = g_force_re
+ report "Unexpected force real at index"
+ severity ERROR;
+ assert TO_SINT(src_out_arr(I).im) = g_force_im
+ report "Unexpected force imag at index"
+ severity ERROR;
else
- assert signed(src_out_arr(I).data) = signed(snk_in_complex_dly.data) report "Unexpected transparant data at index" severity ERROR;
- assert signed(src_out_arr(I).re) = signed(snk_in_complex_dly.re) report "Unexpected transparant real at index" severity ERROR;
- assert signed(src_out_arr(I).im) = signed(snk_in_complex_dly.im) report "Unexpected transparant imag at index" severity ERROR;
+ assert signed(src_out_arr(I).data) = signed(snk_in_complex_dly.data)
+ report "Unexpected transparant data at index"
+ severity ERROR;
+ assert signed(src_out_arr(I).re) = signed(snk_in_complex_dly.re)
+ report "Unexpected transparant real at index"
+ severity ERROR;
+ assert signed(src_out_arr(I).im) = signed(snk_in_complex_dly.im)
+ report "Unexpected transparant imag at index"
+ severity ERROR;
end if;
else
- assert TO_SINT(src_out_arr(I).data) = 0 report "Unexpected force data not zero in rest of block" severity ERROR;
- assert TO_SINT(src_out_arr(I).re) = 0 report "Unexpected force real not zero in rest of block" severity ERROR;
- assert TO_SINT(src_out_arr(I).im) = 0 report "Unexpected force imag not zero in rest of block" severity ERROR;
+ assert TO_SINT(src_out_arr(I).data) = 0
+ report "Unexpected force data not zero in rest of block"
+ severity ERROR;
+ assert TO_SINT(src_out_arr(I).re) = 0
+ report "Unexpected force real not zero in rest of block"
+ severity ERROR;
+ assert TO_SINT(src_out_arr(I).im) = 0
+ report "Unexpected force imag not zero in rest of block"
+ severity ERROR;
end if;
end if;
end loop;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
index f055d4eeee..72e025a7d4 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
@@ -202,14 +202,24 @@ begin
if verify_en = '1' then
for I in 0 to g_nof_streams - 1 loop
if c_real_multiply = true then
- assert signed(out_sosi_arr(I).data) = signed(exp_sosi_arr(I).data) report "Unexpected real data" severity ERROR;
+ assert signed(out_sosi_arr(I).data) = signed(exp_sosi_arr(I).data)
+ report "Unexpected real data"
+ severity ERROR;
else
if g_complex_gain = false then
- assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re) report "Unexpected complex real data, with real gain" severity ERROR;
- assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im) report "Unexpected complex imag data, with real gain" severity ERROR;
+ assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re)
+ report "Unexpected complex real data, with real gain"
+ severity ERROR;
+ assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im)
+ report "Unexpected complex imag data, with real gain"
+ severity ERROR;
else
- assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re) report "Unexpected complex real data, with complex gain" severity ERROR;
- assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im) report "Unexpected complex imag data, with complex gain" severity ERROR;
+ assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re)
+ report "Unexpected complex real data, with complex gain"
+ severity ERROR;
+ assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im)
+ report "Unexpected complex imag data, with complex gain"
+ severity ERROR;
end if;
end if;
end loop;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
index 119ee1426e..4e4e5b17ef 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
@@ -234,14 +234,24 @@ begin
if verify_en = '1' then
for I in 0 to g_nof_streams - 1 loop
if c_real_multiply = true then
- assert signed(out_sosi_arr(I).data) = signed(exp_sosi_arr(I).data) report "Unexpected real data" severity ERROR;
+ assert signed(out_sosi_arr(I).data) = signed(exp_sosi_arr(I).data)
+ report "Unexpected real data"
+ severity ERROR;
else
if g_complex_gain = false then
- assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re) report "Unexpected complex real data, with real gain" severity ERROR;
- assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im) report "Unexpected complex imag data, with real gain" severity ERROR;
+ assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re)
+ report "Unexpected complex real data, with real gain"
+ severity ERROR;
+ assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im)
+ report "Unexpected complex imag data, with real gain"
+ severity ERROR;
else
- assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re) report "Unexpected complex real data, with complex gain" severity ERROR;
- assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im) report "Unexpected complex imag data, with complex gain" severity ERROR;
+ assert signed(out_sosi_arr(I).re) = signed(exp_sosi_arr(I).re)
+ report "Unexpected complex real data, with complex gain"
+ severity ERROR;
+ assert signed(out_sosi_arr(I).im) = signed(exp_sosi_arr(I).im)
+ report "Unexpected complex imag data, with complex gain"
+ severity ERROR;
end if;
end if;
end loop;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
index 869118a709..a12a317cfe 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
@@ -149,8 +149,12 @@ begin
begin
if rising_edge(dp_clk) then
if verify_en = '1' then
- assert signed(out_sosi.re) = signed(exp_sosi.re) report "Unexpected complex real data, with real gain" severity ERROR;
- assert signed(out_sosi.im) = signed(exp_sosi.im) report "Unexpected complex imag data, with real gain" severity ERROR;
+ assert signed(out_sosi.re) = signed(exp_sosi.re)
+ report "Unexpected complex real data, with real gain"
+ severity ERROR;
+ assert signed(out_sosi.im) = signed(exp_sosi.im)
+ report "Unexpected complex imag data, with real gain"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
index 16982fd0cd..1b45aff38c 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
@@ -241,8 +241,12 @@ begin
mm_nof_late_syncs <= mm_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
- assert TO_UINT(mm_nof_early_syncs) = 0 report "Unexpected mm_nof_early_syncs" severity ERROR;
- assert TO_UINT(mm_nof_late_syncs) > 0 report "Unexpected mm_nof_late_syncs" severity ERROR;
+ assert TO_UINT(mm_nof_early_syncs) = 0
+ report "Unexpected mm_nof_early_syncs"
+ severity ERROR;
+ assert TO_UINT(mm_nof_late_syncs) > 0
+ report "Unexpected mm_nof_late_syncs"
+ severity ERROR;
-- read again to verify clear after rd
proc_mem_mm_bus_rd(0, mm_clk, mm_mosi); -- Read nof_early_syncs
@@ -253,8 +257,12 @@ begin
mm_nof_late_syncs <= mm_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
- assert TO_UINT(mm_nof_early_syncs) = 0 report "Unexpected cleared mm_nof_early_syncs" severity ERROR;
- assert TO_UINT(mm_nof_late_syncs) = 0 report "Unexpected cleared mm_nof_late_syncs" severity ERROR;
+ assert TO_UINT(mm_nof_early_syncs) = 0
+ report "Unexpected cleared mm_nof_early_syncs"
+ severity ERROR;
+ assert TO_UINT(mm_nof_late_syncs) = 0
+ report "Unexpected cleared mm_nof_late_syncs"
+ severity ERROR;
wait;
end process;
diff --git a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
index 61d220fd40..3d8b66033a 100644
--- a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
@@ -162,7 +162,9 @@ begin
slave_index_arr(0) <= g_nof_slaves; -- default index of none existing slave
for I in 0 to g_nof_slaves - 1 loop
v_base := TO_UINT(master_mosi.address(c_mm_bus_addr_w - 1 downto g_width_arr(I)));
- assert g_base_arr(I) mod 2**g_width_arr(I) = 0 report "Slave base address must be a multiple of the slave width." severity FAILURE;
+ assert g_base_arr(I) mod 2**g_width_arr(I) = 0
+ report "Slave base address must be a multiple of the slave width."
+ severity FAILURE;
if v_base = g_base_arr(I) / 2**g_width_arr(I) then
slave_index_arr(0) <= I; -- return index of addressed slave
exit; -- Found addressed slave, no need to loop further. EXIT is
diff --git a/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
index 67bcb3211c..eb0740e75f 100644
--- a/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
@@ -138,8 +138,8 @@ architecture str of mm_bus_pipe is
signal adapt_miso_arr : t_mem_miso_arr(0 to g_nof_slaves - 1);
begin
assert not(g_pipeline_miso_wait = true and g_pipeline_mosi = true)
- report "Do not use g_pipeline_mosi = true if g_pipeline_miso_wait = TRUE"
- severity FAILURE;
+ report "Do not use g_pipeline_mosi = true if g_pipeline_miso_wait = TRUE"
+ severity FAILURE;
-- Master side
m_mosi <= master_mosi;
diff --git a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
index e2277654a5..9e6db7515a 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
@@ -343,7 +343,8 @@ package body mm_file_pkg is
end if;
else
- report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) severity NOTE;
+ report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now)
+ severity NOTE;
-- Try again next time; wait one MM clock cycle.
proc_common_wait_some_cycles(mm_clk, 1);
end if;
@@ -399,7 +400,8 @@ package body mm_file_pkg is
end if;
else
- report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now) severity NOTE;
+ report "mmf_mm_from_file() could not open " & rd_filename & " at " & time_to_str(now)
+ severity NOTE;
-- Try again next time; wait in procedure mmf_poll_sim_ctrl_file
end if;
@@ -471,7 +473,8 @@ package body mm_file_pkg is
end if;
end if;
else
- report "mmf_wait_for_file_status() could not open " & rd_filename & " at " & time_to_str(now) severity NOTE;
+ report "mmf_wait_for_file_status() could not open " & rd_filename & " at " & time_to_str(now)
+ severity NOTE;
wait until falling_edge(mm_clk);
end if;
end loop;
@@ -514,7 +517,8 @@ package body mm_file_pkg is
writeline(ctrl_file, wr_line);
file_close(ctrl_file);
else
- report "mmf_mm_bus_wr() could not open " & ctrl_filename & " at " & time_to_str(now) severity NOTE;
+ report "mmf_mm_bus_wr() could not open " & ctrl_filename & " at " & time_to_str(now)
+ severity NOTE;
end if;
-- Prepare for next MM request
@@ -555,7 +559,8 @@ package body mm_file_pkg is
writeline(ctrl_file, wr_line);
file_close(ctrl_file);
else
- report "mmf_mm_bus_rd() could not open " & ctrl_filename & " at " & time_to_str(now) severity FAILURE;
+ report "mmf_mm_bus_rd() could not open " & ctrl_filename & " at " & time_to_str(now)
+ severity FAILURE;
end if;
-- Wait until the MM RD access has written the read data to the .stat file
@@ -573,7 +578,8 @@ package body mm_file_pkg is
-- the wait should be < mm_clk period/2 to not affect the read rate
wait for 1 fs;
else
- report "mmf_mm_bus_rd() could not open " & stat_filename & " at " & time_to_str(now) severity FAILURE;
+ report "mmf_mm_bus_rd() could not open " & stat_filename & " at " & time_to_str(now)
+ severity FAILURE;
end if;
-- No need to prepare for next MM request, because:
@@ -651,7 +657,8 @@ package body mm_file_pkg is
writeline(ctrl_file, wr_line);
file_close(ctrl_file);
else
- report "mmf_sim_get_now() could not open " & ctrl_filename & " at " & time_to_str(now) severity FAILURE;
+ report "mmf_sim_get_now() could not open " & ctrl_filename & " at " & time_to_str(now)
+ severity FAILURE;
end if;
-- Wait until the simulation has written the simulation status to the sim.stat file
@@ -667,7 +674,8 @@ package body mm_file_pkg is
rd_now <= v_rd_now;
print_str("GET_SIM_TIME = " & v_rd_now & " at " & time_to_str(now));
else
- report "mmf_sim_get_now() could not open " & stat_filename & " at " & time_to_str(now) severity FAILURE;
+ report "mmf_sim_get_now() could not open " & stat_filename & " at " & time_to_str(now)
+ severity FAILURE;
end if;
-- No need to prepare for next simulation status request, because:
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
index 76a0c79b24..2fb5a7a4c2 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
@@ -155,7 +155,9 @@ begin
-- Verify that test has indeed ran
wait for 1 ns; -- wait 1 ns to ensure that assert report appears at end of transcript log
- assert cnt_rdval = cnt_rd and cnt_rdval > 0 report "Wrong number of rdval" severity ERROR;
+ assert cnt_rdval = cnt_rd and cnt_rdval > 0
+ report "Wrong number of rdval"
+ severity ERROR;
tb_end <= '1';
wait;
@@ -176,7 +178,8 @@ begin
cnt_rdval <= cnt_rdval + 1;
v_rddata := TO_UINT(master_miso.rddata(c_data_w - 1 downto 0));
if v_rddata /= v_expdata then
- report "Error! Readvalue is not as expected" severity ERROR;
+ report "Error! Readvalue is not as expected"
+ severity ERROR;
end if;
v_expdata := v_expdata + 1;
end if;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
index ce5bfc5ca2..5bebb5ae1b 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
@@ -140,7 +140,9 @@ begin
wait for 2 * c_mmf_mm_timeout;
end if;
mmf_mm_bus_rd(c_reg_r_w_dc_file_pathname, c_mem_reg.latency, I, file_rd_data, mm_clk);
- assert I = TO_UINT(file_rd_data) report "Read data is wrong." severity ERROR;
+ assert I = TO_UINT(file_rd_data)
+ report "Read data is wrong."
+ severity ERROR;
end loop;
-- Write/Read
@@ -154,7 +156,9 @@ begin
mmf_mm_bus_wr(c_reg_r_w_dc_file_pathname, v_addr, I, mm_clk);
proc_common_wait_some_cycles(mm_clk, c_cross_nof_mm_clk);
mmf_mm_bus_rd(c_reg_r_w_dc_file_pathname, c_mem_reg.latency, v_addr, file_rd_data, mm_clk);
- assert TO_UINT(file_wr_data) = TO_UINT(file_rd_data) report "Write/read data is wrong." severity ERROR;
+ assert TO_UINT(file_wr_data) = TO_UINT(file_rd_data)
+ report "Write/read data is wrong."
+ severity ERROR;
end loop;
proc_common_gen_pulse(mm_clk, get_now);
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
index f939920bf7..04211c3ba2 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
@@ -140,7 +140,8 @@ begin
proc_common_wait_some_cycles(mm_clk, c_read_latency);
v_rddata := TO_UINT(stimuli_miso.rddata(c_data_w - 1 downto 0));
if v_rddata /= v_expdata then
- report "Error! Readvalue is not as expected" severity ERROR;
+ report "Error! Readvalue is not as expected"
+ severity ERROR;
end if;
v_expdata := v_expdata + 1;
end loop;
diff --git a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
index 30664c795f..ca3704e486 100644
--- a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
@@ -217,7 +217,9 @@ package body reorder_pkg is
-- index v_out becomes input value at index v_in
v_in := (blk * nof_data_per_block + dat) * nof_words_per_data + wi;
v_out := (dat * nof_blocks_per_packet + blk) * nof_words_per_data + wi;
- assert v_out = v_ch report "Wrong index in func_reorder_transpose_indices()" severity failure;
+ assert v_out = v_ch
+ report "Wrong index in func_reorder_transpose_indices()"
+ severity failure;
v_arr(v_out) := v_in;
v_ch := v_ch + 1;
end loop;
@@ -266,7 +268,9 @@ package body reorder_pkg is
nof_words_per_data);
variable v_list : t_slv_8_arr(packet_list'range);
begin
- assert c_nof_ch = packet_list'length report "Wrong packet_list length" severity error;
+ assert c_nof_ch = packet_list'length
+ report "Wrong packet_list length"
+ severity error;
for ch in 0 to c_nof_ch - 1 loop
v_list(ch) := packet_list(c_look_up_list(ch));
end loop;
diff --git a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
index e23186e439..d679040843 100644
--- a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
@@ -202,12 +202,24 @@ begin
---------------------------------------------------------------
-- CHECK IF PROVIDED GENERICS ARE ALLOWED.
---------------------------------------------------------------
- assert g_reorder_seq.wr_chunksize = g_reorder_seq.rd_nof_chunks * g_reorder_seq.rd_chunksize report "Total write configuration is different from total read configuration!!!" severity FAILURE;
- assert g_reorder_seq.nof_blocks >= g_reorder_seq.rd_chunksize report "The nof_blocks must be larger than or equal to the rd_chunksize!!!" severity FAILURE;
- assert g_reorder_seq.wr_chunksize rem g_data_w_ratio = 0 report "The wr_chunksize must divisible by the g_data_w_ratio!!!" severity FAILURE;
- assert g_reorder_seq.rd_chunksize rem g_data_w_ratio = 0 report "The rd_chunksize must divisible by the g_data_w_ratio!!!" severity FAILURE;
- assert g_reorder_seq.gapsize rem g_data_w_ratio = 0 report "The gapsize must divisible by the g_data_w_ratio!!!" severity FAILURE;
- assert g_reorder_seq.nof_blocks rem g_data_w_ratio = 0 report "The nof_blocks must divisible by the g_data_w_ratio!!!" severity FAILURE;
+ assert g_reorder_seq.wr_chunksize = g_reorder_seq.rd_nof_chunks * g_reorder_seq.rd_chunksize
+ report "Total write configuration is different from total read configuration!!!"
+ severity FAILURE;
+ assert g_reorder_seq.nof_blocks >= g_reorder_seq.rd_chunksize
+ report "The nof_blocks must be larger than or equal to the rd_chunksize!!!"
+ severity FAILURE;
+ assert g_reorder_seq.wr_chunksize rem g_data_w_ratio = 0
+ report "The wr_chunksize must divisible by the g_data_w_ratio!!!"
+ severity FAILURE;
+ assert g_reorder_seq.rd_chunksize rem g_data_w_ratio = 0
+ report "The rd_chunksize must divisible by the g_data_w_ratio!!!"
+ severity FAILURE;
+ assert g_reorder_seq.gapsize rem g_data_w_ratio = 0
+ report "The gapsize must divisible by the g_data_w_ratio!!!"
+ severity FAILURE;
+ assert g_reorder_seq.nof_blocks rem g_data_w_ratio = 0
+ report "The nof_blocks must divisible by the g_data_w_ratio!!!"
+ severity FAILURE;
p_comb : process(r, dp_rst, done)
variable v : reg_type;
diff --git a/libraries/base/reorder/tb/vhdl/reorder_pkg_test.vhd b/libraries/base/reorder/tb/vhdl/reorder_pkg_test.vhd
index e6995c2396..9564b76a2d 100644
--- a/libraries/base/reorder/tb/vhdl/reorder_pkg_test.vhd
+++ b/libraries/base/reorder/tb/vhdl/reorder_pkg_test.vhd
@@ -73,7 +73,9 @@ architecture tb of reorder_pkg_test is
g_nof_words_per_data);
begin
- assert c_exp_addresses_arr = c_impl_addresses_arr report "Wrong func_reorder_transpose_indices_impl()" severity failure;
+ assert c_exp_addresses_arr = c_impl_addresses_arr
+ report "Wrong func_reorder_transpose_indices_impl()"
+ severity failure;
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -112,10 +114,14 @@ begin
if rising_edge(clk) then
if in_val = '1' then
-- Only when valid expect that out_address = exp_address
- assert out_address = exp_address report "Wrong transpose address" severity error;
+ assert out_address = exp_address
+ report "Wrong transpose address"
+ severity error;
end if;
-- Always expect that out_address_lu = out_address
- assert out_address_lu = out_address report "Wrong transpose_lu address" severity error;
+ assert out_address_lu = out_address
+ report "Wrong transpose_lu address"
+ severity error;
end if;
end process;
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
index 126bfc83b1..d7b26cceab 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
@@ -262,13 +262,25 @@ begin
p_verify_out_sosi : process(clk)
begin
if rising_edge(clk) then
- assert dly_out_sosi_arr(O).valid = exp_sosi_arr(O).valid report "Wrong out_sosi.valid" severity ERROR;
- assert dly_out_sosi_arr(O).sop = exp_sosi_arr(O).sop report "Wrong out_sosi.sop" severity ERROR;
- assert dly_out_sosi_arr(O).eop = exp_sosi_arr(O).eop report "Wrong out_sosi.eop" severity ERROR;
- assert dly_out_sosi_arr(O).sync = exp_sosi_arr(O).sync report "Wrong out_sosi.sync" severity ERROR;
+ assert dly_out_sosi_arr(O).valid = exp_sosi_arr(O).valid
+ report "Wrong out_sosi.valid"
+ severity ERROR;
+ assert dly_out_sosi_arr(O).sop = exp_sosi_arr(O).sop
+ report "Wrong out_sosi.sop"
+ severity ERROR;
+ assert dly_out_sosi_arr(O).eop = exp_sosi_arr(O).eop
+ report "Wrong out_sosi.eop"
+ severity ERROR;
+ assert dly_out_sosi_arr(O).sync = exp_sosi_arr(O).sync
+ report "Wrong out_sosi.sync"
+ severity ERROR;
if exp_sosi_arr(O).valid = '1' then
- assert dly_out_sosi_arr(O).re = exp_sosi_arr(O).re report "Wrong out_sosi.re" severity ERROR;
- assert dly_out_sosi_arr(O).im = exp_sosi_arr(O).im report "Wrong out_sosi.im" severity ERROR;
+ assert dly_out_sosi_arr(O).re = exp_sosi_arr(O).re
+ report "Wrong out_sosi.re"
+ severity ERROR;
+ assert dly_out_sosi_arr(O).im = exp_sosi_arr(O).im
+ report "Wrong out_sosi.im"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
index 88d237b1b3..0477f28cea 100644
--- a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
+++ b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
@@ -92,11 +92,15 @@ begin
proc_mem_mm_bus_rd(c_mm_addr_transport_nof_hops, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response = 11 report "wrong c_mm_addr_transport_nof_hops" severity ERROR;
+ assert mm_natural_response = 11
+ report "wrong c_mm_addr_transport_nof_hops"
+ severity ERROR;
proc_mem_mm_bus_rd(c_mm_addr_lane_direction, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1);
- assert mm_natural_response /= 1 report "wrong lane_direction (not read only)" severity ERROR;
+ assert mm_natural_response /= 1
+ report "wrong lane_direction (not read only)"
+ severity ERROR;
proc_common_wait_some_cycles(mm_clk, 100);
tb_mm_reg_end <= '1';
@@ -108,8 +112,12 @@ begin
begin
proc_common_wait_until_high(mm_clk, tb_mm_reg_end); -- wait for p_mm_reg_stimuli done
- assert TO_UINT(lane_info.transport_nof_hops) = 11 report "wrong lane_info.transport_nof_hops value" severity ERROR;
- assert lane_info.lane_direction = '0' report "wrong lane_info.lane_direction value" severity ERROR;
+ assert TO_UINT(lane_info.transport_nof_hops) = 11
+ report "wrong lane_info.transport_nof_hops value"
+ severity ERROR;
+ assert lane_info.lane_direction = '0'
+ report "wrong lane_info.lane_direction value"
+ severity ERROR;
proc_common_wait_some_cycles(mm_clk, 100);
tb_end <= '1';
diff --git a/libraries/base/sens/tb/vhdl/tb_sens.vhd b/libraries/base/sens/tb/vhdl/tb_sens.vhd
index db6ed53a02..0047876169 100644
--- a/libraries/base/sens/tb/vhdl/tb_sens.vhd
+++ b/libraries/base/sens/tb/vhdl/tb_sens.vhd
@@ -88,7 +88,8 @@ begin
proc_common_wait_some_cycles(clk, 10);
for I in sens_data_bytes'range loop
if TO_UINT(sens_data_bytes(I)) /= exp_data_bytes(I) then
- report "Unexpected I2C read sensors result." severity ERROR;
+ report "Unexpected I2C read sensors result."
+ severity ERROR;
exit;
end if;
end loop;
diff --git a/libraries/base/tst/src/vhdl/tst_input.vhd b/libraries/base/tst/src/vhdl/tst_input.vhd
index fbfbf67229..6ade96374b 100644
--- a/libraries/base/tst/src/vhdl/tst_input.vhd
+++ b/libraries/base/tst/src/vhdl/tst_input.vhd
@@ -286,7 +286,8 @@ begin
when others =>
-- unkown state.
- report "unknown state" severity ERROR;
+ report "unknown state"
+ severity ERROR;
nxt_cycle_state := s_idle;
end case;
end loop;
diff --git a/libraries/base/uth/src/vhdl/uth_rx.vhd b/libraries/base/uth/src/vhdl/uth_rx.vhd
index 6d186c500d..a7f844e6ab 100644
--- a/libraries/base/uth/src/vhdl/uth_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx.vhd
@@ -308,7 +308,9 @@ begin
timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
- assert not(rising_edge(clk) and timeout_evt = '1') report "uth_rx(rtl_adapt) timeout occurred!" severity WARNING;
+ assert not(rising_edge(clk) and timeout_evt = '1')
+ report "uth_rx(rtl_adapt) timeout occurred!"
+ severity WARNING;
end generate;
-- XON/XOFF packet flow control
@@ -600,7 +602,9 @@ begin
timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
- assert not(rising_edge(clk) and timeout_evt = '1') report "uth_rx(rtl_hold) timeout occurred!" severity WARNING;
+ assert not(rising_edge(clk) and timeout_evt = '1')
+ report "uth_rx(rtl_hold) timeout occurred!"
+ severity WARNING;
end generate;
-- XON/XOFF packet flow control
diff --git a/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd b/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
index dfdd04816a..720c5a096b 100644
--- a/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
+++ b/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
@@ -76,7 +76,8 @@ architecture rtl of uth_tx_tlen is
constant c_len_arr : t_natural_arr(0 to g_nof_ch - 1) := g_len_arr;
begin
assert ceil_log2(g_len_max) < g_data_w
- report "uth_tx_tlen: g_len_max is too large to use tlen field as length" severity FAILURE;
+ report "uth_tx_tlen: g_len_max is too large to use tlen field as length"
+ severity FAILURE;
process(channel)
variable v_ch : natural;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth.vhd b/libraries/base/uth/tb/vhdl/tb_uth.vhd
index 357f71bd7d..9c4570c7c5 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth.vhd
@@ -128,7 +128,8 @@ begin
------------------------------------------------------------------------------
assert g_phy_link_valid_support = true
- report "TB_UTH : No valid support on the link, this requires using always active streaming control" severity NOTE;
+ report "TB_UTH : No valid support on the link, this requires using always active streaming control"
+ severity NOTE;
in_en <= '1' when g_phy_link_valid_support = false else
'1' when g_in_en = e_active else
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
index 1e550b7099..969ae6e556 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
@@ -221,7 +221,8 @@ begin
------------------------------------------------------------------------------
assert g_phy_link_valid_support = true
- report "TB_UTH_DP_PACKET : No valid support on the link, this requires using always active streaming control" severity NOTE;
+ report "TB_UTH_DP_PACKET : No valid support on the link, this requires using always active streaming control"
+ severity NOTE;
in_en <= '1' when g_phy_link_valid_support = false else
'1' when g_in_en = e_active else
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
index ddfce89f27..0d38444c1b 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
@@ -177,9 +177,11 @@ begin
for i in 0 to g_nof_inputs - 1 loop
if corr_accumulator_src_out_arr(i).valid = '1' then -- Compare against expected data
- assert corr_accumulator_src_out_arr(i).re = expected_data report "Expected real: " & slv_to_str(expected_data) & "; " & lf
+ assert corr_accumulator_src_out_arr(i).re = expected_data
+ report "Expected real: " & slv_to_str(expected_data) & "; " & lf
& " Actual real: " & slv_to_str(corr_accumulator_src_out_arr(i).re) severity ERROR;
- assert corr_accumulator_src_out_arr(i).im = expected_data report "Expected imag: " & slv_to_str(expected_data) & "; " & lf
+ assert corr_accumulator_src_out_arr(i).im = expected_data
+ report "Expected imag: " & slv_to_str(expected_data) & "; " & lf
& " Actual imag: " & slv_to_str(corr_accumulator_src_out_arr(i).im) severity ERROR;
if output_channel = g_nof_channels - 1 then
@@ -196,7 +198,9 @@ begin
-- Check the number of valid output cycles
if verify_done = '1' then
- assert out_valid_count = c_nof_integration_periods * g_nof_channels report "Incorrect number of valid output cycles" severity ERROR;
+ assert out_valid_count = c_nof_integration_periods * g_nof_channels
+ report "Incorrect number of valid output cycles"
+ severity ERROR;
end if;
end process;
diff --git a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
index 5b836e50f3..21584d7561 100644
--- a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
@@ -99,17 +99,27 @@ package body fft_pkg is
function fft_r2_parameter_asserts(g_fft : t_fft) return boolean is
begin
-- nof_points
- assert g_fft.nof_points = 2**true_log2(g_fft.nof_points) report "fft_r2: nof_points must be a power of 2" severity failure;
+ assert g_fft.nof_points = 2**true_log2(g_fft.nof_points)
+ report "fft_r2: nof_points must be a power of 2"
+ severity failure;
-- wb_factor
- assert g_fft.wb_factor = 2**true_log2(g_fft.wb_factor) report "fft_r2: wb_factor must be a power of 2" severity failure;
+ assert g_fft.wb_factor = 2**true_log2(g_fft.wb_factor)
+ report "fft_r2: wb_factor must be a power of 2"
+ severity failure;
-- use_reorder
if g_fft.use_reorder = false then
- assert g_fft.use_separate = false report "fft_r2 : without use_reorder there cannot be use_separate for two real inputs" severity failure;
- assert g_fft.use_fft_shift = false report "fft_r2 : without use_reorder there cannot be use_fft_shift for complex input" severity failure;
+ assert g_fft.use_separate = false
+ report "fft_r2 : without use_reorder there cannot be use_separate for two real inputs"
+ severity failure;
+ assert g_fft.use_fft_shift = false
+ report "fft_r2 : without use_reorder there cannot be use_fft_shift for complex input"
+ severity failure;
end if;
-- use_separate
if g_fft.use_separate = true then
- assert g_fft.use_fft_shift = false report "fft_r2 : with use_separate there cannot be use_fft_shift for two real inputs" severity failure;
+ assert g_fft.use_fft_shift = false
+ report "fft_r2 : with use_separate there cannot be use_fft_shift for two real inputs"
+ severity failure;
end if;
return true;
end;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
index 18b7abe7eb..64f7a2f1b3 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
@@ -263,10 +263,18 @@ begin
begin
if rst = '0' then
if rising_edge(clk) and out_val = '1' then
- assert ref_x_out_re_dly = x_out_re report "Error: wrong RTL result in X real path" severity error;
- assert ref_x_out_im_dly = x_out_im report "Error: wrong RTL result in X imag path" severity error;
- assert ref_y_out_re_dly = y_out_re report "Error: wrong RTL result in Y real path" severity error;
- assert ref_y_out_im_dly = y_out_im report "Error: wrong RTL result in Y imag path" severity error;
+ assert ref_x_out_re_dly = x_out_re
+ report "Error: wrong RTL result in X real path"
+ severity error;
+ assert ref_x_out_im_dly = x_out_im
+ report "Error: wrong RTL result in X imag path"
+ severity error;
+ assert ref_y_out_re_dly = y_out_re
+ report "Error: wrong RTL result in Y real path"
+ severity error;
+ assert ref_y_out_im_dly = y_out_im
+ report "Error: wrong RTL result in Y imag path"
+ severity error;
end if;
end if;
end process p_tester;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
index b1a979ee6a..8d67c94216 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
@@ -416,8 +416,12 @@ begin
begin
-- Wait until tb_end_dut
proc_common_wait_until_high(tb_clk, tb_end_dut);
- assert in_val_cnt > 0 report "Test did not run, no valid input data" severity error;
- assert out_val_cnt = in_val_cnt report "Unexpected number of valid output data" severity error;
+ assert in_val_cnt > 0
+ report "Test did not run, no valid input data"
+ severity error;
+ assert out_val_cnt = in_val_cnt
+ report "Unexpected number of valid output data"
+ severity error;
wait;
end process;
@@ -447,15 +451,27 @@ begin
-- p_verify_output
gen_verify_two_real : if not c_in_complex generate
- assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin report "Output data A real error" severity error;
- assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin report "Output data A imag error" severity error;
- assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin report "Output data B real error" severity error;
- assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin report "Output data B imag error" severity error;
+ assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin
+ report "Output data A real error"
+ severity error;
+ assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin
+ report "Output data A imag error"
+ severity error;
+ assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin
+ report "Output data B real error"
+ severity error;
+ assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin
+ report "Output data B imag error"
+ severity error;
end generate;
gen_verify_complex : if c_in_complex generate
- assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin report "Output data C real error" severity error;
- assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin report "Output data C imag error" severity error;
+ assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin
+ report "Output data C real error"
+ severity error;
+ assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin
+ report "Output data C imag error"
+ severity error;
end generate;
---------------------------------------------------------------
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 93d3ba3dd3..c38c890b40 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -360,14 +360,20 @@ begin
begin
-- Wait until tb_end_almost
proc_common_wait_until_high(clk, tb_end_almost);
- assert in_val_cnt > 0 report "Test did not run, no valid input data" severity error;
+ assert in_val_cnt > 0
+ report "Test did not run, no valid input data"
+ severity error;
-- The PFFT has a memory of 1 block, independent of use_reorder and use_separate, but without the
-- reorder buffer it outputs 1 sample more, because that is immediately available in a new block.
-- Ensure g_data_file_nof_lines is multiple of g_fft.nof_points.
if g_fft.use_reorder = true then
- assert out_val_cnt = in_val_cnt - c_nof_valid_per_block report "Unexpected number of valid output data" severity error;
+ assert out_val_cnt = in_val_cnt - c_nof_valid_per_block
+ report "Unexpected number of valid output data"
+ severity error;
else
- assert out_val_cnt = in_val_cnt - c_nof_valid_per_block + c_nof_channels report "Unexpected number of valid output data" severity error;
+ assert out_val_cnt = in_val_cnt - c_nof_valid_per_block + c_nof_channels
+ report "Unexpected number of valid output data"
+ severity error;
end if;
wait;
end process;
@@ -398,15 +404,27 @@ begin
-- p_verify_output
gen_verify_two_real : if not c_in_complex generate
- assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin report "Output data A real error" severity error;
- assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin report "Output data A imag error" severity error;
- assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin report "Output data B real error" severity error;
- assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin report "Output data B imag error" severity error;
+ assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin
+ report "Output data A real error"
+ severity error;
+ assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin
+ report "Output data A imag error"
+ severity error;
+ assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin
+ report "Output data B real error"
+ severity error;
+ assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin
+ report "Output data B imag error"
+ severity error;
end generate;
gen_verify_complex : if c_in_complex generate
- assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin report "Output data C real error" severity error;
- assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin report "Output data C imag error" severity error;
+ assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin
+ report "Output data C real error"
+ severity error;
+ assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin
+ report "Output data C imag error"
+ severity error;
end generate;
---------------------------------------------------------------
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
index 89835d3eeb..b71d0170b6 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
@@ -336,19 +336,27 @@ begin
begin
-- Wait until tb_end_almost
proc_common_wait_until_high(clk, tb_end_almost);
- assert in_val_cnt > 0 report "Test did not run, no valid input data" severity error;
+ assert in_val_cnt > 0
+ report "Test did not run, no valid input data"
+ severity error;
if g_fft.wb_factor = g_fft.nof_points then
-- Parallel FFT
- assert out_val_cnt = in_val_cnt report "Unexpected number of valid output data" severity error;
+ assert out_val_cnt = in_val_cnt
+ report "Unexpected number of valid output data"
+ severity error;
else
-- Wideband FFT
-- The PFFT has a memory of 1 block, independent of use_reorder and use_separate, but without the
-- reorder buffer it outputs 1 sample more, because that is immediately available in a new block.
-- Ensure g_data_file_nof_lines is multiple of g_fft.nof_points.
if g_fft.use_reorder = true then
- assert out_val_cnt = in_val_cnt - c_nof_valid_per_block report "Unexpected number of valid output data" severity error;
+ assert out_val_cnt = in_val_cnt - c_nof_valid_per_block
+ report "Unexpected number of valid output data"
+ severity error;
else
- assert out_val_cnt = in_val_cnt - c_nof_valid_per_block + c_nof_channels report "Unexpected number of valid output data" severity error;
+ assert out_val_cnt = in_val_cnt - c_nof_valid_per_block + c_nof_channels
+ report "Unexpected number of valid output data"
+ severity error;
end if;
end if;
wait;
@@ -397,15 +405,27 @@ begin
---------------------------------------------------------------
-- p_verify_output
gen_verify_two_real : if not c_in_complex generate
- assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin report "Output data A real error" severity error;
- assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin report "Output data A imag error" severity error;
- assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin report "Output data B real error" severity error;
- assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin report "Output data B imag error" severity error;
+ assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin
+ report "Output data A real error"
+ severity error;
+ assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin
+ report "Output data A imag error"
+ severity error;
+ assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin
+ report "Output data B real error"
+ severity error;
+ assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin
+ report "Output data B imag error"
+ severity error;
end generate;
gen_verify_complex : if c_in_complex generate
- assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin report "Output data C real error" severity error;
- assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin report "Output data C imag error" severity error;
+ assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin
+ report "Output data C real error"
+ severity error;
+ assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin
+ report "Output data C imag error"
+ severity error;
end generate;
---------------------------------------------------------------
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
index 7720437603..8a198c4563 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -239,8 +239,12 @@ begin
begin
if rst = '0' then
if rising_edge(clk) and out_val = '1' then
- assert buf_output_re(I) = out_dat_re report "Error: wrong RTL result in real path" severity error;
- assert buf_output_im(I) = out_dat_im report "Error: wrong RTL result in imag path" severity error;
+ assert buf_output_re(I) = out_dat_re
+ report "Error: wrong RTL result in real path"
+ severity error;
+ assert buf_output_im(I) = out_dat_im
+ report "Error: wrong RTL result in imag path"
+ severity error;
if(I = c_nof_channels * c_nof_points - 1 ) then
I := 0;
else
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
index a38cdfba65..70983eb993 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
@@ -195,8 +195,12 @@ begin
begin
if rst = '0' then
if rising_edge(clk) and out_val = '1' then
- assert buf_output_re(I) = out_dat_re report "Error: wrong RTL result in real path" severity ERROR;
- assert buf_output_im(I) = out_dat_im report "Error: wrong RTL result in imag path" severity ERROR;
+ assert buf_output_re(I) = out_dat_re
+ report "Error: wrong RTL result in real path"
+ severity ERROR;
+ assert buf_output_im(I) = out_dat_im
+ report "Error: wrong RTL result in imag path"
+ severity ERROR;
if(I = c_nof_points - 1 ) then
I := 0;
else
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
index 26a50b4369..7bc046c683 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -304,10 +304,16 @@ begin
if rising_edge(clk) then
if verify_en = '1' then
if exp_val = '1' then
- assert TO_SINT(out_a) = exp_a report "Wrong out_re" severity ERROR;
- assert TO_SINT(out_b) = exp_b report "Wrong out_im" severity ERROR;
+ assert TO_SINT(out_a) = exp_a
+ report "Wrong out_re"
+ severity ERROR;
+ assert TO_SINT(out_b) = exp_b
+ report "Wrong out_im"
+ severity ERROR;
end if;
- assert out_val = exp_val report "Wrong out_val" severity ERROR;
+ assert out_val = exp_val
+ report "Wrong out_val"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
index c021f0cdfb..36977e17fd 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
@@ -410,8 +410,12 @@ begin
-- Output the expected BST array
expected_sst_arr <= v_acc_pwr_arr;
v_acc_pwr_arr := (others => (others => '0'));
- assert expected_sst_arr = result_sst_arr report "Output statistics error" severity error;
- assert expected_sst_arr /= result_sst_arr report "Output statistics OK!!!!" severity note;
+ assert expected_sst_arr = result_sst_arr
+ report "Output statistics error"
+ severity error;
+ assert expected_sst_arr /= result_sst_arr
+ report "Output statistics OK!!!!"
+ severity note;
else
v_int_time := v_int_time + 1;
end if;
@@ -432,10 +436,16 @@ begin
if rising_edge(clk) then
if out_val = '1' then
-- only write when out_val='1', because then the file is independent of cycles with invalid out_dat
- assert out_sync = gold_sync report "Output sync error" severity error;
+ assert out_sync = gold_sync
+ report "Output sync error"
+ severity error;
for I in 0 to g_fft.wb_factor - 1 loop
- assert TO_SINT(out_re_arr(I)) = gold_re_arr(I) report "Output real data error" severity error;
- assert TO_SINT(out_im_arr(I)) = gold_im_arr(I) report "Output imag data error" severity error;
+ assert TO_SINT(out_re_arr(I)) = gold_re_arr(I)
+ report "Output real data error"
+ severity error;
+ assert TO_SINT(out_im_arr(I)) = gold_im_arr(I)
+ report "Output imag data error"
+ severity error;
end loop;
end if;
end if;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index a46728b9cf..ac59e87c8c 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -350,7 +350,9 @@ begin
begin
-- Wait until the coeff dat file and coeff MIF files have been read
proc_common_wait_until_low(clk, rst);
- assert mif_dat_arr = ref_dat_arr report "Coefs file does not match coefs MIF files" severity error;
+ assert mif_dat_arr = ref_dat_arr
+ report "Coefs file does not match coefs MIF files"
+ severity error;
wait;
end process;
@@ -358,7 +360,9 @@ begin
begin
-- Wait until the coeff dat file has been read and the coeff have been read via MM
proc_common_wait_until_high(clk, tb_end_almost);
- assert read_coefs_arr = ref_coefs_arr report "Coefs file does not match coefs read via MM" severity error;
+ assert read_coefs_arr = ref_coefs_arr
+ report "Coefs file does not match coefs read via MM"
+ severity error;
wait;
end process;
@@ -392,7 +396,9 @@ begin
begin
-- Wait until tb_end_almost to avoid that the Error message gets lost in earlier messages
proc_common_wait_until_high(clk, tb_end_almost);
- assert g_fil_ppf.out_dat_w >= g_fil_ppf.coef_dat_w report "Output data width too small for coefficients" severity error;
+ assert g_fil_ppf.out_dat_w >= g_fil_ppf.coef_dat_w
+ report "Output data width too small for coefficients"
+ severity error;
wait;
end process;
@@ -401,8 +407,12 @@ begin
-- Wait until tb_end_almost
proc_common_wait_until_high(clk, tb_end_almost);
-- The filter has a latency of 1 tap, so there remains in_dat for tap in the filter
- assert in_val_cnt > 0 report "Test did not run, no valid input data" severity error;
- assert out_val_cnt = in_val_cnt - c_nof_data_per_tap report "Unexpected number of valid output data coefficients" severity error;
+ assert in_val_cnt > 0
+ report "Test did not run, no valid input data"
+ severity error;
+ assert out_val_cnt = in_val_cnt - c_nof_data_per_tap
+ report "Unexpected number of valid output data coefficients"
+ severity error;
wait;
end process;
@@ -424,7 +434,9 @@ begin
end if;
for S in 0 to g_fil_ppf.nof_streams - 1 loop
-- all streams carry the same data
- assert TO_SINT(out_dat((S + 1) * g_fil_ppf.out_dat_w - 1 downto S * g_fil_ppf.out_dat_w)) = v_coeff report "Output data error" severity error;
+ assert TO_SINT(out_dat((S + 1) * g_fil_ppf.out_dat_w - 1 downto S * g_fil_ppf.out_dat_w)) = v_coeff
+ report "Output data error"
+ severity error;
end loop;
end if;
end if;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
index 0e166466f4..ddebddcfea 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
@@ -298,7 +298,9 @@ begin
begin
-- Wait until tb_end_almost to avoid that the Error message gets lost in earlier messages
proc_common_wait_until_high(clk, tb_end_almost);
- assert g_fil_ppf.out_dat_w >= g_fil_ppf.coef_dat_w report "Output data width too small for coefficients" severity error;
+ assert g_fil_ppf.out_dat_w >= g_fil_ppf.coef_dat_w
+ report "Output data width too small for coefficients"
+ severity error;
wait;
end process;
@@ -307,8 +309,12 @@ begin
-- Wait until tb_end_almost
proc_common_wait_until_high(clk, tb_end_almost);
-- The filter has a latency of 1 tap, so there remains in_dat for tap in the filter
- assert in_val_cnt > 0 report "Test did not run, no valid input data" severity error;
- assert out_val_cnt = in_val_cnt - c_nof_valid_per_tap report "Unexpected number of valid output data coefficients" severity error;
+ assert in_val_cnt > 0
+ report "Test did not run, no valid input data"
+ severity error;
+ assert out_val_cnt = in_val_cnt - c_nof_valid_per_tap
+ report "Unexpected number of valid output data coefficients"
+ severity error;
wait;
end process;
@@ -344,7 +350,9 @@ begin
end if;
for S in 0 to g_fil_ppf.nof_streams - 1 loop
-- all streams carry the same data
- assert TO_SINT(out_dat_arr(P * g_fil_ppf.nof_streams + S)) = v_coeff report "Output data error" severity error;
+ assert TO_SINT(out_dat_arr(P * g_fil_ppf.nof_streams + S)) = v_coeff
+ report "Output data error"
+ severity error;
end loop;
end loop;
end if;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index 1e2c17cee9..8a7c05f079 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -312,7 +312,9 @@ begin
wait for 1 ns;
-- Wait until tb_end_almost to avoid that the Error message gets lost in earlier messages
proc_common_wait_until_high(clk, tb_end_almost);
- assert coefs_dat_arr = coefs_ref_arr report "Unexpected PFIR coefficients." severity error;
+ assert coefs_dat_arr = coefs_ref_arr
+ report "Unexpected PFIR coefficients."
+ severity error;
wait;
end process;
@@ -324,8 +326,12 @@ begin
-- Wait until tb_end_almost
proc_common_wait_until_high(clk, tb_end_almost);
-- The filter has a latency of 1 tap, so there remains in_dat for tap in the filter
- assert in_val_cnt > 0 report "Test did not run, no valid input data" severity error;
- assert out_val_cnt = in_val_cnt - c_nof_valid_per_block report "Unexpected number of valid output data" severity error;
+ assert in_val_cnt > 0
+ report "Test did not run, no valid input data"
+ severity error;
+ assert out_val_cnt = in_val_cnt - c_nof_valid_per_block
+ report "Unexpected number of valid output data"
+ severity error;
wait;
end process;
@@ -366,7 +372,9 @@ begin
if S = 1 then
-- stream 1 carries zero data
v_exp_dat := 0;
- assert v_out_dat = v_exp_dat report "Output data error (stream 1 not zero)" severity error;
+ assert v_out_dat = v_exp_dat
+ report "Output data error (stream 1 not zero)"
+ severity error;
else
-- stream 0 and all other streams >= 2 carry the same data
v_exp_dat := expected_data_arr(vI * g_fil_ppf.wb_factor + P);
diff --git a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
index 65f193f20a..f4313daa89 100644
--- a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
@@ -130,8 +130,12 @@ architecture str of fringe_stop_unit is
signal result_re : std_logic_vector(c_product_w - 1 downto 0);
signal result_im : std_logic_vector(c_product_w - 1 downto 0);
begin
- assert dbg_lookup_real_dc = 0 report "Fringe stop lookup COS must have DC = 0" severity ERROR;
- assert dbg_lookup_imag_dc = 0 report "Fringe stop lookup SIN must have DC = 0" severity ERROR;
+ assert dbg_lookup_real_dc = 0
+ report "Fringe stop lookup COS must have DC = 0"
+ severity ERROR;
+ assert dbg_lookup_imag_dc = 0
+ report "Fringe stop lookup SIN must have DC = 0"
+ severity ERROR;
------------------------------------------------------------------------------
-- Input registers
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
index fd571740a7..e21abaebcc 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
@@ -418,8 +418,12 @@ begin
begin
if rising_edge(dp_clk) then
if r.out_sosi_arr(0).valid = '1' then
- assert TO_SINT(r.out_sosi_arr(0).re) = r.ref_re report "Error: wrong result in real part DUT" severity ERROR;
- assert TO_SINT(r.out_sosi_arr(0).im) = r.ref_im report "Error: wrong result in imaginary part DUT" severity ERROR;
+ assert TO_SINT(r.out_sosi_arr(0).re) = r.ref_re
+ report "Error: wrong result in real part DUT"
+ severity ERROR;
+ assert TO_SINT(r.out_sosi_arr(0).im) = r.ref_im
+ report "Error: wrong result in imaginary part DUT"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
index 7fd9d4c2a1..cc9ef3a76f 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
@@ -211,9 +211,13 @@ begin
mmf_mm_bus_wr(c_mm_file_ram_fringe_stop_step, I, c_in_step2, mm_clk);
-- read back MM page
mmf_mm_bus_rd(c_mm_file_ram_fringe_stop_offset, I, rd_data, mm_clk);
- assert TO_UINT(rd_data) = c_in_offset report "Wrong fringe stop offset readback value" severity ERROR;
+ assert TO_UINT(rd_data) = c_in_offset
+ report "Wrong fringe stop offset readback value"
+ severity ERROR;
mmf_mm_bus_rd(c_mm_file_ram_fringe_stop_step, I, rd_data, mm_clk);
- assert TO_UINT(rd_data) = c_in_step2 report "Wrong fringe stop step readback value" severity ERROR;
+ assert TO_UINT(rd_data) = c_in_step2
+ report "Wrong fringe stop step readback value"
+ severity ERROR;
end loop;
-- write to last address c_nof_channels-1 will cause page swap at in_sosi.sync
@@ -223,7 +227,9 @@ begin
tb_state <= "1-st page swap";
-- read back power up default step value to verify page swap
mmf_mm_bus_rd(c_mm_file_ram_fringe_stop_step, 0, rd_data, mm_clk);
- assert TO_UINT(rd_data) = 0 report "Wrong power up default step readback value" severity ERROR;
+ assert TO_UINT(rd_data) = 0
+ report "Wrong power up default step readback value"
+ severity ERROR;
for I in 0 to c_nof_channels - 1 loop
-- write next page
@@ -239,7 +245,9 @@ begin
verify_out_en <= '1';
-- read back first written step value to verify page swap
mmf_mm_bus_rd(c_mm_file_ram_fringe_stop_step, 0, rd_data, mm_clk);
- assert TO_UINT(rd_data) = c_in_step2 report "Wrong first written step readback value" severity ERROR;
+ assert TO_UINT(rd_data) = c_in_step2
+ report "Wrong first written step readback value"
+ severity ERROR;
-- no write to last address c_nof_channels-1, so no page swap at in_sosi.sync
-- wait until begin of sync interval
@@ -248,9 +256,12 @@ begin
tb_state <= "no page swap ";
-- read back second written step value to verify page swap
mmf_mm_bus_rd(c_mm_file_ram_fringe_stop_step, 0, rd_data, mm_clk);
- assert TO_UINT(rd_data) = c_in_step2 report "Wrong first written step readback value, unexpected page swap" severity ERROR;
+ assert TO_UINT(rd_data) = c_in_step2
+ report "Wrong first written step readback value, unexpected page swap"
+ severity ERROR;
- report "MM done " & integer'image(g_tb_index) severity NOTE;
+ report "MM done " & integer'image(g_tb_index)
+ severity NOTE;
-------------------------------------------------------------------------
-- Test FS step for one phasor period
@@ -258,21 +269,25 @@ begin
-- Wait for at least one fringe stop phase period
v_data := out_re;
proc_common_wait_until_value(v_data + 1, dp_clk, out_re); -- wait until out_re+1, initial (out_re, out_im) = (-c_in_amplitude, 0)
- report "Phasor start " & integer'image(g_tb_index) severity NOTE;
+ report "Phasor start " & integer'image(g_tb_index)
+ severity NOTE;
tb_state <= "Phasor start ";
proc_common_wait_until_evt(dp_clk, out_re); -- wait until out_re+1 changes
proc_common_wait_until_value(v_data, dp_clk, out_re); -- wait until out_re again
proc_common_wait_until_value(v_data + 1, dp_clk, out_re); -- wait until out_re+1 again
- report "Phasor end " & integer'image(g_tb_index) severity NOTE;
+ report "Phasor end " & integer'image(g_tb_index)
+ severity NOTE;
tb_state <= "Phasor end ";
-- Wait some more sync intervals
proc_common_wait_some_cycles(dp_clk, c_in_sync_interval * 3);
- report "tb_almost_end " & integer'image(g_tb_index) severity NOTE;
+ report "tb_almost_end " & integer'image(g_tb_index)
+ severity NOTE;
tb_almost_end <= '1';
proc_common_wait_some_cycles(dp_clk, 10);
- report "tb_end " & integer'image(g_tb_index) severity NOTE;
+ report "tb_end " & integer'image(g_tb_index)
+ severity NOTE;
tb_end <= '1';
end if;
wait;
@@ -335,21 +350,37 @@ begin
if g_mm_stimuli_enable then
proc_common_wait_until_high(dp_clk, verify_out_en);
-- Verify expected initial FS output (c_phi_minus_sign has no influence on initial FS output, because out_im=-out_im=0)
- assert out_re = c_in_amplitude report "Wrong first out_re" severity ERROR;
- assert out_im = 0 report "Wrong first out_im" severity ERROR;
+ assert out_re = c_in_amplitude
+ report "Wrong first out_re"
+ severity ERROR;
+ assert out_im = 0
+ report "Wrong first out_im"
+ severity ERROR;
-- Assume that output is sinusoid if the output changes smoothly and has reached both -c_in_amplitude and +c_in_amplitude
-- . Verify that FS output changes smoothly
while tb_almost_end = '0' loop
proc_common_wait_some_cycles(dp_clk, 1);
- assert out_re = out_re_prev or out_re = out_re_prev - 1 or out_re = out_re_prev + 1 report "Too large change in out_re" severity ERROR;
- assert out_im = out_im_prev or out_im = out_im_prev - 1 or out_im = out_im_prev + 1 report "Too large change in out_im" severity ERROR;
+ assert out_re = out_re_prev or out_re = out_re_prev - 1 or out_re = out_re_prev + 1
+ report "Too large change in out_re"
+ severity ERROR;
+ assert out_im = out_im_prev or out_im = out_im_prev - 1 or out_im = out_im_prev + 1
+ report "Too large change in out_im"
+ severity ERROR;
end loop;
-- . Verify that output has reached +-c_in_amplitude
- assert out_re_max = c_in_amplitude report "Wrong out_re_max" severity ERROR;
- assert out_im_max = c_in_amplitude report "Wrong out_im_max" severity ERROR;
- assert out_re_min = -c_in_amplitude report "Wrong out_re_min" severity ERROR;
- assert out_im_min = -c_in_amplitude report "Wrong out_im_min" severity ERROR;
+ assert out_re_max = c_in_amplitude
+ report "Wrong out_re_max"
+ severity ERROR;
+ assert out_im_max = c_in_amplitude
+ report "Wrong out_im_max"
+ severity ERROR;
+ assert out_re_min = -c_in_amplitude
+ report "Wrong out_re_min"
+ severity ERROR;
+ assert out_im_min = -c_in_amplitude
+ report "Wrong out_im_min"
+ severity ERROR;
end if;
wait;
end process;
@@ -379,9 +410,15 @@ begin
-- Report
proc_common_wait_some_cycles(dp_clk, 10);
- assert out_re_sum = 0 report "Fringe stop real sum must have DC = 0 over one period." severity ERROR;
- assert out_im_sum = 0 report "Fringe stop imag sum must have DC = 0 over one period." severity ERROR;
- assert vPeriod = c_exp_nof_steps_per_period report "Unexpected fringe stop period " & int_to_str(vPeriod) & " /= " & int_to_str(c_exp_nof_steps_per_period) severity ERROR;
+ assert out_re_sum = 0
+ report "Fringe stop real sum must have DC = 0 over one period."
+ severity ERROR;
+ assert out_im_sum = 0
+ report "Fringe stop imag sum must have DC = 0 over one period."
+ severity ERROR;
+ assert vPeriod = c_exp_nof_steps_per_period
+ report "Unexpected fringe stop period " & int_to_str(vPeriod) & " /= " & int_to_str(c_exp_nof_steps_per_period)
+ severity ERROR;
end if;
wait;
end process;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
index 4e003ef01b..d6b9c13e84 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
@@ -295,19 +295,35 @@ begin
if rising_edge(dp_clk) then
if diag_out_valid = '1' then
if g_nof_int = 8 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
--REPORT "I exp = " & integer'image(to_uint(s_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in Q out DUT" severity ERROR;
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_word_w), c_lsb_w))
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_word_w), c_lsb_w))
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_word_w), c_lsb_w))
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
elsif g_nof_int = 16 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
--REPORT "I expected = " & integer'image(to_uint(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in Q out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_word_w), c_lsb_w))
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
--REPORT "Q expected = " & integer'image(to_sint(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w)));
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_word_w), c_lsb_w))
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_word_w), c_lsb_w))
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
end if;
report "I = " & integer'image(to_uint(i_out.data)) & ", Q = " & integer'image(to_sint(q_out.data)) &
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
index a6c8893509..d7cae96865 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
@@ -234,36 +234,48 @@ begin
if diag_out_valid = '1' then
if g_use_accum = true and g_nof_int = 8 then
assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
- report "Error: wrong result in I out DUT" severity ERROR;
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in Q out DUT" severity ERROR;
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in U out DUT" severity ERROR;
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in V out DUT" severity ERROR;
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
--REPORT "I exp = " & integer'image(to_uint(s_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
elsif g_use_accum = true and g_nof_int = 16 then
assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
- report "Error: wrong result in I out DUT" severity ERROR;
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in Q out DUT" severity ERROR;
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in U out DUT" severity ERROR;
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in V out DUT" severity ERROR;
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
--REPORT "I expected = " & integer'image(to_uint(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
--REPORT "Q expected = " & integer'image(to_sint(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w)));
elsif g_use_accum = false then
assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_noint_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
- report "Error: wrong result in I out DUT" severity ERROR;
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_noint_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in Q out DUT" severity ERROR;
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_noint_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in U out DUT" severity ERROR;
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_noint_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
- report "Error: wrong result in V out DUT" severity ERROR;
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
--REPORT "U expected = " & integer'image(to_sint(s_round(TO_SVEC(u_noint_exp_arr(v_index),c_fsd_w), c_lsb_w, TRUE)));
--REPORT "U actual = " & integer'image(to_sint(u_out.data));
end if;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
index a411df293f..e164712465 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
@@ -198,19 +198,35 @@ begin
if rising_edge(dp_clk) then
if diag_out_valid = '1' then
if g_nof_int = 8 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, c_clip, c_even)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, c_clip, c_even))
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
--REPORT "I exp = " & integer'image(to_uint(s_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w), c_lsb_w, c_clip)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in Q out DUT" severity ERROR;
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even))
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even))
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even))
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
elsif g_nof_int = 16 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, c_clip, c_even)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, c_clip, c_even))
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
--REPORT "I expected = " & integer'image(to_uint(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w), c_lsb_w, c_clip, c_even)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in Q out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even))
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
--REPORT "Q expected = " & integer'image(to_sint(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)));
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even))
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even))
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
end if;
report "I = " & integer'image(to_uint(i_out.data)) & ", Q = " & integer'image(to_sint(q_out.data)) &
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
index 5a42db7fff..48b0d8f3a7 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
@@ -282,13 +282,17 @@ begin
v_expected_iab := TO_SVEC(to_sint(v_expected_iquv) * c_nof_iab_int, c_fsd_w);
end if;
assert TO_UINT(i_out.data) = TO_UINT(u_round(i_expected_iab, c_lsb_w, true))
- report "Error: wrong result in I out DUT" severity ERROR;
+ report "Error: wrong result in I out DUT"
+ severity ERROR;
assert TO_SINT(q_out.data) = TO_SINT(s_round(q_expected_iab, c_lsb_w, true))
- report "Error: wrong result in Q out DUT" severity ERROR;
+ report "Error: wrong result in Q out DUT"
+ severity ERROR;
assert TO_SINT(u_out.data) = TO_SINT(s_round(u_expected_iab, c_lsb_w, true))
- report "Error: wrong result in U out DUT" severity ERROR;
+ report "Error: wrong result in U out DUT"
+ severity ERROR;
assert TO_SINT(v_out.data) = TO_SINT(s_round(v_expected_iab, c_lsb_w, true))
- report "Error: wrong result in V out DUT" severity ERROR;
+ report "Error: wrong result in V out DUT"
+ severity ERROR;
--REPORT "I expected IQUV = " & integer'image(to_uint(i_expected_iquv));
--REPORT "I expected IAB = " & integer'image(to_uint(u_round(i_expected_iab, c_lsb_w, TRUE)));
--REPORT "I actual = " & integer'image(TO_UINT(i_out.data));
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
index 5f7b31c5ce..af88a73b74 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
@@ -94,5 +94,7 @@ begin
end process;
end generate;
- assert g_lat <= 1 report "rTwoWeights : g_lat must be 0 or 1" severity failure;
+ assert g_lat <= 1
+ report "rTwoWeights : g_lat must be 0 or 1"
+ severity failure;
end rtl;
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
index b0b5384066..8d4db8548e 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
@@ -331,9 +331,15 @@ begin
if rising_edge(clk) then
if out_val = '1' and gold_index <= gold_index_max then
-- only write when out_val='1', because then the file is independent of cycles with invalid out_dat
- assert out_sync = gold_sync report "Output sync error" severity error;
- assert TO_SINT(out_re) = gold_re report "Output real data error" severity error;
- assert TO_SINT(out_im) = gold_im report "Output imag data error" severity error;
+ assert out_sync = gold_sync
+ report "Output sync error"
+ severity error;
+ assert TO_SINT(out_re) = gold_re
+ report "Output real data error"
+ severity error;
+ assert TO_SINT(out_im) = gold_im
+ report "Output imag data error"
+ severity error;
end if;
end if;
end process;
diff --git a/libraries/dsp/si/tb/vhdl/tb_si.vhd b/libraries/dsp/si/tb/vhdl/tb_si.vhd
index a55ad221f1..66d297c017 100755
--- a/libraries/dsp/si/tb/vhdl/tb_si.vhd
+++ b/libraries/dsp/si/tb/vhdl/tb_si.vhd
@@ -228,15 +228,20 @@ begin
if v_even /= -1 * v_odd then
if not (v_clip_even = '1') then
if not (v_clip_odd = '1') then
- report "Wrong negate value at valid (v_even = " & int_to_str(v_even) & " v_odd = " & int_to_str(v_odd) severity ERROR;
+ report "Wrong negate value at valid (v_even = " & int_to_str(v_even) & " v_odd = " & int_to_str(v_odd)
+ severity ERROR;
end if;
end if;
end if;
end if;
else
-- Verify expected number of clip_even (when in_sop is at even) and clip_odd (when in_sop is at odd)
- assert cnt_even = 4 report "Wrong number of expected clipped c_min to c_max at even index" severity ERROR;
- assert cnt_odd = 12 report "Wrong number of expected clipped c_min to c_max at odd index" severity ERROR;
+ assert cnt_even = 4
+ report "Wrong number of expected clipped c_min to c_max at even index"
+ severity ERROR;
+ assert cnt_odd = 12
+ report "Wrong number of expected clipped c_min to c_max at odd index"
+ severity ERROR;
wait;
end if;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
index 72d545e3f5..6c57ffd469 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
@@ -238,7 +238,9 @@ begin
for j in 0 to g_nof_bins - 1 loop
proc_common_wait_until_high(mm_clk, histogram_valid);
if i = 0 then -- Sync period 0: we expect RAM to contain zeros
- assert histogram_data = 0 report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")" severity ERROR;
+ assert histogram_data = 0
+ report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")"
+ severity ERROR;
else -- Sync period 1 onwards
v_expected_ram_content_counter := c_expected_ram_content_counter;
if ver_long_sync_interval and j = 0 then
@@ -249,7 +251,9 @@ begin
v_expected_ram_content_counter := 0;
end if;
-- Check counter data: bin values remain the same every sync
- assert histogram_data = v_expected_ram_content_counter report "RAM contains wrong bin count (expected " & integer'image(v_expected_ram_content_counter) & ", actual " & integer'image(histogram_data) & ")" severity ERROR;
+ assert histogram_data = v_expected_ram_content_counter
+ report "RAM contains wrong bin count (expected " & integer'image(v_expected_ram_content_counter) & ", actual " & integer'image(histogram_data) & ")"
+ severity ERROR;
end if;
sum_of_bins <= sum_of_bins + histogram_data; -- Keep the sum of all bins
proc_common_wait_some_cycles(mm_clk, 1);
@@ -262,7 +266,9 @@ begin
if ver_long_sync_interval then
v_sum_of_bins := g_nof_data_per_sync + g_nof_data_per_sync_diff;
end if;
- assert sum_of_bins = v_sum_of_bins report "Sum of bins not equal to g_nof_data_per_sync (expected " & integer'image(v_sum_of_bins) & ", actual " & integer'image(sum_of_bins) & ")" severity ERROR;
+ assert sum_of_bins = v_sum_of_bins
+ report "Sum of bins not equal to g_nof_data_per_sync (expected " & integer'image(v_sum_of_bins) & ", actual " & integer'image(sum_of_bins) & ")"
+ severity ERROR;
end if;
ver_long_sync_interval <= not ver_long_sync_interval;
end loop;
@@ -275,7 +281,9 @@ begin
begin
proc_common_wait_until_high(dp_clk, stimuli_done);
proc_common_wait_some_cycles(dp_clk, 50);
- assert verification_done = '1' report "Verification failed" severity ERROR;
+ assert verification_done = '1'
+ report "Verification failed"
+ severity ERROR;
wait;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd b/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
index 738ce81a41..d6947cfd59 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
@@ -159,7 +159,9 @@ begin
begin
if rising_edge(clk) then
if out_val = '1' then
- assert out_acc = expected_acc_p report "Error: wrong result" severity ERROR;
+ assert out_acc = expected_acc_p
+ report "Error: wrong result"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index 85a515726d..df823cd06f 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -310,19 +310,27 @@ begin
for j in 0 to g_nof_bins - 1 loop
proc_common_wait_until_high(dp_clk, histogram_valid);
if i = 0 then -- Sync period 0: we expect RAM to contain zeros
- assert histogram_data = 0 report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")" severity ERROR;
+ assert histogram_data = 0
+ report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")"
+ severity ERROR;
else -- Sync period 1 onwards
if g_stimuli_mode = "counter" then
-- Counter data: bin values remain the same every sync
- assert histogram_data = c_expected_ram_content_counter report "RAM contains wrong bin count (expected " & integer'image(c_expected_ram_content_counter) & ", actual " & integer'image(histogram_data) & ")" severity ERROR;
+ assert histogram_data = c_expected_ram_content_counter
+ report "RAM contains wrong bin count (expected " & integer'image(c_expected_ram_content_counter) & ", actual " & integer'image(histogram_data) & ")"
+ severity ERROR;
elsif g_stimuli_mode = "dc" then
-- DC data: DC level increments every sync
if j = (i / c_nof_levels_per_bin) then -- Check bin address and account for multiple levels per bin
-- this address (j) should contain the DC level total count of this sync period (i)
- assert histogram_data = g_nof_data_per_sync report "RAM contains wrong bin count (expected " & integer'image(g_nof_data_per_sync) & ", actual " & integer'image(histogram_data) & ")" severity ERROR;
+ assert histogram_data = g_nof_data_per_sync
+ report "RAM contains wrong bin count (expected " & integer'image(g_nof_data_per_sync) & ", actual " & integer'image(histogram_data) & ")"
+ severity ERROR;
else
-- this address should contain zero
- assert histogram_data = 0 report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")" severity ERROR;
+ assert histogram_data = 0
+ report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")"
+ severity ERROR;
end if;
end if;
end if;
@@ -332,7 +340,9 @@ begin
-- Check the sum of all bins
if i > 0 then -- Skip sync 0 (histogram still all zeros)
- assert sum_of_bins = g_nof_data_per_sync report "Sum of bins not equal to g_nof_data_per_sync (expected " & integer'image(g_nof_data_per_sync) & ", actual " & integer'image(sum_of_bins) & ")" severity ERROR;
+ assert sum_of_bins = g_nof_data_per_sync
+ report "Sum of bins not equal to g_nof_data_per_sync (expected " & integer'image(g_nof_data_per_sync) & ", actual " & integer'image(sum_of_bins) & ")"
+ severity ERROR;
end if;
end loop;
verification_done <= '1'; -- We have blocking proc_common_wait_until_high procedures above so we need to know if we make it here.
@@ -344,7 +354,9 @@ begin
begin
proc_common_wait_until_high(dp_clk, stimuli_done);
proc_common_wait_some_cycles(dp_clk, 50);
- assert verification_done = '1' report "Verification failed" severity ERROR;
+ assert verification_done = '1'
+ report "Verification failed"
+ severity ERROR;
wait;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
index d3217150a2..f6c938c023 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
@@ -196,7 +196,9 @@ begin
proc_common_wait_until_high(mm_clk, ram_st_xsq_miso.rdval);
proc_common_wait_some_cycles(mm_clk, 2 * c_nof_statistics * c_nof_complex * g_stat_data_sz + 10);
for I in 0 to c_nof_statistics * c_nof_complex - 1 loop
- assert TO_SINT(st_xsq_out_arr(I * 2)) = c_expected_xsq(I) report "WRONG XSQ DATA" severity ERROR; -- Only read low part of statistic
+ assert TO_SINT(st_xsq_out_arr(I * 2)) = c_expected_xsq(I)
+ report "WRONG XSQ DATA"
+ severity ERROR; -- Only read low part of statistic
end loop;
wait;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
index 51fd62c3f9..f9359ae87d 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
@@ -214,7 +214,9 @@ begin
proc_common_wait_some_cycles(mm_clk, 2 * c_total_mem_size + 10);
for M in 0 to g_nof_streams - 1 loop
for I in 0 to c_nof_statistics * c_nof_complex - 1 loop
- assert TO_SINT(st_xsq_out_2arr(M)(g_stat_data_sz * I)) = expected_xsq_2arr(M)(I) report "WRONG XSQ DATA" severity ERROR; -- Only read low part of statistic
+ assert TO_SINT(st_xsq_out_2arr(M)(g_stat_data_sz * I)) = expected_xsq_2arr(M)(I)
+ report "WRONG XSQ DATA"
+ severity ERROR; -- Only read low part of statistic
end loop;
end loop;
wait;
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
index 6cf6177c66..d60e44233b 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
@@ -343,7 +343,9 @@ begin
end loop;
end loop;
proc_common_wait_some_cycles(mm_clk, 1);
- assert read_coefs_arr = flip_coefs_arr report "Coefs file does not match coefs read via MM" severity error;
+ assert read_coefs_arr = flip_coefs_arr
+ report "Coefs file does not match coefs read via MM"
+ severity error;
wait;
end process;
end generate;
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
index ee4a173a4a..541dd5e095 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
@@ -1094,16 +1094,28 @@ begin
---------------------------------------------------------------------------
-- Verify
---------------------------------------------------------------------------
- assert almost_equal(input_ampl_a, c_wg_ampl_a, 1.0) report "Wrong amplitude for WG input a, " & real_to_str(input_ampl_a, 7, 0) & " /~= " & real_to_str(c_wg_ampl_a, 7, 0) severity ERROR;
- assert almost_equal(input_ampl_a, cw_ampl_a, 0.02) report "Wrong estimated amplitude for WG input a, " & real_to_str(input_ampl_a, 7, 0) & " /~= " & real_to_str(cw_ampl_a, 7, 0) severity ERROR;
- assert almost_zero(input_mean_a, 0.01) report "Wrong estimated DC mean for WG input a, " & real_to_str(input_mean_a, 7, 0) & " /~= 0.0" severity ERROR;
- assert almost_zero(fir_mean_a, 0.01) report "Wrong estimated DC mean for FIR filter output a, " & real_to_str(fir_mean_a, 7, 0) & " /~= 0.0" severity ERROR;
+ assert almost_equal(input_ampl_a, c_wg_ampl_a, 1.0)
+ report "Wrong amplitude for WG input a, " & real_to_str(input_ampl_a, 7, 0) & " /~= " & real_to_str(c_wg_ampl_a, 7, 0)
+ severity ERROR;
+ assert almost_equal(input_ampl_a, cw_ampl_a, 0.02)
+ report "Wrong estimated amplitude for WG input a, " & real_to_str(input_ampl_a, 7, 0) & " /~= " & real_to_str(cw_ampl_a, 7, 0)
+ severity ERROR;
+ assert almost_zero(input_mean_a, 0.01)
+ report "Wrong estimated DC mean for WG input a, " & real_to_str(input_mean_a, 7, 0) & " /~= 0.0"
+ severity ERROR;
+ assert almost_zero(fir_mean_a, 0.01)
+ report "Wrong estimated DC mean for FIR filter output a, " & real_to_str(fir_mean_a, 7, 0) & " /~= 0.0"
+ severity ERROR;
if not c_bin_a_frac_en then
- assert almost_equal(fir_ampl_a, fil_ampl_a, 10.0) report "Wrong estimated amplitude for FIR filter output a, " & real_to_str(fir_ampl_a, 7, 0) & " /~= " & real_to_str(fil_ampl_a, 7, 0) severity ERROR;
+ assert almost_equal(fir_ampl_a, fil_ampl_a, 10.0)
+ report "Wrong estimated amplitude for FIR filter output a, " & real_to_str(fir_ampl_a, 7, 0) & " /~= " & real_to_str(fil_ampl_a, 7, 0)
+ severity ERROR;
assert almost_equal(sub_a_ampl / cw_ampl_a / c_pfb_sub_scaling, 1.0, 0.01)
- report "Wrong measured scaling for PFB subband output a, " & real_to_str(sub_a_ampl / cw_ampl_a, 7, 0) & " /~= " & real_to_str(c_pfb_sub_scaling, 7, 0) severity ERROR;
+ report "Wrong measured scaling for PFB subband output a, " & real_to_str(sub_a_ampl / cw_ampl_a, 7, 0) & " /~= " & real_to_str(c_pfb_sub_scaling, 7, 0)
+ severity ERROR;
assert almost_equal(sst_wg_power_a / c_exp_sst_a, 1.0, 0.01)
- report "Wrong measured scaling for PFB SST output a, " & real_to_str(sst_wg_power_a / c_exp_sst_a, 7, 0) & " /~= 1.0" severity ERROR;
+ report "Wrong measured scaling for PFB SST output a, " & real_to_str(sst_wg_power_a / c_exp_sst_a, 7, 0) & " /~= 1.0"
+ severity ERROR;
end if;
tb_end <= '1';
wait;
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
index c75f7f8c99..011a04bce7 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
@@ -125,7 +125,9 @@ begin
---------------------------------------------------------------
-- CHECK IF PROVIDED GENERICS ARE ALLOWED.
---------------------------------------------------------------
- assert not(g_wpfb.nof_chan /= 0 and g_wpfb.wb_factor /= 1 and rising_edge(dp_clk)) report "nof_chan must be 0 when wb_factor > 1" severity FAILURE;
+ assert not(g_wpfb.nof_chan /= 0 and g_wpfb.wb_factor /= 1 and rising_edge(dp_clk))
+ report "nof_chan must be 0 when wb_factor > 1"
+ severity FAILURE;
---------------------------------------------------------------
-- INPUT REGISTER FOR THE SOSI ARRAY
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
index 654192f40f..bd2307d3ce 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
@@ -264,7 +264,9 @@ begin
proc_mem_mm_bus_rd(L * g_wpfb.nof_points * g_wpfb.nof_taps + K * c_nof_bands_per_chn * g_wpfb.nof_taps + J * c_nof_bands_per_chn + I, clk, ram_coefs_miso, ram_coefs_mosi); -- Read the coefficient from the memory
temp_reg <= coefs_arr(I);
if(ram_coefs_miso.rdval = '1') then
- assert temp_reg = TO_UINT(ram_coefs_miso.rddata(g_wpfb.coef_dat_w - 1 downto 0)) report "Read data from memory error" severity error;
+ assert temp_reg = TO_UINT(ram_coefs_miso.rddata(g_wpfb.coef_dat_w - 1 downto 0))
+ report "Read data from memory error"
+ severity error;
end if;
end loop;
proc_common_wait_some_cycles(clk, 1);
@@ -399,8 +401,12 @@ begin
proc_common_wait_some_cycles(clk, 10);
- assert expected_sst_arr = result_sst_arr report "Output statistics error" severity error;
- assert expected_sst_arr /= result_sst_arr report "Output statistics OK!!!!" severity note;
+ assert expected_sst_arr = result_sst_arr
+ report "Output statistics error"
+ severity error;
+ assert expected_sst_arr /= result_sst_arr
+ report "Output statistics OK!!!!"
+ severity note;
end loop;
end process;
@@ -536,10 +542,16 @@ begin
if (out_val = '1' and v_output_cnt < (c_nof_spectra_in_file * g_wpfb.nof_points / g_wpfb.wb_factor)) then
-- only write when out_val='1', because then the file is independent of cycles with invalid out_dat
-- only check the first c_nof_spectra_in_file spectrums.
- assert out_sync = gold_sync report "Output sync error" severity error;
+ assert out_sync = gold_sync
+ report "Output sync error"
+ severity error;
for I in 0 to g_wpfb.wb_factor - 1 loop
- assert TO_SINT(out_re_arr(I)) = gold_re_arr(I) report "Output real data error" severity error;
- assert TO_SINT(out_im_arr(I)) = gold_im_arr(I) report "Output imag data error" severity error;
+ assert TO_SINT(out_re_arr(I)) = gold_re_arr(I)
+ report "Output real data error"
+ severity error;
+ assert TO_SINT(out_im_arr(I)) = gold_im_arr(I)
+ report "Output imag data error"
+ severity error;
end loop;
v_output_cnt := v_output_cnt + 1;
end if;
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index bcccc8f0fa..3624614409 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -521,14 +521,20 @@ begin
begin
-- Wait until tb_end_almost
proc_common_wait_until_high(clk, tb_end_almost);
- assert in_val_cnt > 0 report "Test did not run, no valid input data" severity error;
+ assert in_val_cnt > 0
+ report "Test did not run, no valid input data"
+ severity error;
-- The WPFB has a memory of 2 block, independent of use_reorder and use_separate, but without the
-- reorder buffer it outputs 1 sample more, because that is immediately available in a new block.
-- Ensure g_data_file_nof_lines is multiple of g_wpfb.nof_points.
if g_wpfb.use_reorder = true then
- assert out_val_cnt = in_val_cnt - 2 * c_nof_valid_per_block report "Unexpected number of valid output data" severity error;
+ assert out_val_cnt = in_val_cnt - 2 * c_nof_valid_per_block
+ report "Unexpected number of valid output data"
+ severity error;
else
- assert out_val_cnt = in_val_cnt - 2 * c_nof_valid_per_block + c_nof_channels report "Unexpected number of valid output data" severity error;
+ assert out_val_cnt = in_val_cnt - 2 * c_nof_valid_per_block + c_nof_channels
+ report "Unexpected number of valid output data"
+ severity error;
end if;
wait;
end process;
@@ -584,31 +590,55 @@ begin
if not c_in_complex then
if reg_out_channel = 1 then
--if reg_out_val_a='1' then
- assert out_re_a_scope = 0 report "Output data A real error in channel" severity error;
- assert out_im_a_scope = 0 report "Output data A imag error in channel" severity error;
+ assert out_re_a_scope = 0
+ report "Output data A real error in channel"
+ severity error;
+ assert out_im_a_scope = 0
+ report "Output data A imag error in channel"
+ severity error;
--end if;
if reg_out_val_b = '1' then
- assert out_re_b_scope = 0 report "Output data B real error in channel" severity error;
- assert out_im_b_scope = 0 report "Output data B imag error in channel" severity error;
+ assert out_re_b_scope = 0
+ report "Output data B real error in channel"
+ severity error;
+ assert out_im_b_scope = 0
+ report "Output data B imag error in channel"
+ severity error;
end if;
else
--if reg_out_val_a='1' then
- assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin report "Output data A real error" severity error;
- assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin report "Output data A imag error" severity error;
+ assert diff_re_a_scope >= -g_diff_margin and diff_re_a_scope <= g_diff_margin
+ report "Output data A real error"
+ severity error;
+ assert diff_im_a_scope >= -g_diff_margin and diff_im_a_scope <= g_diff_margin
+ report "Output data A imag error"
+ severity error;
--end if;
if reg_out_val_b = '1' then
- assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin report "Output data B real error" severity error;
- assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin report "Output data B imag error" severity error;
+ assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin
+ report "Output data B real error"
+ severity error;
+ assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin
+ report "Output data B imag error"
+ severity error;
end if;
end if;
else
if reg_out_val_c = '1' then
if reg_out_channel = 1 then
- assert out_re_c_scope = 0 report "Output data C real error in channel" severity error;
- assert out_im_c_scope = 0 report "Output data C imag error in channel" severity error;
+ assert out_re_c_scope = 0
+ report "Output data C real error in channel"
+ severity error;
+ assert out_im_c_scope = 0
+ report "Output data C imag error in channel"
+ severity error;
else
- assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin report "Output data C real error" severity error;
- assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin report "Output data C imag error" severity error;
+ assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin
+ report "Output data C real error"
+ severity error;
+ assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin
+ report "Output data C imag error"
+ severity error;
end if;
end if;
end if;
diff --git a/libraries/io/aduh/src/vhdl/aduh_pll.vhd b/libraries/io/aduh/src/vhdl/aduh_pll.vhd
index 36ef83efb9..5d8aefc640 100644
--- a/libraries/io/aduh/src/vhdl/aduh_pll.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_pll.vhd
@@ -160,7 +160,8 @@ begin
-- 2 TRUE YES
-- 2 FALSE NO
assert not(g_ai.use_lvds_clk = false and g_ai.nof_clocks > 1)
- report "aduh_pll.vhd: when the dp_clk is used to capture the LVDS data, then nof_clocks must be 1" severity FAILURE;
+ report "aduh_pll.vhd: when the dp_clk is used to capture the LVDS data, then nof_clocks must be 1"
+ severity FAILURE;
-- nof_clocks nof_adu Supported
-- 1 1 YES
@@ -168,7 +169,8 @@ begin
-- 2 1 NO
-- 2 2 YES
assert not(g_ai.nof_clocks > g_ai.nof_adu)
- report "aduh_pll.vhd: when only one ADU is used then the nof clocks must be 1" severity FAILURE;
+ report "aduh_pll.vhd: when only one ADU is used then the nof clocks must be 1"
+ severity FAILURE;
-----------------------------------------------------------------------------
-- Prepare lvdsh_pll input
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd b/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
index c4d13dbe00..233da434b6 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
@@ -155,7 +155,8 @@ architecture rtl of lvdsh_pll is
signal nxt_rx_val : std_logic;
begin
assert g_use_ddio = false
- report "lvdsh_pll.vhd: LVDS Rx using DDIO without PLL is not supported yet" severity FAILURE;
+ report "lvdsh_pll.vhd: LVDS Rx using DDIO without PLL is not supported yet"
+ severity FAILURE;
no_lvds_clk_rst : if g_use_lvds_clk_rst = false generate
lvds_clk_rst <= '0';
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
index 8240c5af17..45b965d43e 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
@@ -270,7 +270,8 @@ begin
-- Wait some time
wait for c_verify_period;
if verify_en_all /= '1' then
- report "ADUH using DD: No valid data, test may not be running." severity ERROR;
+ report "ADUH using DD: No valid data, test may not be running."
+ severity ERROR;
end if;
wait;
end process;
@@ -296,7 +297,8 @@ begin
if verify_en_all = '1' then
for J in 0 to c_dp_factor - 1 loop
if verify_data(I)((J + 1) * c_adc_w - 1 downto J * c_adc_w) /= INCR_UVEC(verify_data(I - 1)((J + 1) * c_adc_w - 1 downto J * c_adc_w), c_ana_diff) then
- report "ADUH using DD: Wrong alignment between ADCs." severity ERROR;
+ report "ADUH using DD: Wrong alignment between ADCs."
+ severity ERROR;
end if;
end loop;
end if;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
index b2f46d0e35..4b14d9a6cf 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
@@ -160,7 +160,9 @@ begin
while vI < c_exp_sum_arr'length loop
wait until rising_edge(clk);
if sum_sync = '1' then
- assert sum = TO_SVEC(c_exp_sum_arr(vI), c_sum_w) report "Unexpected voltage sum." severity ERROR;
+ assert sum = TO_SVEC(c_exp_sum_arr(vI), c_sum_w)
+ report "Unexpected voltage sum."
+ severity ERROR;
vI := vI + 1;
end if;
end loop;
@@ -172,7 +174,9 @@ begin
p_verify_done : process
begin
proc_common_wait_until_high(clk, verify_done);
- assert verify_done = '1' report "No sum output" severity ERROR;
+ assert verify_done = '1'
+ report "No sum output"
+ severity ERROR;
wait;
end process;
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
index ca47377b5d..d91f6ac4a1 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
@@ -368,7 +368,8 @@ begin
wait until falling_edge(restart_any);
wait for c_measurement_period;
if verify_en_all = '0' then
- report "ADUH with PLL: No valid data, test may not be running." severity ERROR;
+ report "ADUH with PLL: No valid data, test may not be running."
+ severity ERROR;
end if;
end loop;
end process;
@@ -393,7 +394,8 @@ begin
if verify_en_all = '1' then
for J in 0 to c_ai.dp_deser_factor - 1 loop
if verify_data(I)((J + 1) * c_adc_w - 1 downto J * c_adc_w) /= INCR_UVEC(verify_data(I - 1)((J + 1) * c_adc_w - 1 downto J * c_adc_w), c_ana_diff) then
- report "ADUH with PLL: Wrong alignment between ADCs." severity ERROR;
+ report "ADUH with PLL: Wrong alignment between ADCs."
+ severity ERROR;
end if;
end loop;
end if;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
index 05a46a4529..1e6fbdce6b 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
@@ -159,7 +159,9 @@ begin
while vI < c_exp_sum_arr'length loop
wait until rising_edge(clk);
if pwr_sum_sync = '1' then
- assert pwr_sum = TO_SVEC(c_exp_sum_arr(vI), c_pwr_sum_w) report "Unexpected power sum." severity ERROR;
+ assert pwr_sum = TO_SVEC(c_exp_sum_arr(vI), c_pwr_sum_w)
+ report "Unexpected power sum."
+ severity ERROR;
vI := vI + 1;
end if;
end loop;
@@ -171,7 +173,9 @@ begin
p_verify_done : process
begin
proc_common_wait_until_high(clk, verify_done);
- assert verify_done = '1' report "No power sum output" severity ERROR;
+ assert verify_done = '1'
+ report "No power sum output"
+ severity ERROR;
wait;
end process;
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
index 33684e3688..56e71661f2 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
@@ -156,10 +156,12 @@ begin
if rising_edge(dp_clk) then
if verify_ok = '1' then
if a_verify_res_val = '0' or unsigned(a_verify_res) /= 0 then
- report "ADUH A: test pattern I error." severity ERROR;
+ report "ADUH A: test pattern I error."
+ severity ERROR;
end if;
if b_verify_res_val = '0' or unsigned(b_verify_res) /= 0 then
- report "ADUH B: test pattern Q error." severity ERROR;
+ report "ADUH B: test pattern Q error."
+ severity ERROR;
end if;
end if;
end if;
@@ -171,10 +173,12 @@ begin
if rising_edge(dp_clk) then
if verify_wrong = '1' then
if a_verify_res_val = '0' or unsigned(a_verify_res) = 0 then
- report "ADUH A: test pattern I undetected error." severity ERROR;
+ report "ADUH A: test pattern I undetected error."
+ severity ERROR;
end if;
if b_verify_res_val = '0' or unsigned(b_verify_res) = 0 then
- report "ADUH B: test pattern Q undetected error." severity ERROR;
+ report "ADUH B: test pattern Q undetected error."
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
index c40e2ec4f3..521771b61f 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
@@ -238,10 +238,14 @@ begin
begin
if rising_edge(dp_clk) then
if verify_phase_en = '1' then
- assert dp_phs_locked = '1' report "Unexpected dp phase detected" severity ERROR;
+ assert dp_phs_locked = '1'
+ report "Unexpected dp phase detected"
+ severity ERROR;
end if;
if verify_sample_phase_en = '1' then
- assert dp_sample_phase = in_sample_phase report "Unexpected dp_sample_phase" severity ERROR;
+ assert dp_sample_phase = in_sample_phase
+ report "Unexpected dp_sample_phase"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
index 83c07b0cab..4b486c7860 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
@@ -167,7 +167,9 @@ begin
begin
if rising_edge(dp_clk) then
if verify_phase_en = '1' then
- assert dp_sync_phase = g_in_phase or dp_sync_phase = 4 + g_in_phase report "Unexpected dp_sync_phase" severity ERROR;
+ assert dp_sync_phase = g_in_phase or dp_sync_phase = 4 + g_in_phase
+ report "Unexpected dp_sync_phase"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
index e3afe02e4d..7bebc062b5 100644
--- a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
@@ -65,26 +65,58 @@ architecture tb of tb_mms_aduh_quad is
procedure proc_verify_bist_expect_ok(aduh_a_verify, aduh_b_verify, aduh_c_verify, aduh_d_verify : std_logic_vector) is
begin
- assert aduh_a_verify(c_aduh_verify_val_bi) = '1' report "ADU-A bist did not run" severity ERROR;
- assert aduh_b_verify(c_aduh_verify_val_bi) = '1' report "ADU-B bist did not run" severity ERROR;
- assert aduh_c_verify(c_aduh_verify_val_bi) = '1' report "ADU-C bist did not run" severity ERROR;
- assert aduh_d_verify(c_aduh_verify_val_bi) = '1' report "ADU-D bist did not run" severity ERROR;
- assert TO_UINT(aduh_a_verify(c_aduh_verify_res_hi downto 0)) = 0 report "ADU-A bist went wrong" severity ERROR;
- assert TO_UINT(aduh_b_verify(c_aduh_verify_res_hi downto 0)) = 0 report "ADU-B bist went wrong" severity ERROR;
- assert TO_UINT(aduh_c_verify(c_aduh_verify_res_hi downto 0)) = 0 report "ADU-C bist went wrong" severity ERROR;
- assert TO_UINT(aduh_d_verify(c_aduh_verify_res_hi downto 0)) = 0 report "ADU-D bist went wrong" severity ERROR;
+ assert aduh_a_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-A bist did not run"
+ severity ERROR;
+ assert aduh_b_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-B bist did not run"
+ severity ERROR;
+ assert aduh_c_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-C bist did not run"
+ severity ERROR;
+ assert aduh_d_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-D bist did not run"
+ severity ERROR;
+ assert TO_UINT(aduh_a_verify(c_aduh_verify_res_hi downto 0)) = 0
+ report "ADU-A bist went wrong"
+ severity ERROR;
+ assert TO_UINT(aduh_b_verify(c_aduh_verify_res_hi downto 0)) = 0
+ report "ADU-B bist went wrong"
+ severity ERROR;
+ assert TO_UINT(aduh_c_verify(c_aduh_verify_res_hi downto 0)) = 0
+ report "ADU-C bist went wrong"
+ severity ERROR;
+ assert TO_UINT(aduh_d_verify(c_aduh_verify_res_hi downto 0)) = 0
+ report "ADU-D bist went wrong"
+ severity ERROR;
end;
procedure proc_verify_bist_expect_errors(aduh_a_verify, aduh_b_verify, aduh_c_verify, aduh_d_verify : std_logic_vector) is
begin
- assert aduh_a_verify(c_aduh_verify_val_bi) = '1' report "ADU-A bist did not run" severity ERROR;
- assert aduh_b_verify(c_aduh_verify_val_bi) = '1' report "ADU-B bist did not run" severity ERROR;
- assert aduh_c_verify(c_aduh_verify_val_bi) = '1' report "ADU-C bist did not run" severity ERROR;
- assert aduh_d_verify(c_aduh_verify_val_bi) = '1' report "ADU-D bist did not run" severity ERROR;
- assert TO_UINT(aduh_a_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask report "ADU-A bist error detection went wrong" severity ERROR;
- assert TO_UINT(aduh_b_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask report "ADU-B bist error detection went wrong" severity ERROR;
- assert TO_UINT(aduh_c_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask report "ADU-C bist error detection went wrong" severity ERROR;
- assert TO_UINT(aduh_d_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask report "ADU-D bist error detection went wrong" severity ERROR;
+ assert aduh_a_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-A bist did not run"
+ severity ERROR;
+ assert aduh_b_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-B bist did not run"
+ severity ERROR;
+ assert aduh_c_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-C bist did not run"
+ severity ERROR;
+ assert aduh_d_verify(c_aduh_verify_val_bi) = '1'
+ report "ADU-D bist did not run"
+ severity ERROR;
+ assert TO_UINT(aduh_a_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask
+ report "ADU-A bist error detection went wrong"
+ severity ERROR;
+ assert TO_UINT(aduh_b_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask
+ report "ADU-B bist error detection went wrong"
+ severity ERROR;
+ assert TO_UINT(aduh_c_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask
+ report "ADU-C bist error detection went wrong"
+ severity ERROR;
+ assert TO_UINT(aduh_d_verify(c_aduh_verify_res_hi downto 0)) = c_aduh_verify_res_mask
+ report "ADU-D bist error detection went wrong"
+ severity ERROR;
end;
signal tb_end : std_logic := '0';
@@ -174,8 +206,12 @@ begin
proc_mem_mm_bus_rd(0, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); aduh_ab_locked <= reg_miso.rddata(31 downto 0);
proc_mem_mm_bus_rd(1, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); aduh_cd_locked <= reg_miso.rddata(31 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
- assert TO_UINT(aduh_ab_locked) = 1 report "ADU-AB in not locked" severity ERROR;
- assert TO_UINT(aduh_cd_locked) = 1 report "ADU-CD in not locked" severity ERROR;
+ assert TO_UINT(aduh_ab_locked) = 1
+ report "ADU-AB in not locked"
+ severity ERROR;
+ assert TO_UINT(aduh_cd_locked) = 1
+ report "ADU-CD in not locked"
+ severity ERROR;
----------------------------------------------------------------------------
-- Expect aduh BIST OK for A, B, C, D
@@ -195,8 +231,12 @@ begin
proc_mem_mm_bus_rd(0, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); aduh_ab_locked <= reg_miso.rddata(31 downto 0);
proc_mem_mm_bus_rd(1, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); aduh_cd_locked <= reg_miso.rddata(31 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
- assert TO_UINT(aduh_ab_locked) = 3 report "ADU-AB in not locked stable" severity ERROR;
- assert TO_UINT(aduh_cd_locked) = 3 report "ADU-CD in not locked stable" severity ERROR;
+ assert TO_UINT(aduh_ab_locked) = 3
+ report "ADU-AB in not locked stable"
+ severity ERROR;
+ assert TO_UINT(aduh_cd_locked) = 3
+ report "ADU-CD in not locked stable"
+ severity ERROR;
----------------------------------------------------------------------------
-- Expect aduh BIST errors for A, B, C, D
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 1e1bb093fd..34004c890e 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -409,7 +409,9 @@ begin
state_vec => state_vec
);
- assert g_rd_fifo_depth > c_rd_fifo_af_margin report "io_ddr: rd FIFO depth must be > almost full margin." severity FAILURE;
+ assert g_rd_fifo_depth > c_rd_fifo_af_margin
+ report "io_ddr: rd FIFO depth must be > almost full margin."
+ severity FAILURE;
u_rd_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
generic map (
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 814d64c3fb..683d62a69e 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -277,11 +277,15 @@ begin
-- . verify ddr_gigabytes
ddr_gigabytes <= TO_SINT(reg_io_ddr_miso.rddata(23 downto 16));
proc_common_wait_some_cycles(mm_clk, 1);
- assert ddr_gigabytes = c_exp_gigabytes report "Wrong read ddr_gigabytes" severity ERROR;
+ assert ddr_gigabytes = c_exp_gigabytes
+ report "Wrong read ddr_gigabytes"
+ severity ERROR;
-- . verify ctlr_nof_bytes_per_word
ctlr_nof_bytes_per_word <= TO_UINT(reg_io_ddr_miso.rddata(15 downto 8));
proc_common_wait_some_cycles(mm_clk, 1);
- assert ctlr_nof_bytes_per_word = c_exp_nof_bytes_per_word report "Wrong read ctlr_nof_bytes_per_word" severity ERROR;
+ assert ctlr_nof_bytes_per_word = c_exp_nof_bytes_per_word
+ report "Wrong read ctlr_nof_bytes_per_word"
+ severity ERROR;
-- Start diagnostics source for write and sink for verify read
proc_common_wait_some_cycles(dp_clk, 1);
@@ -326,13 +330,21 @@ begin
proc_common_wait_some_cycles(ctlr_clk, largest(TO_UINT(wr_fifo_usedw) / g_dp_factor, TO_UINT(rd_fifo_usedw)));
proc_common_wait_some_cycles(ctlr_clk, 10); -- some extra margin
- assert unsigned(wr_fifo_usedw) < g_dp_factor report "[ERROR] Write FIFO is flushed but not empty!" severity FAILURE;
- assert unsigned(rd_fifo_usedw) = 0 report "[ERROR] Read FIFO is not empty!" severity FAILURE;
- assert unsigned(snk_val_cnt) = expected_cnt report "[ERROR] Unexpected number of read data!" severity FAILURE;
+ assert unsigned(wr_fifo_usedw) < g_dp_factor
+ report "[ERROR] Write FIFO is flushed but not empty!"
+ severity FAILURE;
+ assert unsigned(rd_fifo_usedw) = 0
+ report "[ERROR] Read FIFO is not empty!"
+ severity FAILURE;
+ assert unsigned(snk_val_cnt) = expected_cnt
+ report "[ERROR] Unexpected number of read data!"
+ severity FAILURE;
-- Check diagnostics sink after the rd fifo has been read empty
proc_common_wait_some_cycles(dp_clk, 1);
- assert snk_diag_res_val = '1' report "[ERROR] DIAG_RES INVALID!" severity FAILURE;
+ assert snk_diag_res_val = '1'
+ report "[ERROR] DIAG_RES INVALID!"
+ severity FAILURE;
--ASSERT snk_diag_res = '0' REPORT "[ERROR] WRONG DIAG_RES!" SEVERITY FAILURE;
--FIXME: Add 4GB DDR4 IO driver IP for unb2c and then uncomment ASSERT snk_diag_res and delete this IF-THEN-ELSE.
if c_tech_ddr.name = "DDR4" and g_technology = c_tech_arria10_e2sg then
@@ -340,10 +352,14 @@ begin
-- unb2c), because we have 8GB DDR4 IO Driver and 4GB DDR4 memory. In
-- simulation these can connect, but appear to yield dbg_rd_data = 0
-- causing wrong snk_diag_res.
- report "Did not check snk_diag_res." severity NOTE;
+ report "Did not check snk_diag_res."
+ severity NOTE;
else
- assert snk_diag_res = '0' report "[ERROR] WRONG DIAG_RES!" severity FAILURE;
- report "Checked snk_diag_res." severity NOTE;
+ assert snk_diag_res = '0'
+ report "[ERROR] WRONG DIAG_RES!"
+ severity FAILURE;
+ report "Checked snk_diag_res."
+ severity NOTE;
end if;
-- Stop diagnostics sink
@@ -356,7 +372,8 @@ begin
end loop;
-- If the test failed then it would have stopped already (due to SEVERITY FAILURE), so if it gets here then the test has passed
- report "[OK] Test passed." severity NOTE;
+ report "[OK] Test passed."
+ severity NOTE;
-- Stop the simulation
-- . Stopping the clocks via tb_end does end the tb for the DDR3 IP, but is not sufficient to stop the tb for the DDR4 IP.
@@ -365,9 +382,11 @@ begin
ctlr_ref_rst <= '1';
if g_tb_end = false then
- report "Tb Simulation finished." severity NOTE;
+ report "Tb Simulation finished."
+ severity NOTE;
else
- report "Tb Simulation finished." severity FAILURE;
+ report "Tb Simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index 19797cbbf6..496fc4c014 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -98,7 +98,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
index f73e223e0a..665281d1bb 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
@@ -85,7 +85,9 @@ begin
---------------------------------------------------------------
-- CHECK IF PROVIDED GENERICS ARE ALLOWED.
---------------------------------------------------------------
- assert not((g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize) /= (g_ddr3_seq.rd_nof_chunks * g_ddr3_seq.rd_chunksize) and rising_edge(dp_clk)) report "Total write configuration is different from total read configuration!!!" severity FAILURE;
+ assert not((g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize) /= (g_ddr3_seq.rd_nof_chunks * g_ddr3_seq.rd_chunksize) and rising_edge(dp_clk))
+ report "Total write configuration is different from total read configuration!!!"
+ severity FAILURE;
p_comb : process(r, dp_rst, init_done, done, ctlr_rdy, sync_ok_in)
variable v : reg_type;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
index e86d259cb1..be8fb6e031 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
@@ -153,9 +153,15 @@ begin
wait for 2 us; -- 'Done' means all requests are posted. Wait for the last read data to arrive.
- assert snk_diag_res_val = '1' report "[ERROR] DIAG_RES INVALID!" severity FAILURE;
- assert snk_diag_res = '0' report "[ERROR] NON-ZERO DIAG_RES!" severity FAILURE;
- assert false report "[OK] Test passed." severity NOTE;
+ assert snk_diag_res_val = '1'
+ report "[ERROR] DIAG_RES INVALID!"
+ severity FAILURE;
+ assert snk_diag_res = '0'
+ report "[ERROR] NON-ZERO DIAG_RES!"
+ severity FAILURE;
+ assert false
+ report "[OK] Test passed."
+ severity NOTE;
tb_end <= '1';
wait;
diff --git a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
index 0fe6818b45..c2a5fda906 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
@@ -162,7 +162,9 @@ begin
begin
if rising_edge(st_clk) then
if g_use_dp_header and decoded_sosi.sop = '1' then
- assert decoded_length = exp_length report "Unexpected Rx length" & natural'image(decoded_length) & " /= " & natural'image(exp_length) & " expected length from Tx" severity ERROR;
+ assert decoded_length = exp_length
+ report "Unexpected Rx length" & natural'image(decoded_length) & " /= " & natural'image(exp_length) & " expected length from Tx"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_eth.vhd
index 9a880edc09..246a81a62d 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth.vhd
@@ -653,19 +653,24 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt + rx_pkt_discarded_cnt + TO_UINT(rx_pkt_flushed_cnt) then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
wait for 1 us;
tb_end <= '1';
if g_tb_end = false then
- report "Tb simulation finished." severity NOTE;
+ report "Tb simulation finished."
+ severity NOTE;
else
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
index 60e4727e69..4c44542bc6 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
@@ -186,7 +186,9 @@ begin
for I in 0 to c_wait_eop_sop - 1 loop wait until rising_edge(clk); end loop;
tb_end <= '1';
- assert false report "Simulation tb_eth_checksum finished." severity NOTE;
+ assert false
+ report "Simulation tb_eth_checksum finished."
+ severity NOTE;
wait;
end process;
@@ -194,10 +196,14 @@ begin
begin
wait until rising_edge(clk);
if checksum_val = '1' then
- assert unsigned(checksum) = c_exp_checksum report "Wrong checksum" severity ERROR;
+ assert unsigned(checksum) = c_exp_checksum
+ report "Wrong checksum"
+ severity ERROR;
end if;
if tb_end = '1' then
- assert checksum_val = '1' report "Checksum is not valid at tb_end" severity ERROR;
+ assert checksum_val = '1'
+ report "Checksum is not valid at tb_end"
+ severity ERROR;
end if;
end process;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
index e241e09243..9bbed1aa3c 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
@@ -116,49 +116,73 @@ architecture tb of tb_eth_IHL_to_20 is
begin
-- Eth header
wait until falling_edge(clk) and src_out.valid = '1' and src_out.sop = '1';
- assert src_out.data(31 downto 0) = X"0000FFFF" report "Wrong word align and Destination MAC" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"0000FFFF"
+ report "Wrong word align and Destination MAC"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"FFFFFFFF" report "Wrong Destination MAC" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"FFFFFFFF"
+ report "Wrong Destination MAC"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"10FA0004" report "Wrong Source MAC" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"10FA0004"
+ report "Wrong Source MAC"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"00000800" report "Wrong Source MAC and EtherType" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"00000800"
+ report "Wrong Source MAC and EtherType"
+ severity FAILURE;
-- IPv4 header
wait until falling_edge(clk) and src_out.valid = '1';
assert src_out.data(31 downto 0) = X"4" &
- TO_UVEC(c_IHL, c_network_ip_header_length_w) &
- X"00" &
+ TO_UVEC(c_IHL, c_network_ip_header_length_w) &
+ X"00" &
TO_UVEC((c_IHL + UDP_payload_len + 2) * 4, c_network_ip_total_length_w)
- report "Wrong Version / IHL / Total Length" severity FAILURE;
+ report "Wrong Version / IHL / Total Length"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"00004000" report "Wrong identification / Flags / Frag Offset" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"00004000"
+ report "Wrong identification / Flags / Frag Offset"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"80110000" report "Wrong TTL / Protocol / Checksum" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"80110000"
+ report "Wrong TTL / Protocol / Checksum"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"0A0B0001" report "Wrong Source IP" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"0A0B0001"
+ report "Wrong Source IP"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"0A0B00FF" report "Wrong Dest IP" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"0A0B00FF"
+ report "Wrong Dest IP"
+ severity FAILURE;
-- No options Here
-- UDP header
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"10FA10FA" report "Wrong UDP ports" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"10FA10FA"
+ report "Wrong UDP ports"
+ severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
assert src_out.data(31 downto 0) = TO_UVEC((UDP_payload_len + 2) * 4, c_network_udp_total_length_w) &
- X"0000"
- report "Wrong UDP length / CRC" severity FAILURE;
+ X"0000"
+ report "Wrong UDP length / CRC"
+ severity FAILURE;
-- UDP payload
for I in 0 to UDP_payload_len - 1 loop
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"BEEF" & TO_UVEC(I, 16) report "Wrong UDP Payload" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"BEEF" & TO_UVEC(I, 16)
+ report "Wrong UDP Payload"
+ severity FAILURE;
-- ASSERT src_out.data(31 downto 0) = X"BEEF" & TO_UVEC(I,16) REPORT "Wrong UDP Payload: 0xBEEF" & TO_UVEC(I,16)'IMAGE SEVERITY FAILURE;
end loop;
-- Eth CRC
wait until falling_edge(clk) and src_out.valid = '1' and src_out.eop <= '1';
- assert src_out.data(31 downto 0) = X"CCCCCCCC" report "Wrong Eth CRC" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"CCCCCCCC"
+ report "Wrong Eth CRC"
+ severity FAILURE;
end procedure check_eth_frame;
begin
clk <= not clk or tb_end after clk_period / 2;
@@ -179,7 +203,9 @@ begin
wait for 1 ms;
if tb_end = '0' then
- assert false report "ERROR: Processing was too long. DUT is stuck" severity FAILURE;
+ assert false
+ report "ERROR: Processing was too long. DUT is stuck"
+ severity FAILURE;
end if;
wait;
end process;
@@ -211,7 +237,9 @@ begin
wait for 1 us;
tb_end <= '1';
- assert false report "Simulation tb_eth_IHL_to_20 finished." severity NOTE;
+ assert false
+ report "Simulation tb_eth_IHL_to_20 finished."
+ severity NOTE;
wait;
end process;
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
index 61a076e891..476110e4cb 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
@@ -551,9 +551,13 @@ begin
tx_hdr_word <= v_word;
-- Verify expected word
if c_use_shortened_header then
- assert c_expected_tx_hdr_word_arr_shortened(I) = v_word report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_shortened(I)) severity ERROR;
+ assert c_expected_tx_hdr_word_arr_shortened(I) = v_word
+ report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_shortened(I))
+ severity ERROR;
else
- assert c_expected_tx_hdr_word_arr_default(I) = v_word report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_default(I)) severity ERROR;
+ assert c_expected_tx_hdr_word_arr_default(I) = v_word
+ report "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr_default(I))
+ severity ERROR;
end if;
end loop;
print_str("", g_print_en);
@@ -620,9 +624,13 @@ begin
rx_hdr_word <= v_word;
-- Verify expected word
if c_use_shortened_header then
- assert v_word = c_expected_rx_hdr_word_arr_shortened(I) report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_shortened(I)) severity ERROR;
+ assert v_word = c_expected_rx_hdr_word_arr_shortened(I)
+ report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_shortened(I))
+ severity ERROR;
else
- assert v_word = c_expected_rx_hdr_word_arr_default(I) report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_default(I)) severity ERROR;
+ assert v_word = c_expected_rx_hdr_word_arr_default(I)
+ report "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr_default(I))
+ severity ERROR;
end if;
end loop;
print_str("", g_print_en);
@@ -637,9 +645,13 @@ begin
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
rx_hdr_word <= v_word; -- View word in wave window
if c_use_shortened_header then
- assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_shortened(0), 1) report "Unexpected dp_bsn from MM" severity ERROR;
+ assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_shortened(0), 1)
+ report "Unexpected dp_bsn from MM"
+ severity ERROR;
else
- assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_default(0), 1) report "Unexpected dp_bsn from MM" severity ERROR;
+ assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_default(0), 1)
+ report "Unexpected dp_bsn from MM"
+ severity ERROR;
end if;
-- dp_sync
if c_use_shortened_header then
@@ -650,7 +662,9 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
rx_hdr_word <= v_word; -- View word in wave window
- assert v_word = TO_UVEC(0, 32) report "Unexpected dp_sync from MM" severity ERROR;
+ assert v_word = TO_UVEC(0, 32)
+ report "Unexpected dp_sync from MM"
+ severity ERROR;
wait;
end process;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
index 4f5554d5c5..8ed87e7f9a 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
@@ -236,7 +236,9 @@ begin
print_str(c_tb_str &
"ETH bit rate :" &
" c_bg_nof_bps = " & real'image(c_bg_nof_bps) & " bps");
- assert c_bg_nof_bps < 10.0**9 report "Tx flow control will keep ETH bitrate < 1Gbps." severity NOTE;
+ assert c_bg_nof_bps < 10.0**9
+ report "Tx flow control will keep ETH bitrate < 1Gbps."
+ severity NOTE;
-------------------------------------------------------------------------
-- Verification: Total counts
@@ -268,19 +270,22 @@ begin
-- Verify, only log when wrong
if c_bg_nof_bps < 10.0**9 then
- assert tx_total_count_nof_packet = tx_exp_total_count_nof_packet report c_tb_str &
- "Wrong Tx total nof packets count, Tx count = " & natural'image(tx_total_count_nof_packet) &
- " /= " & natural'image(tx_exp_total_count_nof_packet) &
+ assert tx_total_count_nof_packet = tx_exp_total_count_nof_packet
+ report c_tb_str &
+ "Wrong Tx total nof packets count, Tx count = " & natural'image(tx_total_count_nof_packet) &
+ " /= " & natural'image(tx_exp_total_count_nof_packet) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_packet = rx_exp_total_count_nof_packet report c_tb_str &
- "Wrong Rx total nof packets count, Rx count = " & natural'image(rx_total_count_nof_packet) &
- " /= " & natural'image(rx_exp_total_count_nof_packet) &
+ assert rx_total_count_nof_packet = rx_exp_total_count_nof_packet
+ report c_tb_str &
+ "Wrong Rx total nof packets count, Rx count = " & natural'image(rx_total_count_nof_packet) &
+ " /= " & natural'image(rx_exp_total_count_nof_packet) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_valid = rx_exp_total_count_nof_valid report c_tb_str &
- "Wrong Rx total nof valids count, Rx count = " & natural'image(rx_total_count_nof_valid) &
- " /= " & natural'image(rx_exp_total_count_nof_valid) &
+ assert rx_total_count_nof_valid = rx_exp_total_count_nof_valid
+ report c_tb_str &
+ "Wrong Rx total nof valids count, Rx count = " & natural'image(rx_total_count_nof_valid) &
+ " /= " & natural'image(rx_exp_total_count_nof_valid) &
" = Expected count" severity ERROR;
end if;
@@ -329,18 +334,29 @@ begin
-- Verify BSN monitors only when the BG sync interval is stable, so
-- the ETH data rate < 1 Gbps and no BG block flow control.
-- Verify, only log when wrong
- assert tx_mon_nof_sop = c_mon_nof_sop_tx report c_tb_str & "Wrong tx nof_sop" severity ERROR;
- assert rx_mon_nof_sop = c_mon_nof_sop_rx report c_tb_str & "Wrong rx nof_sop" severity ERROR;
- assert tx_mon_nof_valid = c_mon_nof_valid_tx report c_tb_str & "Wrong tx nof_valid" severity ERROR;
- assert rx_mon_nof_valid = c_mon_nof_valid_rx report c_tb_str & "Wrong rx nof_valid" severity ERROR;
- assert tx_mon_latency = c_tx_exp_latency report c_tb_str & "Wrong tx latency" severity ERROR;
+ assert tx_mon_nof_sop = c_mon_nof_sop_tx
+ report c_tb_str & "Wrong tx nof_sop"
+ severity ERROR;
+ assert rx_mon_nof_sop = c_mon_nof_sop_rx
+ report c_tb_str & "Wrong rx nof_sop"
+ severity ERROR;
+ assert tx_mon_nof_valid = c_mon_nof_valid_tx
+ report c_tb_str & "Wrong tx nof_valid"
+ severity ERROR;
+ assert rx_mon_nof_valid = c_mon_nof_valid_rx
+ report c_tb_str & "Wrong rx nof_valid"
+ severity ERROR;
+ assert tx_mon_latency = c_tx_exp_latency
+ report c_tb_str & "Wrong tx latency"
+ severity ERROR;
-- For short block lengths the Rx latency appears to become less, the
-- exact Rx latency is therefore hard to predetermine. The actual
-- latency is not critical, therefore it is sufficient to only very
-- the latency when it is more or less fixed.
if c_rx_exp_latency_en then
- assert almost_equal(rx_mon_latency, c_rx_exp_latency_st, 0) report
+ assert almost_equal(rx_mon_latency, c_rx_exp_latency_st, 0)
+ report
c_tb_str & "Wrong rx latency using st interface" severity ERROR;
end if;
end if;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index 96ef9afd24..ca245a0750 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -354,7 +354,9 @@ begin
"ETH bit rate total :" &
" c_bg_nof_bps_total = " & real'image(c_bg_nof_bps_total) & " bps");
end if;
- assert c_bg_nof_bps_total < 10.0**9 report "Tx flow control will keep ETH bitrate < 1Gbps." severity NOTE;
+ assert c_bg_nof_bps_total < 10.0**9
+ report "Tx flow control will keep ETH bitrate < 1Gbps."
+ severity NOTE;
-------------------------------------------------------------------------
-- Verification: Total counts
@@ -394,45 +396,51 @@ begin
-- Verify, only log when wrong
if g_corrupted_en = false then
if c_bg_nof_bps_total < 10.0**9 then
- assert tx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ assert tx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Tx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Rx total nof packets count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ assert rx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof packets count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_valid_arr(I) = rx_exp_total_count_nof_valid_arr(I) report c_tb_str &
- "Wrong Rx total nof valids count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
+ assert rx_total_count_nof_valid_arr(I) = rx_exp_total_count_nof_valid_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof valids count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I) report c_tb_str &
- "Wrong Rx total nof corrupted count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
+ assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof corrupted count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
" = Expected count" severity ERROR;
else
-- Verify that Tx total nof packets = Rx total nof packets, also when
-- BG experiences siso.xon block level flow control, to stay below
-- 1 Gbps of the 1GbE link rate.
- assert tx_total_count_nof_packet_arr(I) = rx_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ assert tx_total_count_nof_packet_arr(I) = rx_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
" = Rx count" severity ERROR;
end if;
else
-- g_corrupted_en = TRUE
- assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I) report c_tb_str &
- "Wrong Rx total nof corrupted count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
+ assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof corrupted count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
" = Expected count" severity ERROR;
end if;
end loop;
@@ -485,17 +493,35 @@ begin
-- the ETH data rate < 1 Gbps and no BG block flow control.
-- Verify, only log when wrong
if I = 0 then
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_rx report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first
+ report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_first
+ report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx
+ report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_rx
+ report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
else
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_rx report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others
+ report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_others
+ report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx
+ report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_rx
+ report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
end if;
- assert tx_mon_latency_arr(I) = c_tx_exp_latency report c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_latency_arr(I) = c_tx_exp_latency
+ report c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")"
+ severity ERROR;
-- For short block lengths the Rx latency appears to become less, the
-- exact Rx latency is therefore hard to predetermine. The actual
@@ -510,15 +536,18 @@ begin
if g_loopback_eth = true then
if g_nof_streams = 1 then
if g_eth_sim_level = 0 then
- assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_tech_tse, 10) report
+ assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_tech_tse, 10)
+ report
c_tb_str & "Wrong rx latency using tech_tse interface" severity ERROR;
elsif g_eth_sim_level = 1 then
- assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_sim_tse, 10) report
+ assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_sim_tse, 10)
+ report
c_tb_str & "Wrong rx latency using sim_tse interface" severity ERROR;
end if;
end if;
else
- assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10) report
+ assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10)
+ report
c_tb_str & "Wrong rx latency using st interface (" & natural'image(I) & ")" severity ERROR;
end if;
end if;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
index 90f4db2db3..b1d9e68fe7 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
@@ -353,37 +353,42 @@ begin
-- Verify, only log when wrong
if c_bg_nof_bps_total < 10.0**9 then
- assert tx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ assert tx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Tx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Rx total nof packets count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ assert rx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof packets count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_valid_arr(I) = rx_exp_total_count_nof_valid_arr(I) report c_tb_str &
- "Wrong Rx total nof valids count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
+ assert rx_total_count_nof_valid_arr(I) = rx_exp_total_count_nof_valid_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof valids count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
" = Expected count" severity ERROR;
- assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I) report c_tb_str &
- "Wrong Rx total nof corrupted count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
+ assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I)
+ report c_tb_str &
+ "Wrong Rx total nof corrupted count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
" = Expected count" severity ERROR;
else
-- Verify that Tx total nof packets = Rx total nof packets, also when
-- BG experiences siso.xon block level flow control, to stay below
-- 1 Gbps of the 1GbE link rate.
- assert tx_total_count_nof_packet_arr(I) = rx_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ assert tx_total_count_nof_packet_arr(I) = rx_total_count_nof_packet_arr(I)
+ report c_tb_str &
+ "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
" = Rx count" severity ERROR;
end if;
end loop;
@@ -436,24 +441,43 @@ begin
-- the ETH data rate < 1 Gbps and no BG block flow control.
-- Verify, only log when wrong
if I = 0 then
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_rx report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first
+ report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_first
+ report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx
+ report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_rx
+ report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
else
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
- assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_rx report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others
+ report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_sop_arr(I) = c_mon_nof_sop_others
+ report c_tb_str & "Wrong rx nof_sop for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx
+ report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
+ assert rx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_rx
+ report c_tb_str & "Wrong rx nof_valid for stream (" & natural'image(I) & ")"
+ severity ERROR;
end if;
- assert tx_mon_latency_arr(I) = c_tx_exp_latency report c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_latency_arr(I) = c_tx_exp_latency
+ report c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")"
+ severity ERROR;
-- For short block lengths the Rx latency appears to become less, the
-- exact Rx latency is therefore hard to predetermine. The actual
-- latency is not critical, therefore it is sufficient to only very
-- the latency when it is more or less fixed.
if c_rx_exp_latency_en then
- assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10) report
+ assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10)
+ report
c_tb_str & "Wrong rx latency using st interface (" & natural'image(I) & ")" severity ERROR;
end if;
end if;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
index 14ea6f5af1..f9480ff638 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
@@ -359,7 +359,9 @@ begin
begin
wait until tb_end = '1';
wait for 10 us;
- assert false report "Simulation tb_eth_udp_offload finished." severity NOTE;
+ assert false
+ report "Simulation tb_eth_udp_offload finished."
+ severity NOTE;
wait;
end process;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
index f0db304df3..c62aac3708 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
@@ -74,7 +74,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
index 5d5731ec82..bd7dc11045 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
@@ -221,7 +221,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
index b22af44ba5..febedbf79f 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
@@ -162,7 +162,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
index 1c7c417a59..8bb2f3f2ec 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
@@ -642,19 +642,24 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt + rx_pkt_discarded_cnt + TO_UINT(rx_pkt_flushed_cnt) then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
wait for 1 us;
tb_end <= '1';
if g_tb_end = false then
- report "Tb simulation finished." severity NOTE;
+ report "Tb simulation finished."
+ severity NOTE;
else
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
index 98f9c0ae04..eed13173ae 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
@@ -71,7 +71,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
index 9a20f6b167..2f9f6fa97e 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
@@ -271,7 +271,8 @@ begin
protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w - 1 downto 0));
proc_common_wait_some_cycles(clk, 1);
assert c_protocol_ram_init(I) = protocol_data
- report "Unexpected protocol data" severity ERROR;
+ report "Unexpected protocol data"
+ severity ERROR;
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
proc_mem_mm_bus_rd(I, clk, protocol_miso, protocol_mosi);
@@ -279,7 +280,8 @@ begin
protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w - 1 downto 0));
proc_common_wait_some_cycles(clk, 1);
assert SMBUS_C_END = protocol_data
- report "Unexpected protocol end data" severity ERROR;
+ report "Unexpected protocol end data"
+ severity ERROR;
end loop;
end if;
@@ -322,7 +324,8 @@ begin
result_error_cnt <= TO_UINT(commander_miso.rddata);
proc_common_wait_some_cycles(clk, 1);
assert result_error_cnt = 0
- report "The result error count is not 0" severity ERROR;
+ report "The result error count is not 0"
+ severity ERROR;
-- Read commander result data
for I in 0 to c_nof_result_data_arr(P) - 1 loop
@@ -331,7 +334,8 @@ begin
result_data <= TO_UINT(commander_miso.rddata);
proc_common_wait_some_cycles(clk, 1);
assert c_expected_data_mat(P)(I) = result_data
- report "Unexpected result data" severity ERROR;
+ report "Unexpected result data"
+ severity ERROR;
end loop;
-- Wait for protocol idle
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
index 352690a6f6..70a41a6ba6 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
@@ -214,7 +214,8 @@ begin
protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w - 1 downto 0));
proc_common_wait_some_cycles(clk, 1);
assert c_protocol_ram_init(I) = protocol_data
- report "Unexpected protocol data" severity ERROR;
+ report "Unexpected protocol data"
+ severity ERROR;
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
proc_mem_mm_bus_rd(I, clk, protocol_miso, protocol_mosi);
@@ -222,7 +223,8 @@ begin
protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w - 1 downto 0));
proc_common_wait_some_cycles(clk, 1);
assert SMBUS_C_END = protocol_data
- report "Unexpected protocol end data" severity ERROR;
+ report "Unexpected protocol end data"
+ severity ERROR;
end loop;
end if;
@@ -265,7 +267,8 @@ begin
result_error_cnt <= TO_UINT(commander_miso.rddata);
proc_common_wait_some_cycles(clk, 1);
assert result_error_cnt = 0
- report "The result error count is not 0" severity ERROR;
+ report "The result error count is not 0"
+ severity ERROR;
-- Read commander result data
for I in 0 to c_nof_result_data_arr(P) - 1 loop
@@ -274,7 +277,8 @@ begin
result_data <= TO_UINT(commander_miso.rddata);
proc_common_wait_some_cycles(clk, 1);
assert c_expected_data_mat(P)(I) = result_data
- report "Unexpected result data" severity WARNING;
+ report "Unexpected result data"
+ severity WARNING;
end loop;
-- Wait for protocol idle
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
index 065b2c384d..03907440b8 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
@@ -219,7 +219,8 @@ begin
protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w - 1 downto 0));
proc_common_wait_some_cycles(clk, 1);
assert c_protocol_ram_init(I) = protocol_data
- report "Unexpected protocol data" severity ERROR;
+ report "Unexpected protocol data"
+ severity ERROR;
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
proc_mem_mm_bus_rd(I, clk, protocol_miso, protocol_mosi);
@@ -227,7 +228,8 @@ begin
protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w - 1 downto 0));
proc_common_wait_some_cycles(clk, 1);
assert SMBUS_C_END = protocol_data
- report "Unexpected protocol end data" severity ERROR;
+ report "Unexpected protocol end data"
+ severity ERROR;
end loop;
end if;
@@ -270,7 +272,8 @@ begin
result_error_cnt <= TO_UINT(commander_miso.rddata);
proc_common_wait_some_cycles(clk, 1);
assert result_error_cnt = 0
- report "The result error count is not 0" severity ERROR;
+ report "The result error count is not 0"
+ severity ERROR;
-- Read commander result data
for I in 0 to c_nof_result_data_arr(P) - 1 loop
@@ -279,7 +282,8 @@ begin
result_data <= TO_UINT(commander_miso.rddata);
proc_common_wait_some_cycles(clk, 1);
assert c_expected_data_mat(P)(I) = result_data
- report "Unexpected result data" severity WARNING;
+ report "Unexpected result data"
+ severity WARNING;
end loop;
-- Wait for protocol idle
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
index ca4e441e2a..fb37baedd3 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
@@ -224,7 +224,9 @@ begin
proc_common_wait_some_cycles(clk, 100);
-- verify that there happened valid I2C communication
- assert result_cnt = expected_cnt report "I2C error in nof result count" severity ERROR;
+ assert result_cnt = expected_cnt
+ report "I2C error in nof result count"
+ severity ERROR;
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
@@ -250,11 +252,13 @@ begin
if result_val = '1' then
if c_expected_mask(result_cnt) = 0 then
if TO_UINT(result_data) /= 0 then
- report "I2C error in control result byte" severity ERROR;
+ report "I2C error in control result byte"
+ severity ERROR;
end if;
else
if TO_UINT(result_data) /= expected_data then
- report "I2C error in control result byte" severity ERROR;
+ report "I2C error in control result byte"
+ severity ERROR;
end if;
end if;
end if;
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy.vhd b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
index 3f6b278be9..f753401492 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
@@ -242,7 +242,9 @@ begin
end if;
when others =>
- assert false report "Uknown state." severity Failure;
+ assert false
+ report "Uknown state."
+ severity Failure;
nxt_state <= s_idle;
end case;
end process;
diff --git a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
index 9f0b403713..9c8ab33c5f 100644
--- a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
+++ b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
@@ -122,7 +122,8 @@ begin
v_match := true;
end if;
else
- report "Preamble too long, not supported by this slave model" severity FAILURE;
+ report "Preamble too long, not supported by this slave model"
+ severity FAILURE;
v_match := false;
state <= s_idle;
end if;
@@ -213,7 +214,9 @@ begin
end if;
when others => -- can not occur
- assert false report "Unknown MDIO state." severity FAILURE;
+ assert false
+ report "Unknown MDIO state."
+ severity FAILURE;
end case;
if v_match = false then
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
index 1822ffda11..6dfe0ee3c4 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
@@ -171,9 +171,11 @@ begin
-- Check read back value
----------------------------------------------------------------------------
if phy_readdata = c_phy_data then
- report "Write MDIO slave reg and readback went OK" severity NOTE;
+ report "Write MDIO slave reg and readback went OK"
+ severity NOTE;
else
- report "Write MDIO slave reg and readback went wrong" severity ERROR;
+ report "Write MDIO slave reg and readback went wrong"
+ severity ERROR;
end if;
tb_end <= '1';
wait;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
index f697479167..7c278ee42b 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
@@ -130,9 +130,11 @@ begin
-- Check read back value
----------------------------------------------------------------------------
if rx_dat = c_phy_data then
- report "Write MDIO slave reg and readback went OK" severity NOTE;
+ report "Write MDIO slave reg and readback went OK"
+ severity NOTE;
else
- report "Write MDIO slave reg and readback went wrong" severity ERROR;
+ report "Write MDIO slave reg and readback went wrong"
+ severity ERROR;
end if;
----------------------------------------------------------------------------
@@ -166,9 +168,11 @@ begin
-- Check read back value
----------------------------------------------------------------------------
if rx_dat = c_phy_data then
- report "Write MDIO slave reg and readback went OK" severity NOTE;
+ report "Write MDIO slave reg and readback went OK"
+ severity NOTE;
else
- report "Write MDIO slave reg and readback went wrong" severity ERROR;
+ report "Write MDIO slave reg and readback went wrong"
+ severity ERROR;
end if;
tb_end <= '1';
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
index 9b5a2bcdd2..d1176feacc 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
@@ -96,9 +96,11 @@ begin
-- Check read back value
----------------------------------------------------------------------------
if rx_dat = c_phy_data then
- report "Write MDIO slave reg and readback went OK" severity NOTE;
+ report "Write MDIO slave reg and readback went OK"
+ severity NOTE;
else
- report "Write MDIO slave reg and readback went wrong" severity ERROR;
+ report "Write MDIO slave reg and readback went wrong"
+ severity ERROR;
end if;
tb_end <= '1';
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
index 0ce05943ac..bbe3a85b21 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
@@ -166,9 +166,11 @@ begin
proc_common_wait_some_cycles(clk, c_delay);
if phy_readdata = c_phy_data then
- report "Write MDIO slave reg and readback went OK" severity NOTE;
+ report "Write MDIO slave reg and readback went OK"
+ severity NOTE;
else
- report "Write MDIO slave reg and readback went wrong" severity ERROR;
+ report "Write MDIO slave reg and readback went wrong"
+ severity ERROR;
end if;
tb_end <= '1';
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
index f5af904d95..ba3b5c7df1 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
@@ -82,7 +82,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
index 65be3c0f2f..06de4b3a39 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
@@ -141,46 +141,86 @@ begin
proc_common_wait_some_cycles(st_clk, c_pps_period / 2); -- Verification offset
-- 1
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '0' report "1) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1000 report "1) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '0'
+ report "1) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1000
+ report "1) Wrong capture_cnt"
+ severity ERROR;
-- 2
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '1' report "2) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1000 report "2) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '1'
+ report "2) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1000
+ report "2) Wrong capture_cnt"
+ severity ERROR;
-- 3
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '0' report "3) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 999 report "3) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '0'
+ report "3) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 999
+ report "3) Wrong capture_cnt"
+ severity ERROR;
-- 4
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '0' report "4) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1000 report "4) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '0'
+ report "4) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1000
+ report "4) Wrong capture_cnt"
+ severity ERROR;
-- 5
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '1' report "5) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1000 report "5) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '1'
+ report "5) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1000
+ report "5) Wrong capture_cnt"
+ severity ERROR;
-- 6
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '1' report "6) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1000 report "6) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '1'
+ report "6) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1000
+ report "6) Wrong capture_cnt"
+ severity ERROR;
-- 7
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '0' report "7) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1001 report "7) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '0'
+ report "7) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1001
+ report "7) Wrong capture_cnt"
+ severity ERROR;
-- 8
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '0' report "8) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1000 report "8) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '0'
+ report "8) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1000
+ report "8) Wrong capture_cnt"
+ severity ERROR;
-- 9
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
- assert pps_stable = '1' report "9) Wrong pps_stable" severity ERROR;
- assert capture_cnt = 1000 report "9) Wrong capture_cnt" severity ERROR;
+ assert pps_stable = '1'
+ report "9) Wrong pps_stable"
+ severity ERROR;
+ assert capture_cnt = 1000
+ report "9) Wrong capture_cnt"
+ severity ERROR;
-- 10
proc_common_wait_some_cycles(st_clk, c_pps_period / 10);
- assert offset_cnt = last_offset_cnt report "10) Wrong offset_cnt" severity ERROR;
+ assert offset_cnt = last_offset_cnt
+ report "10) Wrong offset_cnt"
+ severity ERROR;
-- 11
proc_common_wait_some_cycles(st_clk, c_pps_period / 10);
- assert offset_cnt = last_offset_cnt report "11) Wrong offset_cnt" severity ERROR;
+ assert offset_cnt = last_offset_cnt
+ report "11) Wrong offset_cnt"
+ severity ERROR;
wait;
end process;
diff --git a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
index e54dd7851d..3cba0ad705 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
@@ -90,7 +90,8 @@ begin
pps_stable_ack <= '0';
wait for 9000 ms; -- wait until p_capture_edge is done
if pps_stable /= '0' then
- report "PPSH : Unexpected pps_stable, should be 0." severity ERROR;
+ report "PPSH : Unexpected pps_stable, should be 0."
+ severity ERROR;
end if;
-- ack PPS stable monitor
pps_stable_ack <= '1';
@@ -98,11 +99,13 @@ begin
pps_stable_ack <= '0';
wait for 10 ms;
if pps_stable /= '1' then
- report "PPSH : Unexpected pps_stable, should be 1." severity ERROR;
+ report "PPSH : Unexpected pps_stable, should be 1."
+ severity ERROR;
end if;
wait for 13000 ms; -- wait until first loop in p_pps_default_period is done
if pps_stable /= '0' then
- report "PPSH : Unexpected pps_stable, should have become 0." severity ERROR;
+ report "PPSH : Unexpected pps_stable, should have become 0."
+ severity ERROR;
end if;
wait;
end process;
@@ -212,27 +215,31 @@ begin
unsigned(capture_cnt) /= c_clk_freq - 1 and
unsigned(capture_cnt) /= 0 and
unsigned(capture_cnt) /= 2**capture_cnt'length - 1 then
- report "PPSH : Unexpected capture count value." severity ERROR;
+ report "PPSH : Unexpected capture count value."
+ severity ERROR;
end if;
-- Verify influence of PPS capture edge selection
if (NOW > 6000 ms) and (NOW <= 6000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq + 1 then
- report "PPSH : Unexpected capture count value at 6 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 6 s."
+ severity ERROR;
end if;
verify_s <= 6.0;
end if;
if (NOW > 7000 ms) and (NOW <= 7000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq then
- report "PPSH : Unexpected capture count value at 7 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 7 s."
+ severity ERROR;
end if;
verify_s <= 7.0;
end if;
if (NOW > 8000 ms) and (NOW <= 8000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq - 1 then
- report "PPSH : Unexpected capture count value at 8 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 8 s."
+ severity ERROR;
end if;
verify_s <= 8.0;
end if;
@@ -240,49 +247,56 @@ begin
-- Verify external PPS period fluctuations at specific stimuli moments
if (NOW > 10000 ms) and (NOW <= 10000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq then
- report "PPSH : Unexpected capture count value at 10 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 10 s."
+ severity ERROR;
end if;
verify_s <= 10.0;
end if;
if (NOW > 22000 ms) and (NOW <= 22000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq - 1 then
- report "PPSH : Unexpected capture count value at 22 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 22 s."
+ severity ERROR;
end if;
verify_s <= 22.0;
end if;
if (NOW > 25000 ms) and (NOW <= 25000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq then
- report "PPSH : Unexpected capture count value at 25 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 25 s."
+ severity ERROR;
end if;
verify_s <= 25.0;
end if;
if (NOW > 28000 ms) and (NOW <= 28000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq + 1 then
- report "PPSH : Unexpected capture count value at 28 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 28 s."
+ severity ERROR;
end if;
verify_s <= 28.0;
end if;
if (NOW > 30000 ms) and (NOW <= 30000 ms + c_clk_period) then
if unsigned(capture_cnt) /= c_clk_freq then
- report "PPSH : Unexpected capture count value at 30 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 30 s."
+ severity ERROR;
end if;
verify_s <= 30.0;
end if;
if (NOW > 35000 ms) and (NOW <= 35000 ms + c_clk_period) then
if unsigned(capture_cnt) /= 2**capture_cnt'length - 1 then
- report "PPSH : Unexpected capture count value at 35 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 35 s."
+ severity ERROR;
end if;
verify_s <= 35.0;
end if;
if (NOW > 49000 ms) and (NOW <= 49000 ms + c_clk_period) then
if unsigned(capture_cnt) /= 2**capture_cnt'length - 1 then
- report "PPSH : Unexpected capture count value at 49 s." severity ERROR;
+ report "PPSH : Unexpected capture count value at 49 s."
+ severity ERROR;
end if;
verify_s <= 49.0;
end if;
@@ -290,14 +304,16 @@ begin
-- check if offset_cnt is counting
if (NOW > 7500 ms) and (NOW <= 7500 ms + c_clk_period) then
if unsigned(offset_cnt) /= 475 then
- report "PPSH : Unexpected offset count value at 7.5 s." severity ERROR;
+ report "PPSH : Unexpected offset count value at 7.5 s."
+ severity ERROR;
end if;
verify_s <= 7.5;
end if;
if (NOW > 7700 ms) and (NOW <= 7700 ms + c_clk_period) then
if unsigned(offset_cnt) /= 675 then
- report "PPSH : Unexpected offset count value at 7.7 s." severity ERROR;
+ report "PPSH : Unexpected offset count value at 7.7 s."
+ severity ERROR;
end if;
verify_s <= 7.7;
end if;
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
index a07ba8b66f..3940f49fbf 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
@@ -80,7 +80,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
index 1f7f9a16d2..280a320b41 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
@@ -50,9 +50,12 @@ begin
p_tb_end : process
begin
wait until tb_end = '1';
- assert (c_tech_select_default = c_tech_stratixiv) report "Technology is not stratixiv, skipping testbench..." severity WARNING;
+ assert (c_tech_select_default = c_tech_stratixiv)
+ report "Technology is not stratixiv, skipping testbench..."
+ severity WARNING;
wait for 1 ms;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
index 623b6e66aa..cf018611c2 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
@@ -282,10 +282,18 @@ begin
p_verify : process(verify_en, bn_snk_diag_res_val, bn_snk_diag_res, fn_snk_diag_res_val, fn_snk_diag_res)
begin
if verify_en = '1' then
- assert bn_snk_diag_res_val = c_slv1(c_nof_gx - 1 downto 0) report "BN rx diag not valid error" severity ERROR;
- assert bn_snk_diag_res = c_slv0(c_nof_gx - 1 downto 0) report "BN rx diag data error" severity ERROR;
- assert fn_snk_diag_res_val = c_slv1(c_nof_gx - 1 downto 0) report "FN rx diag not valid error" severity ERROR;
- assert fn_snk_diag_res = c_slv0(c_nof_gx - 1 downto 0) report "FN rx diag data error" severity ERROR;
+ assert bn_snk_diag_res_val = c_slv1(c_nof_gx - 1 downto 0)
+ report "BN rx diag not valid error"
+ severity ERROR;
+ assert bn_snk_diag_res = c_slv0(c_nof_gx - 1 downto 0)
+ report "BN rx diag data error"
+ severity ERROR;
+ assert fn_snk_diag_res_val = c_slv1(c_nof_gx - 1 downto 0)
+ report "FN rx diag not valid error"
+ severity ERROR;
+ assert fn_snk_diag_res = c_slv0(c_nof_gx - 1 downto 0)
+ report "FN rx diag data error"
+ severity ERROR;
end if;
end process;
@@ -296,9 +304,11 @@ begin
wait for 50 us;
tb_end <= '1';
if g_tb_end = false then
- report "Tb Simulation finished." severity NOTE;
+ report "Tb Simulation finished."
+ severity NOTE;
else
- report "Tb Simulation finished." severity FAILURE;
+ report "Tb Simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
index efe6772df5..d893dc78e1 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
@@ -51,7 +51,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
index ba35ff1c89..ff4a974661 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
@@ -136,9 +136,11 @@ begin
-- Stop the simulation
tb_end <= '1';
if g_tb_end = false then
- report "Tb Simulation finished." severity NOTE;
+ report "Tb Simulation finished."
+ severity NOTE;
else
- report "Tb Simulation finished." severity FAILURE;
+ report "Tb Simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
@@ -155,7 +157,9 @@ begin
begin
if rising_edge(rx_clk) then
if verify_en = '1' then
- assert unsigned(snk_diag_res) = 0 and signed(snk_diag_res_val) = -1 report "tb_tr_xaui : Wrong diagnostics result value" severity ERROR;
+ assert unsigned(snk_diag_res) = 0 and signed(snk_diag_res_val) = -1
+ report "tb_tr_xaui : Wrong diagnostics result value"
+ severity ERROR;
end if;
end if;
end process;
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd
index f2b093acab..1093a80ba5 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd
@@ -125,7 +125,9 @@ begin
-- Stop the simulation
tb_end <= '1';
- assert false report "Simulation finished." severity NOTE;
+ assert false
+ report "Simulation finished."
+ severity NOTE;
wait;
end process;
diff --git a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
index 1ca8d66bf7..88e05741e1 100644
--- a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
@@ -103,7 +103,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
wait;
end process;
diff --git a/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd b/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
index e911163a9e..0cb16b557d 100644
--- a/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
@@ -117,10 +117,12 @@ begin
p_verify : process(clk)
begin
if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at falling edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at falling edge";
end if;
if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at rising edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
end tb;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
index 404edfb6b6..5ddb58a6a6 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
@@ -97,7 +97,9 @@ architecture SYN of ip_agi027_1e1v_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_agi027_1e1v_ram_cr_cw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
index 73342ddfb0..783707ecab 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
@@ -103,7 +103,9 @@ architecture SYN of ip_agi027_1e1v_ram_crk_cw is
end component;
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_crk_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_agi027_1e1v_ram_crk_cw : read latency must be 1 (default) or 2"
+ severity FAILURE;
u_altera_syncram : altera_syncram
generic map (
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
index 2024e3de75..f17b57890b 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
@@ -95,7 +95,9 @@ architecture SYN of ip_agi027_1e1v_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_agi027_1e1v_ram_r_w : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
index b0110c61d5..2728a1373e 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
@@ -117,7 +117,9 @@ architecture SYN of ip_agi027_1e1v_ram_rw_rw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_agi027_1e1v_ram_rw_rw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
diff --git a/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
index 322a320bac..08749d90f2 100644
--- a/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
+++ b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
@@ -112,10 +112,12 @@ begin
p_verify : process(clk)
begin
if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_ddio_1: Error, unexpeced data at falling edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_ddio_1: Error, unexpeced data at falling edge";
end if;
if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_ddio_1: Error, unexpeced data at rising edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
index aae0526f13..90349c3b99 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
@@ -92,7 +92,9 @@ architecture SYN of ip_arria10_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_ram_cr_cw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_ram_cr_cw/ram_2port_140/sim/ip_arria10_ram_cr_cw_ram_2port_140_72tpmcy.vhd
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
index 0623c7ea71..0468c1636d 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
@@ -108,7 +108,9 @@ architecture SYN of ip_arria10_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_ram_crw_crw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_ram_crw_crw/ram_2port_140/sim/ip_arria10_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
index b661c825c2..b00fa8271b 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
@@ -89,7 +89,9 @@ architecture SYN of ip_arria10_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_ram_r_w : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_ram_r_w/ram_2port_140/sim/ip_arria10_ram_r_w_ram_2port_140_hukd7xi.vhd
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
index cd1d8282ea..d67636a264 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
@@ -339,17 +339,29 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -361,12 +373,16 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -384,7 +400,9 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -392,7 +410,9 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -727,15 +747,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
index e5ad6682c9..6b9cecf757 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
@@ -342,17 +342,29 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -364,12 +376,16 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -387,7 +403,9 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -395,7 +413,9 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -709,15 +729,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
index fc77aadfc8..bdaf3ed315 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
@@ -112,10 +112,12 @@ begin
p_verify : process(clk)
begin
if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at falling edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at falling edge";
end if;
if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at rising edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
index a39c8c4058..1c75242119 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
@@ -92,7 +92,9 @@ architecture SYN of ip_arria10_e1sg_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e1sg_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e1sg_ram_cr_cw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e1sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e1sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
index 00a9c179e4..3e5905d0a0 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
@@ -108,7 +108,9 @@ architecture SYN of ip_arria10_e1sg_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e1sg_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e1sg_ram_crw_crw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e1sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
index b1f010f12a..e120f25745 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
@@ -89,7 +89,9 @@ architecture SYN of ip_arria10_e1sg_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e1sg_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e1sg_ram_r_w : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e1sg_ram_r_w/ram_2port_140/sim/ip_arria10_e1sg_ram_r_w_ram_2port_140_hukd7xi.vhd
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
index 5a53d30972..c34c3da846 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
@@ -339,17 +339,29 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -361,12 +373,16 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -384,7 +400,9 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -392,7 +410,9 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -727,15 +747,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
index 1fcf8f332f..48a6a2f985 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
@@ -342,17 +342,29 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -364,12 +376,16 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -387,7 +403,9 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -395,7 +413,9 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -709,15 +729,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
index 11481111e8..d86ac57715 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
@@ -112,10 +112,12 @@ begin
p_verify : process(clk)
begin
if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at falling edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at falling edge";
end if;
if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at rising edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
index 1c729b5a1f..b3c7996041 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
@@ -93,7 +93,9 @@ architecture SYN of ip_arria10_e2sg_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e2sg_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e2sg_ram_cr_cw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e2sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e2sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
index 8d7ed900e9..8fc3d6cdb2 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -109,7 +109,9 @@ architecture SYN of ip_arria10_e2sg_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e2sg_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e2sg_ram_crw_crw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
index 5f5c45d246..0c5cf62ba1 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
@@ -89,7 +89,9 @@ architecture SYN of ip_arria10_e2sg_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e2sg_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e2sg_ram_r_w : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e2sg_ram_r_w/ram_2port_140/sim/ip_arria10_e2sg_ram_r_w_ram_2port_140_hukd7xi.vhd
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
index d4639eafa1..b48037f8d5 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
@@ -339,17 +339,29 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_gx is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -361,12 +373,16 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -384,7 +400,9 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -392,7 +410,9 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_gx is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -727,15 +747,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
index 7ee9e483be..ebfade5dbe 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
@@ -342,17 +342,29 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_lvds is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -364,12 +376,16 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -387,7 +403,9 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -395,7 +413,9 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_lvds is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -709,15 +729,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
index b03e85e474..de5b09afae 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
@@ -112,10 +112,12 @@ begin
p_verify : process(clk)
begin
if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at falling edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at falling edge";
end if;
if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at rising edge";
+ assert out_dat = out_dat_exp
+ report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
index 0ef9b7ea3f..7f8749f641 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
@@ -92,7 +92,9 @@ architecture SYN of ip_arria10_e3sge3_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e3sge3_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e3sge3_ram_cr_cw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e3sge3_ram_cr_cw/ram_2port_140/sim/ip_arria10_e3sge3_ram_cr_cw_ram_2port_140_72tpmcy.vhd
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
index 9ee98ecdf2..9dbfceaedf 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
@@ -108,7 +108,9 @@ architecture SYN of ip_arria10_e3sge3_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e3sge3_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e3sge3_ram_crw_crw : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e3sge3_ram_crw_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
index c428676d10..35128814f5 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
@@ -89,7 +89,9 @@ architecture SYN of ip_arria10_e3sge3_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e3sge3_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_arria10_e3sge3_ram_r_w : read latency must be 1 (default) or 2"
+ severity FAILURE;
gen_ip : if g_inferred = false generate
-- Copied from ip_arria10_e3sge3_ram_r_w/ram_2port_140/sim/ip_arria10_e3sge3_ram_r_w_ram_2port_140_hukd7xi.vhd
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd
index b95e10bb59..0ef8de91b2 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd
@@ -339,17 +339,29 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_gx is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -361,12 +373,16 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -384,7 +400,9 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_gx is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -392,7 +410,9 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_gx is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -727,15 +747,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
index f5617ba27a..75d0da1d57 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
@@ -342,17 +342,29 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_lvds is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -364,12 +376,16 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -387,7 +403,9 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -395,7 +413,9 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_lvds is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -709,15 +729,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
index 947d81825c..a71d4b4ed8 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
@@ -166,13 +166,17 @@ begin
wait for 2 us;
assert xgmii_rx_d = c_xgmii_d_test or
xgmii_rx_d = c_xgmii_d_test(31 downto 0) & c_xgmii_d_test(63 downto 32)
- report "tb_ip_stratixiv_phy_xaui : Wrong xgmii_rx_d result value" severity ERROR;
+ report "tb_ip_stratixiv_phy_xaui : Wrong xgmii_rx_d result value"
+ severity ERROR;
wait for g_sim_time - 2 us;
assert xgmii_rx_d = c_xgmii_d_test or
xgmii_rx_d = c_xgmii_d_test(31 downto 0) & c_xgmii_d_test(63 downto 32)
- report "tb_ip_stratixiv_phy_xaui : Wrong xgmii_rx_d result value" severity ERROR;
+ report "tb_ip_stratixiv_phy_xaui : Wrong xgmii_rx_d result value"
+ severity ERROR;
end if;
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
index e39939d794..2b39421c4d 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
@@ -342,17 +342,29 @@ architecture tb of tb_ip_stratixiv_tse_sgmii_lvds is
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- assert dp_snk_in.data(31 downto 16) = X"0000" report "RX: Alignment half word not zero" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0)) report "RX: Wrong dst_mac_addr(15 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Alignment half word not zero"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(dst_mac_addr(15 downto 0))
+ report "RX: Wrong dst_mac_addr(15 downto 0)"
+ severity ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16)) report "RX: Wrong dst_mac_addr(47 downto 16)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(dst_mac_addr(47 downto 16))
+ report "RX: Wrong dst_mac_addr(47 downto 16)"
+ severity ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0)) report "RX: Wrong src_mac_addr(31 downto 0)" severity ERROR;
+ assert dp_snk_in.data(31 downto 0) = hton(src_mac_addr(31 downto 0))
+ report "RX: Wrong src_mac_addr(31 downto 0)"
+ severity ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32)) report "RX: Wrong src_mac_addr(47 downto 32)" severity ERROR;
- assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype) report "RX: Wrong ethertype" severity ERROR;
+ assert dp_snk_in.data(31 downto 16) = hton(src_mac_addr(47 downto 32))
+ report "RX: Wrong src_mac_addr(47 downto 32)"
+ severity ERROR;
+ assert dp_snk_in.data(15 downto 0) = hton(c_eth_ethertype)
+ report "RX: Wrong ethertype"
+ severity ERROR;
-- Verify DATA
v_first := true;
proc_valid(dp_clk, dp_snk_in.valid);
@@ -364,12 +376,16 @@ architecture tb of tb_ip_stratixiv_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
end if;
v_first := false;
@@ -387,7 +403,9 @@ architecture tb of tb_ip_stratixiv_tse_sgmii_lvds is
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
- assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end loop;
else
-- data : X"00000001", X"00000002", X"00000003", etc
@@ -395,7 +413,9 @@ architecture tb of tb_ip_stratixiv_tse_sgmii_lvds is
for J in v_empty - 1 downto 0 loop
v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
else
-- No verify on CRC32 word
@@ -702,15 +722,20 @@ begin
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
-- Stop the simulation
- assert false report "Simulation finished." severity FAILURE;
+ assert false
+ report "Simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
index 2fc9f11faa..b20fa8e7c6 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
@@ -51,9 +51,13 @@ end ip_ultrascale_ram_cr_cw;
architecture SYN of ip_ultrascale_ram_cr_cw is
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_ultrascale_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_ultrascale_ram_cr_cw : read latency must be 1 (default) or 2"
+ severity FAILURE;
- assert g_inferred = false report "ip_ultrascale_ram_crw_crw : cannot infer RAM" severity FAILURE;
+ assert g_inferred = false
+ report "ip_ultrascale_ram_crw_crw : cannot infer RAM"
+ severity FAILURE;
-- xpm_memory_sdpram: Simple Dual Port RAM
-- Xilinx Parameterized Macro, version 2022.1
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
index 9f9d96612e..16b83747fd 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
@@ -54,8 +54,12 @@ end ip_ultrascale_ram_crw_crw;
architecture SYN of ip_ultrascale_ram_crw_crw is
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_ultrascale_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
- assert g_inferred = false report "ip_ultrascale_ram_crw_crw : cannot infer RAM" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2
+ report "ip_ultrascale_ram_crw_crw : read latency must be 1 (default) or 2"
+ severity FAILURE;
+ assert g_inferred = false
+ report "ip_ultrascale_ram_crw_crw : cannot infer RAM"
+ severity FAILURE;
-- xpm_memory_tdpram: True Dual Port RAM
-- Xilinx Parameterized Macro, version 2022.1
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index c3ee7ab19d..e241e15f74 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -220,12 +220,14 @@ begin
proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_enable_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
assert unsigned(jesd204b_rddata) = tech_jesd204b_field_rx_err_enable_reset
- report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset) severity ERROR;
+ report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset)
+ severity ERROR;
proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_link_reinit_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
assert unsigned(jesd204b_rddata) = tech_jesd204b_field_rx_err_link_reinit_reset
- report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset) severity ERROR;
+ report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset)
+ severity ERROR;
proc_mem_mm_bus_rd(tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
@@ -519,7 +521,9 @@ begin
begin
wait for 2 * c_sysref_period * c_jesd204b_sampclk_period;
- assert sim_done = '1' report "No rx samples were received." severity ERROR;
+ assert sim_done = '1'
+ report "No rx samples were received."
+ severity ERROR;
wait for 10 us;
tb_end <= '1';
end process;
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
index 9376a133bf..8a7c106faa 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
@@ -223,12 +223,14 @@ begin
proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_enable_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
assert unsigned(jesd204b_rddata) = tech_jesd204b_field_rx_err_enable_reset
- report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset) severity ERROR;
+ report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset)
+ severity ERROR;
proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_link_reinit_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
assert unsigned(jesd204b_rddata) = tech_jesd204b_field_rx_err_link_reinit_reset
- report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset) severity ERROR;
+ report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(jesd204b_rddata)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset)
+ severity ERROR;
proc_mem_mm_bus_rd(tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
@@ -529,7 +531,9 @@ begin
begin
wait for 2 * c_sysref_period * c_jesd204b_sampclk_period;
- assert sim_done = '1' report "No rx samples were received." severity ERROR;
+ assert sim_done = '1'
+ report "No rx samples were received."
+ severity ERROR;
wait for 10 us;
tb_end <= '1';
end process;
diff --git a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
index bedceebc63..02fdaf8f18 100644
--- a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
@@ -57,7 +57,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
index 40274bb238..b7c1ec7b6b 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
@@ -345,17 +345,31 @@ package body tb_tech_mac_10g_pkg is
----------------------------------------------------------------------------
-- . wait for sop
proc_dp_stream_valid_sop(ff_clk, ff_snk_in.valid, ff_snk_in.sop);
- assert ff_snk_in.data(63 downto 16) = X"00000000_0000" report "RX: Wrong ETH alignment padding not zero" severity ERROR;
- assert ff_snk_in.data(15 downto 0) = c_eth_header.dst_mac(47 downto 32) report "RX: Wrong ETH dst_mac_addr(47 downto 32)" severity ERROR;
+ assert ff_snk_in.data(63 downto 16) = X"00000000_0000"
+ report "RX: Wrong ETH alignment padding not zero"
+ severity ERROR;
+ assert ff_snk_in.data(15 downto 0) = c_eth_header.dst_mac(47 downto 32)
+ report "RX: Wrong ETH dst_mac_addr(47 downto 32)"
+ severity ERROR;
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
- assert ff_snk_in.data(63 downto 32) = c_eth_header.dst_mac(31 downto 0) report "RX: Wrong ETH dst_mac_addr(31 downto 0)" severity ERROR;
- assert ff_snk_in.data(31 downto 0) = c_eth_header.src_mac(47 downto 16) report "RX: Wrong ETH src_mac_addr(47 downto 16)" severity ERROR;
+ assert ff_snk_in.data(63 downto 32) = c_eth_header.dst_mac(31 downto 0)
+ report "RX: Wrong ETH dst_mac_addr(31 downto 0)"
+ severity ERROR;
+ assert ff_snk_in.data(31 downto 0) = c_eth_header.src_mac(47 downto 16)
+ report "RX: Wrong ETH src_mac_addr(47 downto 16)"
+ severity ERROR;
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
- assert ff_snk_in.data(63 downto 48) = c_eth_header.src_mac(15 downto 0) report "RX: Wrong ETH src_mac_addr(15 downto 0)" severity ERROR;
- assert ff_snk_in.data(47 downto 32) = c_eth_header.eth_type report "RX: Wrong ETH ethertype" severity ERROR;
+ assert ff_snk_in.data(63 downto 48) = c_eth_header.src_mac(15 downto 0)
+ report "RX: Wrong ETH src_mac_addr(15 downto 0)"
+ severity ERROR;
+ assert ff_snk_in.data(47 downto 32) = c_eth_header.eth_type
+ report "RX: Wrong ETH ethertype"
+ severity ERROR;
-- . verify remaining half word
- assert ff_snk_in.data(31 downto 0) = v_hdr_words_arr(c_nof_eth_beats - 1)(31 downto 0) report "RX: Wrong " & v_hdr_string & " response half word" severity ERROR;
+ assert ff_snk_in.data(31 downto 0) = v_hdr_words_arr(c_nof_eth_beats - 1)(31 downto 0)
+ report "RX: Wrong " & v_hdr_string & " response half word"
+ severity ERROR;
if c_data_type = c_tb_tech_mac_10g_data_type_arp then
@@ -365,7 +379,9 @@ package body tb_tech_mac_10g_pkg is
for I in c_nof_eth_beats to c_nof_hdr_beats - 1 loop
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
- assert ff_snk_in.data(63 downto 0) = v_hdr_words_arr(I) report "RX: Wrong " & v_hdr_string & " response word" severity ERROR;
+ assert ff_snk_in.data(63 downto 0) = v_hdr_words_arr(I)
+ report "RX: Wrong " & v_hdr_string & " response word"
+ severity ERROR;
end loop;
-- . continue to eop
while ff_snk_in.eop /= '1' loop
@@ -382,7 +398,9 @@ package body tb_tech_mac_10g_pkg is
for I in c_nof_eth_beats to c_nof_hdr_beats - 1 loop
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
if I /= c_network_total_header_64b_ip_header_checksum_wi then -- do not verify tx ip header checksum
- assert ff_snk_in.data(63 downto 0) = v_hdr_words_arr(I) report "RX: Wrong " & v_hdr_string & " response word" severity ERROR;
+ assert ff_snk_in.data(63 downto 0) = v_hdr_words_arr(I)
+ report "RX: Wrong " & v_hdr_string & " response word"
+ severity ERROR;
end if;
end loop;
@@ -404,14 +422,18 @@ package body tb_tech_mac_10g_pkg is
-- data : X"00000000_00000001", X"00000000_00000002", X"00000000_00000003", etc
v_num := v_num + 1;
if unsigned(v_prev_data) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
when others =>
-- data : X"01020304_05060708", X"090A0B0C_0D0E0F10", X"11121314_15161718", etc
for J in c_tech_mac_10g_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
if unsigned(v_prev_data((J + 1) * c_tech_mac_10g_symbol_w - 1 downto J * c_tech_mac_10g_symbol_w)) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data((J + 1) * c_tech_mac_10g_symbol_w - 1 downto J * c_tech_mac_10g_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tech_mac_10g_symbol_w - 1 downto J * c_tech_mac_10g_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
v_sym := v_sym + J;
exit;
end if;
@@ -438,14 +460,18 @@ package body tb_tech_mac_10g_pkg is
v_num((J + 1) * c_tech_mac_10g_symbol_w - 1 downto J * c_tech_mac_10g_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
if unsigned(v_prev_data) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
when others =>
-- data : X"01020304_05060708", X"090A0B0C_0D0E0F10", X"11121314_15161718", etc
for J in c_tech_mac_10g_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
if unsigned(v_prev_data((J + 1) * c_tech_mac_10g_symbol_w - 1 downto J * c_tech_mac_10g_symbol_w)) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data((J + 1) * c_tech_mac_10g_symbol_w - 1 downto J * c_tech_mac_10g_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tech_mac_10g_symbol_w - 1 downto J * c_tech_mac_10g_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
v_sym := v_sym + J;
exit;
end if;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
index 7563515c0a..a727766d13 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
@@ -57,9 +57,11 @@ begin
tb_end <= '1';
proc_common_wait_some_cycles(clk, 1);
if g_tb_end = false then
- report "Tb simulation finished." severity NOTE;
+ report "Tb simulation finished."
+ severity NOTE;
else
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
index edddc9a01f..a93b5f6f5e 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
@@ -71,14 +71,18 @@ begin
if g_no_padding = false and g_pkt_length_arr(vI) < 64 - 14 - 20 - 8 - 4 then -- = minimum frame 64 - ETH 14 - IP 20 - UDP 8 - CRC 4
-- frame shorter than 64 get padded by MAC so empty after stripping the Rx CRC is fixed 4, which becomes 6 due to pre header padding for UDP word align
if TO_UINT(rx_sosi_reg.empty) /= 6 then
- report "RX at eop: Wrong padded empty" severity ERROR;
+ report "RX at eop: Wrong padded empty"
+ severity ERROR;
end if;
else
if rx_sosi_reg.empty /= expected_sosi_arr(vI).empty then
- report "RX at eop: Wrong empty" severity ERROR;
+ report "RX at eop: Wrong empty"
+ severity ERROR;
else
vLow := TO_UINT(rx_sosi_reg.empty) * 8;
- assert rx_sosi_reg.data(63 downto vLow) = expected_sosi_arr(vI).data(63 downto vLow) report "RX at eop: Wrong data" severity ERROR;
+ assert rx_sosi_reg.data(63 downto vLow) = expected_sosi_arr(vI).data(63 downto vLow)
+ report "RX at eop: Wrong data"
+ severity ERROR;
end if;
end if;
vI := vI + 1;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
index 369325f476..baf3e94c78 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
@@ -59,13 +59,17 @@ begin
-- Verify that all transmitted packets have been received
if i_tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif i_tx_pkt_cnt /= g_nof_pkt then
- report "Not all packets were transmitted." severity ERROR;
+ report "Not all packets were transmitted."
+ severity ERROR;
elsif i_rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif i_tx_pkt_cnt /= i_rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
wait;
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index 03bce9fe76..ed21fc2983 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -122,7 +122,8 @@ package body technology_pkg is
when 6250 => r := "6250 Mbps";
when others =>
r := "ERROR: tech_nat_to_mbps_str UNSUPPORTED DATA RATE"; -- This too long string will cause an error in Quartus synthesis
- report r severity FAILURE; -- Severity Failure will stop the Modelsim simulation
+ report r
+ severity FAILURE; -- Severity Failure will stop the Modelsim simulation
end case;
return r;
end;
diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd
index 3b3671516d..777df6b10b 100644
--- a/libraries/technology/transceiver/sim_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd
@@ -134,7 +134,9 @@ begin
wait until rising_edge(tr_clk);
v_period := NOW - v_period;
wait until rising_edge(tr_clk);
- assert v_period >= c_tr_clk_period report "Actual tr_clk period = " & time_to_str(v_period) & " should be >= c_tr_clk_period = " & time_to_str(c_tr_clk_period) severity ERROR;
+ assert v_period >= c_tr_clk_period
+ report "Actual tr_clk period = " & time_to_str(v_period) & " should be >= c_tr_clk_period = " & time_to_str(c_tr_clk_period)
+ severity ERROR;
-- use signal to show tr_clk period in Wave window
tr_clk_period <= v_period;
diff --git a/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd b/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
index 1b3a3e3b58..c5138684e1 100644
--- a/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
+++ b/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
@@ -73,7 +73,9 @@ begin
-- Stop the simulation
tb_end <= '1';
- assert false report "Simulation finished." severity NOTE;
+ assert false
+ report "Simulation finished."
+ severity NOTE;
wait;
end process;
diff --git a/libraries/technology/tse/tb_tb_tech_tse.vhd b/libraries/technology/tse/tb_tb_tech_tse.vhd
index ad1cbfd3b2..7a34c5f7b0 100644
--- a/libraries/technology/tse/tb_tb_tech_tse.vhd
+++ b/libraries/technology/tse/tb_tb_tech_tse.vhd
@@ -62,7 +62,8 @@ begin
begin
wait until tb_end = '1';
wait for 1 ns;
- report "Multi tb simulation finished." severity FAILURE;
+ report "Multi tb simulation finished."
+ severity FAILURE;
wait;
end process;
end tb;
diff --git a/libraries/technology/tse/tb_tech_tse.vhd b/libraries/technology/tse/tb_tech_tse.vhd
index 4df0ac76f0..539e4ee070 100644
--- a/libraries/technology/tse/tb_tech_tse.vhd
+++ b/libraries/technology/tse/tb_tech_tse.vhd
@@ -269,19 +269,24 @@ begin
wait until rx_end = '1';
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
tb_end <= '1';
wait for 1 ns;
if g_tb_end = false then
- report "Tb simulation finished." severity NOTE;
+ report "Tb simulation finished."
+ severity NOTE;
else
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
diff --git a/libraries/technology/tse/tb_tech_tse_pkg.vhd b/libraries/technology/tse/tb_tech_tse_pkg.vhd
index 8b6cefa92a..68ff9cd953 100644
--- a/libraries/technology/tse/tb_tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tb_tech_tse_pkg.vhd
@@ -389,21 +389,35 @@ package body tb_tech_tse_pkg is
-- Verify ETH Header
-- . wait for sop
proc_dp_stream_valid_sop(ff_clk, ff_snk_in.valid, ff_snk_in.sop);
- assert ff_snk_in.data(31 downto 16) = X"0000" report "RX: Wrong ETH alignment half word not zero" severity ERROR;
- assert ff_snk_in.data(15 downto 0) = c_eth_header.dst_mac(47 downto 32) report "RX: Wrong ETH dst_mac_addr(47 downto 32)" severity ERROR;
+ assert ff_snk_in.data(31 downto 16) = X"0000"
+ report "RX: Wrong ETH alignment half word not zero"
+ severity ERROR;
+ assert ff_snk_in.data(15 downto 0) = c_eth_header.dst_mac(47 downto 32)
+ report "RX: Wrong ETH dst_mac_addr(47 downto 32)"
+ severity ERROR;
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
- assert ff_snk_in.data(31 downto 0) = c_eth_header.dst_mac(31 downto 0) report "RX: Wrong ETH dst_mac_addr(31 downto 0)" severity ERROR;
+ assert ff_snk_in.data(31 downto 0) = c_eth_header.dst_mac(31 downto 0)
+ report "RX: Wrong ETH dst_mac_addr(31 downto 0)"
+ severity ERROR;
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
- assert ff_snk_in.data(31 downto 0) = c_eth_header.src_mac(47 downto 16) report "RX: Wrong ETH src_mac_addr(47 downto 16)" severity ERROR;
+ assert ff_snk_in.data(31 downto 0) = c_eth_header.src_mac(47 downto 16)
+ report "RX: Wrong ETH src_mac_addr(47 downto 16)"
+ severity ERROR;
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
- assert ff_snk_in.data(31 downto 16) = c_eth_header.src_mac(15 downto 0) report "RX: Wrong ETH src_mac_addr(15 downto 0)" severity ERROR;
- assert ff_snk_in.data(15 downto 0) = c_eth_header.eth_type report "RX: Wrong ETH ethertype" severity ERROR;
+ assert ff_snk_in.data(31 downto 16) = c_eth_header.src_mac(15 downto 0)
+ report "RX: Wrong ETH src_mac_addr(15 downto 0)"
+ severity ERROR;
+ assert ff_snk_in.data(15 downto 0) = c_eth_header.eth_type
+ report "RX: Wrong ETH ethertype"
+ severity ERROR;
----------------------------------------------------------------------------
-- Verify ETH higher layer headers
if c_data_type = c_tb_tech_tse_data_type_arp then
for I in c_nof_eth_beats to c_nof_hdr_beats - 1 loop
proc_dp_stream_valid(ff_clk, ff_snk_in.valid);
- assert ff_snk_in.data(31 downto 0) = c_arp_words_arr(I) report "RX: Wrong ARP response word" severity ERROR;
+ assert ff_snk_in.data(31 downto 0) = c_arp_words_arr(I)
+ report "RX: Wrong ARP response word"
+ severity ERROR;
end loop;
-- . continue to eop
while ff_snk_in.eop /= '1' loop
@@ -436,14 +450,18 @@ package body tb_tech_tse_pkg is
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
if unsigned(v_prev_data) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data) = v_num report "RX: Wrong data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong data word"
+ severity ERROR;
end if;
when others =>
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tech_tse_symbols_per_beat - 1 downto 0 loop
v_sym := v_sym + 1;
if unsigned(v_prev_data((J + 1) * c_tech_tse_symbol_w - 1 downto J * c_tech_tse_symbol_w)) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data((J + 1) * c_tech_tse_symbol_w - 1 downto J * c_tech_tse_symbol_w)) = v_sym report "RX: Wrong data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tech_tse_symbol_w - 1 downto J * c_tech_tse_symbol_w)) = v_sym
+ report "RX: Wrong data symbol"
+ severity ERROR;
end if;
end loop;
end case;
@@ -468,14 +486,18 @@ package body tb_tech_tse_pkg is
v_num((J + 1) * c_tech_tse_symbol_w - 1 downto J * c_tech_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
end loop;
if unsigned(v_prev_data) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
+ assert unsigned(v_prev_data) = v_num
+ report "RX: Wrong empty data word"
+ severity ERROR;
end if;
when others =>
-- data : X"01020304", X"05060708", X"090A0B0C", etc
for J in c_tech_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
v_sym := v_sym + 1;
if unsigned(v_prev_data((J + 1) * c_tech_tse_symbol_w - 1 downto J * c_tech_tse_symbol_w)) /= 0 then -- do not verify zero padding
- assert unsigned(v_prev_data((J + 1) * c_tech_tse_symbol_w - 1 downto J * c_tech_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
+ assert unsigned(v_prev_data((J + 1) * c_tech_tse_symbol_w - 1 downto J * c_tech_tse_symbol_w)) = v_sym
+ report "RX: Wrong empty data symbol"
+ severity ERROR;
end if;
end loop;
end case;
diff --git a/libraries/technology/tse/tb_tech_tse_with_setup.vhd b/libraries/technology/tse/tb_tech_tse_with_setup.vhd
index 701cbd3f55..50d5b2e8de 100644
--- a/libraries/technology/tse/tb_tech_tse_with_setup.vhd
+++ b/libraries/technology/tse/tb_tech_tse_with_setup.vhd
@@ -173,7 +173,9 @@ begin
when c_tech_arria10_e2sg => v_version := 16#1304#; -- unb2c
when others => v_version := 0; -- default
end case;
- assert unsigned(mm_rddata(c_16 - 1 downto 0)) = v_version report "Wrong external MM read access result." severity ERROR;
+ assert unsigned(mm_rddata(c_16 - 1 downto 0)) = v_version
+ report "Wrong external MM read access result."
+ severity ERROR;
-- Wait for link synchronisation
proc_common_wait_until_high(mm_clk, tse_led.link);
@@ -287,19 +289,24 @@ begin
wait until rx_end = '1';
-- Verify that all transmitted packets have been received
if tx_pkt_cnt = 0 then
- report "No packets were transmitted." severity ERROR;
+ report "No packets were transmitted."
+ severity ERROR;
elsif rx_pkt_cnt = 0 then
- report "No packets were received." severity ERROR;
+ report "No packets were received."
+ severity ERROR;
elsif tx_pkt_cnt /= rx_pkt_cnt then
- report "Not all transmitted packets were received." severity ERROR;
+ report "Not all transmitted packets were received."
+ severity ERROR;
end if;
tb_end <= '1';
wait for 1 ns;
if g_tb_end = false then
- report "Tb simulation finished." severity NOTE;
+ report "Tb simulation finished."
+ severity NOTE;
else
- report "Tb simulation finished." severity FAILURE;
+ report "Tb simulation finished."
+ severity FAILURE;
end if;
wait;
end process;
--
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