diff --git a/tools/oneclick/doc/fpga_firmware_overview.txt b/tools/oneclick/doc/fpga_firmware_overview.txt
index 6000475cfdb06cba3f22600b9a369f187c145da1..28ff16c764cbaf79ffaa17903b080d766eece3c6 100755
--- a/tools/oneclick/doc/fpga_firmware_overview.txt
+++ b/tools/oneclick/doc/fpga_firmware_overview.txt
@@ -23,6 +23,23 @@ Purpose:
   - Clean coding
   - Reuse through HDL libraries
   - Standard interfaces: MM & ST, support Avalon, AXI using VHDL records mosi/miso, sosi/siso
+  - Distinguish beteen state registers and pipeline registers. The state registers keep the state of the
+    function and the function itself is programmed in combinatorial logic. In this way the pipelining that
+    is needed to achieve timing closure can be added independent of the function.
+  - Components need pipelining to achieve timing closure. This pipelining causes a latency in the data
+    stream. This latency is typically no problem, because it only delays the output. If components need
+    flow control then the stream has a siso backpressure signal that must have a certain timing relation
+    to the sosi data signal. This timing relation is the ready latency (RL) and the RL can be >= 0. For 
+    RL = 0 the ready signal acts as a data acknowledge and for RL > 0 the ready signal acts as a data
+    request signal. Adding pipelining to the sosi data increases the RL.
+  - The RL is explained in the Avalon specification. An example of RL = 0 are so called look ahead (Altera)
+    or first word fall through (Xilinx) FIFOs. In our UniBoard applications we use RL = 1. For most parts
+    of the design we try to not use flow control. I think that the Axi stream use RL = 0.
+  - The function operates with ready latency (RL) = 0, if it is combinatorial. If the stream has no flow then
+    the pipeline is achieved as an output register stage. If the stream does need flow control, then this
+    output register stage increases the RL by 1. To restore the RL to 0 a dp_latency_adapter.vhd is needed.
+    This latency adapter also registes the ready, so it provides pipelining for both the output stream data
+    as well as the output stream ready flow control. For example: dp_block_resize.vhd, dp_counter.vhd.
   - Board minimal design that provides control access to the FPGA board and the board control functions
   - Board test design that contain the minimal design plus interfaces to use the board IO (transceivers, DDR)
   - Build FPGA appliciation design upon a board minimal design and the relevant IO from the board test design
@@ -30,6 +47,14 @@ Purpose:
     . base: common, dp, mm, diag, reorder, uth
     . dsp: wpfb, bf, correlator, st
     . io: eth, io_ddr, i2c
+  - Design for scaleability with generics that can be scaled over the logical range, e.g. >= 0, even if the
+    application only requires a certain fixed value. The reasons are:
+    . During development the application typically starts small (e.g. a BF with 4 inputs) while the final
+      application is much larger (e.g. a BF with 64 input). With generics both can be supported through a
+      parameter change.
+    . For simulation it is often necessary to reduce the size of the design to be able to simulate it in a
+      reasonable time. By scaling it down via generics the design preserves its structure but becomes much
+      smaller. 
 
 3) VHDL testing:
   - detailed unit tests per HDL library using entity IO
@@ -54,9 +79,12 @@ Purpose:
     . we need proper data capture machines, to validata 10G, 40 GbE data output (e.g. using wireshark and some Python code)
 
 4) RadioHDL
-  - RadioHDL is our umbrella name for set of tool scripts that we use for firmware development, focus on implementation.
+  - RadioHDL is our umbrella name for set of tool scripts that we use for firmware development, focus on implementation. RadioHDL makes
+    it easier for developers to organize different versions and combinations of their firmware, tools and boards. RadioHDL is a platform?
   - The name RadioHDL covers HDL code for RadioAstronomy as a link to what we do at Astron. However by using only the word Radio we keep
-    the name a bit more general, because in fact the RadioHDL tool scripts can be used for any (FPGA) HDL development.
+    the name a bit more general, because in fact the RadioHDL tool scripts can be used for any (FPGA) HDL development. Outside Astron
+    the word RadioHDL can be advertised as an HDL radio station that like to listen to, so a feel good name with a strong link to HDL but
+    otherwise not explicitely telling what it is.
   - Automate implementation flow (source --> config file --> tool script --> product, a product can be the source of a next product)
   - Organize code in libraries using hdllib.cfg
   - Manage tool versions using hdltool_<toolset name>.cfg
@@ -64,7 +92,7 @@ Purpose:
   - ARGS (Automatic Register Generation System using MM bus and MM register config files in yaml)
   - Create FPGA info (used to be called system info) address map stored in FPGA to allow dynamic definition of address maps. The definition
     of the MM register fields is kept in files because it typically remains fixed.
-  - Easily enroll the environment on a new PC and introduce a new employee (to be done)
+  - Easily enroll the environment on a new PC and introduce a new employee (to be done --> OpenCores, Ruud Overeem)
   
 5) Oneclick
   - OneClick is our umbrella name for new ideas and design methods, focus on firmware specifcation and design. New tools that are