diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 1a4a516dfca2e8a38163c37ee9085a7b6d704bef..cd42192996de6c6cc89c81caed63e498d2ce169c 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -157,8 +157,7 @@ ENTITY io_ddr IS
     g_sim_model               : BOOLEAN := FALSE;
     g_technology              : NATURAL := c_tech_select_default;
     g_tech_ddr                : t_c_tech_ddr;
-    g_cross_domain_dvr_ctlr   : BOOLEAN := TRUE;
-    g_cross_domain_delay_len  : NATURAL := c_meta_delay_len;
+    g_cross_domain_dvr_ctlr   : BOOLEAN := TRUE;    -- use TRUE when MM clock is used for the access control, use FALSE when ctlr_clk_in=ctlr_clk_out is used to avoid extra latency
     g_wr_data_w               : NATURAL := 32;  
     g_wr_fifo_depth           : NATURAL := 256;     -- >=16                             , defined at DDR side of the FIFO, default 256 because 32b*256 fits in 1 M9K
     g_rd_fifo_depth           : NATURAL := 256;     -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO, default 256 because 32b*256 fits in 1 M9K 
@@ -280,7 +279,7 @@ BEGIN
   u_io_ddr_cross_domain : ENTITY work.io_ddr_cross_domain
   GENERIC MAP (
     g_cross_domain => g_cross_domain_dvr_ctlr,
-    g_delay_len    => g_cross_domain_delay_len
+    g_delay_len    => c_meta_delay_len
   )
   PORT MAP(
     -- Driver clock domain
@@ -482,7 +481,7 @@ BEGIN
                    RESIZE_UVEC(ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok & 
                                ctlr_rst_out_i    & ctlr_wr_flush_en     & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done, c_mem_reg_dat_w);   
   
-  u_reg_map : ENTITY common_lib. common_reg_r_w_dc
+  u_reg_map : ENTITY common_lib.common_reg_r_w_dc
   GENERIC MAP (
     g_cross_clock_domain => TRUE,             
     g_in_new_latency     => 0,