From a83dd0c5427987ee9284fb62f13c5b01444650f4 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 10 Dec 2014 13:12:19 +0000
Subject: [PATCH] Use g_no_dut instead of c_loopback_st.
---
.../technology/eth_10g/tb_tb_tech_eth_10g.vhd | 14 +-
.../technology/eth_10g/tb_tech_eth_10g.vhd | 160 +++++++++---------
2 files changed, 89 insertions(+), 85 deletions(-)
diff --git a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
index 74fa70275e..d01d180131 100644
--- a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
@@ -43,23 +43,25 @@ ARCHITECTURE tb OF tb_tb_tech_eth_10g IS
CONSTANT c_156 : TIME := 6.4 ns;
CONSTANT c_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
- CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'1');
- SIGNAL tb_end_vec : STD_LOGIC_VECTOR(1 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
BEGIN
-- g_technology : NATURAL := c_tech_select_default;
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
--- g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+-- g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
+-- g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
-- g_ref_clk_644_period : TIME := tech_pll_clk_644_period; -- for 10GBASE-R
-- g_ref_clk_156_period : TIME := 6.4 ns; -- for XAUI
-- g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
-- g_verify_link_recovery : BOOLEAN := TRUE;
-- g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
--- g_use_serial_rx_in : BOOLEAN := FALSE
+-- g_use_serial_rx_in : BOOLEAN := FALSE -- default FALSE when this tb is ran standalone, else use TRUE to simulate a link between two instances of this tb
- u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(0));
- u_sim_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, 1, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(1));
+ u_no_dut : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, TRUE, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(0));
+ u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(1));
+ u_sim_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 1, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(2));
p_tb_end : PROCESS
BEGIN
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
index 3350ce6b33..f57363aeda 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
@@ -48,13 +48,14 @@ ENTITY tb_tech_eth_10g IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
+ g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
+ g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
g_ref_clk_644_period : TIME := tech_pll_clk_644_period; -- for 10GBASE-R
g_ref_clk_156_period : TIME := 6.4 ns; -- for XAUI
g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
g_verify_link_recovery : BOOLEAN := TRUE;
g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
- g_use_serial_rx_in : BOOLEAN := FALSE
+ g_use_serial_rx_in : BOOLEAN := FALSE -- default FALSE when this tb is ran standalone, else use TRUE to simulate a link between two instances of this tb
);
PORT (
tb_end : OUT STD_LOGIC;
@@ -70,12 +71,14 @@ END tb_tech_eth_10g;
ARCHITECTURE tb OF tb_tech_eth_10g IS
- CONSTANT phy_delay : TIME := 0 ns;
+ CONSTANT c_sim : BOOLEAN := TRUE; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ CONSTANT c_nof_channels : NATURAL := 1; -- fixed in this tb
+ CONSTANT cal_clk_period : TIME := 25 ns; -- 40 MHz
+
+ CONSTANT phy_delay : TIME := 0 ns;
CONSTANT c_phy_loopback : BOOLEAN := NOT g_use_serial_rx_in;
- CONSTANT c_st_loopback : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
- CONSTANT c_rl : NATURAL := 1;
- CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+
CONSTANT c_pkt_length_arr1 : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000; -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
-- jumbo frame is 9018-46 = 8972
CONSTANT c_pkt_length_arr2 : t_nat_natural_arr := array_init(46, 10, 139) & 1472;
@@ -99,6 +102,7 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
-- Clocks and reset
SIGNAL rx_end : STD_LOGIC := '0';
+ SIGNAL cal_clk : STD_LOGIC := '1'; -- calibration clock
SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock
SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
@@ -125,26 +129,22 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
-- 10G MAC control interface
SIGNAL mm_init : STD_LOGIC := '1';
- SIGNAL mm_mosi : t_mem_mosi;
- SIGNAL mm_mosi_wrdata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit;
- SIGNAL mm_miso : t_mem_miso;
- SIGNAL mm_miso_rdval : STD_LOGIC;
- SIGNAL mm_miso_rddata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit;
+ SIGNAL mac_mosi : t_mem_mosi;
+ SIGNAL mac_mosi_wrdata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit;
+ SIGNAL mac_miso : t_mem_miso;
+ SIGNAL mac_miso_rdval : STD_LOGIC;
+ SIGNAL mac_miso_rddata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit;
-- 10G MAC transmit interface
-- . The tb is the ST source
SIGNAL tx_siso : t_dp_siso;
- SIGNAL tx_siso_arr : t_dp_siso_arr(0 DOWNTO 0);
SIGNAL tx_sosi : t_dp_sosi;
- SIGNAL tx_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
SIGNAL tx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
-- 10G MAC receive interface
-- . The tb is the ST sink
SIGNAL rx_siso : t_dp_siso;
- SIGNAL rx_siso_arr : t_dp_siso_arr(0 DOWNTO 0);
SIGNAL rx_sosi : t_dp_sosi;
- SIGNAL rx_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
-- PHY serial IO
@@ -166,10 +166,12 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
BEGIN
+ cal_clk <= NOT cal_clk AFTER cal_clk_period/2; -- Calibration clock
+
-- debug signals to ease monitoring in wave window
- mm_mosi_wrdata <= mm_mosi.wrdata(c_word_w-1 DOWNTO 0);
- mm_miso_rddata <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
- mm_miso_rdval <= '1' WHEN mm_mosi.rd='1' AND mm_miso.waitrequest='0' ELSE '0'; -- c_rd_latency = 1
+ mac_mosi_wrdata <= mac_mosi.wrdata(c_word_w-1 DOWNTO 0);
+ mac_miso_rddata <= mac_miso.rddata(c_word_w-1 DOWNTO 0);
+ mac_miso_rdval <= '1' WHEN mac_mosi.rd='1' AND mac_miso.waitrequest='0' ELSE '0'; -- c_rd_latency = 1
tx_sosi_data <= tx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0);
rx_sosi_data <= rx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0);
@@ -187,8 +189,8 @@ BEGIN
mm_clk => mm_clk,
mm_rst => mm_rst,
mm_init => mm_init,
- mm_mosi => mm_mosi,
- mm_miso => mm_miso
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso
);
-- Packet transmitter
@@ -202,26 +204,19 @@ BEGIN
PORT MAP (
mm_init => mm_init,
total_header => total_header,
- clk_156 => tb_tx_clk,
+ tx_clk => tb_tx_clk,
tx_siso => tx_siso,
tx_sosi => tx_sosi,
link_fault => link_fault,
tx_end => rx_end
);
- -- Rewire DP to DP array type.
- tx_sosi_arr(0) <= tx_sosi;
- tx_siso <= tx_siso_arr(0);
-
- rx_siso_arr(0) <= rx_siso;
- rx_sosi <= rx_sosi_arr(0);
-
-- Generate reference clocks
gen_ref_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
tr_ref_clk_644 <= 'X';
tr_ref_clk_312 <= 'X';
tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_ref_clk_156_period/2;
- tr_ref_rst_156 <= '0' AFTER g_ref_clk_156_period*5;
+ tr_ref_rst_156 <= '1', '0' AFTER g_ref_clk_156_period*5;
END GENERATE;
gen_ref_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
@@ -244,7 +239,7 @@ BEGIN
u_tech_eth_10g_clocks : ENTITY work.tech_eth_10g_clocks
GENERIC MAP (
g_technology => g_technology,
- g_nof_channels => 1
+ g_nof_channels => c_nof_channels
)
PORT MAP (
-- Input clocks
@@ -274,79 +269,86 @@ BEGIN
eth_rx_rst_arr(0) => tb_rx_rst
);
- no_dut : IF c_st_loopback=TRUE GENERATE
+ no_dut : IF g_no_dut=TRUE GENERATE
+ tx_rst_arr_out <= (OTHERS=>tr_ref_rst_156);
+ rx_clk_arr_out <= (OTHERS=>tr_ref_clk_156);
+ rx_rst_arr_out <= (OTHERS=>tr_ref_rst_156);
+
rx_sosi <= tx_sosi;
tx_siso <= rx_siso;
END GENERATE;
- gen_dut : IF c_st_loopback=FALSE GENERATE
+ gen_dut : IF g_no_dut=FALSE GENERATE
dut : ENTITY work.tech_eth_10g
GENERIC MAP (
g_technology => g_technology,
- g_sim => TRUE,
+ g_sim => c_sim,
g_sim_level => g_sim_level,
- g_nof_channels => 1,
+ g_nof_channels => c_nof_channels,
g_link_status_check => g_link_status_check,
g_pre_header_padding => TRUE
)
PORT MAP (
-- Transceiver PLL reference clock
- tr_ref_clk_644 => tb_ref_clk_644,
- tr_ref_clk_312 => tb_ref_clk_312,
- tr_ref_clk_156 => tb_ref_clk_156,
- tr_ref_rst_156 => tb_ref_rst_156,
+ tr_ref_clk_644 => tb_ref_clk_644,
+ tr_ref_clk_312 => tb_ref_clk_312,
+ tr_ref_clk_156 => tb_ref_clk_156,
+ tr_ref_rst_156 => tb_ref_rst_156,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_clk, -- for XAUI
-- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mac_mosi => mm_mosi, -- CSR = control status register
- mac_miso => mm_miso,
+ mac_mosi => mac_mosi, -- CSR = control status register
+ mac_miso => mac_miso,
-- XAUI clocks
- tx_clk_arr_in(0) => tb_tx_clk, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
- tx_rst_arr_out => tx_rst_arr_out,
- rx_clk_arr_out => rx_clk_arr_out,
- rx_clk_arr_in(0) => tb_rx_clk, -- externally connect to rx_clk_arr_out to avoid clock delta-delay
- rx_rst_arr_out => rx_rst_arr_out,
+ tx_clk_arr_in(0) => tb_tx_clk, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_rst_arr_out => tx_rst_arr_out,
+ rx_clk_arr_out => rx_clk_arr_out,
+ rx_clk_arr_in(0) => tb_rx_clk, -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_rst_arr_out => rx_rst_arr_out,
-- ST
- tx_snk_in_arr => tx_sosi_arr, -- 64 bit data @ 156 tb_tx_clk
- tx_snk_out_arr => tx_siso_arr,
+ tx_snk_in_arr(0) => tx_sosi, -- 64 bit data @ 156 tb_tx_clk
+ tx_snk_out_arr(0) => tx_siso,
- rx_src_out_arr => rx_sosi_arr, -- 64 bit data @ 156 tb_rx_clk
- rx_src_in_arr => rx_siso_arr,
+ rx_src_out_arr(0) => rx_sosi, -- 64 bit data @ 156 tb_rx_clk
+ rx_src_in_arr(0) => rx_siso,
-- PHY serial IO
-- . 10GBASE-R (single lane)
- serial_tx_arr => serial_tx_arr,
- serial_rx_arr => serial_rx_arr,
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr,
-- . XAUI (four lanes)
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr
);
END GENERATE;
u_link_connect : ENTITY tech_mac_10g_lib.tb_tech_mac_10g_link_connect
GENERIC MAP (
- g_loopback => c_phy_loopback, -- default TRUE for loopback tx to rx, else use FALSE to connect tx-tx, rx-rx between two tb devices
+ g_loopback => c_phy_loopback, -- default TRUE for loopback tx to rx, else use FALSE to connect tx-tx, rx-rx between two tb devices
g_link_delay => phy_delay
)
PORT MAP (
- link_fault => link_fault, -- when '1' then forces rx_serial_arr(0)='0'
+ link_fault => link_fault, -- when '1' then forces rx_serial_arr(0)='0'
-- 10GBASE-R serial layer connect
- serial_tx_arr => serial_tx_arr,
- serial_rx_arr => serial_rx_arr, -- connects to delayed tx_serial_arr(0) when g_loopback=TRUE else to rx_serial_in
- serial_tx_out => serial_tx_out, -- connects to delayed tx_serial_arr(0)
- serial_rx_in => serial_rx_in, -- used when g_loopback=FALSE
+ serial_tx => serial_tx_arr(0),
+ serial_rx => serial_rx_arr(0), -- connects to delayed tx_serial_arr(0) when g_loopback=TRUE else to rx_serial_in
+ serial_tx_out => serial_tx_out, -- connects to delayed tx_serial_arr(0)
+ serial_rx_in => serial_rx_in, -- used when g_loopback=FALSE
-- XAUI serial layer connect
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr, -- connects to delayed xaui_tx_arr(0) when g_loopback=TRUE else to xaui_rx_in
- xaui_tx_out => xaui_tx_out, -- connects to delayed xaui_tx_arr(0)
- xaui_rx_in => xaui_rx_in -- used when g_loopback=FALSE
+ xaui_tx => xaui_tx_arr(0),
+ xaui_rx => xaui_rx_arr(0), -- connects to delayed xaui_tx_arr(0) when g_loopback=TRUE else to xaui_rx_in
+ xaui_tx_out => xaui_tx_out, -- connects to delayed xaui_tx_arr(0)
+ xaui_rx_in => xaui_rx_in -- used when g_loopback=FALSE
);
-- Packet receiver
@@ -357,7 +359,7 @@ BEGIN
PORT MAP (
mm_init => mm_init,
total_header => total_header,
- clk_156 => tb_rx_clk,
+ rx_clk => tb_rx_clk,
rx_sosi => rx_sosi,
rx_siso => rx_siso,
rx_toggle => rx_toggle
@@ -366,28 +368,28 @@ BEGIN
-- Verification
u_verify_rx_at_eop : ENTITY tech_mac_10g_lib.tb_tech_mac_10_verify_rx_at_eop
GENERIC MAP (
- g_no_padding => FALSE,
+ g_no_padding => g_no_dut,
g_pkt_length_arr => c_pkt_length_arr
)
PORT MAP (
- tx_clk_156 => tb_tx_clk,
- tx_sosi => tx_sosi,
- rx_clk_156 => tb_rx_clk,
- rx_sosi => rx_sosi
+ tx_clk => tb_tx_clk,
+ tx_sosi => tx_sosi,
+ rx_clk => tb_rx_clk,
+ rx_sosi => rx_sosi
);
u_verify_rx_pkt_cnt : ENTITY tech_mac_10g_lib.tb_tech_mac_10g_verify_rx_pkt_cnt
GENERIC MAP (
- g_nof_pkt => c_nof_pkt
+ g_nof_pkt => c_nof_pkt
)
PORT MAP (
- tx_clk_156 => tb_tx_clk,
- tx_sosi => tx_sosi,
- rx_clk_156 => tb_rx_clk,
- rx_sosi => rx_sosi,
- tx_pkt_cnt => tx_pkt_cnt,
- rx_pkt_cnt => rx_pkt_cnt,
- rx_end => rx_end
+ tx_clk => tb_tx_clk,
+ tx_sosi => tx_sosi,
+ rx_clk => tb_rx_clk,
+ rx_sosi => rx_sosi,
+ tx_pkt_cnt => tx_pkt_cnt,
+ rx_pkt_cnt => rx_pkt_cnt,
+ rx_end => rx_end
);
p_tb_end : PROCESS
--
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