diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/doc/README b/applications/lofar2/designs/lofar2_unb2b_adc/doc/README
index 35b46c0a8b12d15e66e308319a5ffd0bdacd5997..edb74b356a5ef6c37d62772502c6d3c66ba7bfc5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/doc/README
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/doc/README
@@ -9,7 +9,7 @@ Quick steps to compile
    generate_ip_libs unb2b
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 -> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
index da85c19f6523141cbbe5eb02ad1bd1dc0e4f2fdb..9244ccb60caff6178449688b9e70af4d40d6908f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
index d2d66a2cb73c41d96ae3de0aef988ec37c9867fc..ef4007969863434069392cdc9ebdf6a31759f18a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
@@ -25,7 +25,7 @@ quartus_copy_files =
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_adc.sdc
@@ -36,54 +36,54 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_6ch_200MHz/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_6ch_200MHz/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_3.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_4.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_5.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_6.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_7.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_8.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_3.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_4.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_5.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_6.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_7.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_8.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
index 2edaaa62557d3216749a6fc2459b25a6d53c6c5b..fc8bd8e67ff89523e3aaf9f0a32459f8a179c11d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -29,7 +29,7 @@ quartus_copy_files =
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_adc.sdc
@@ -40,43 +40,43 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_full/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_full/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
index 9779c2a24803fa214c1f32c586f7eed74db4a6c2..29ba8f06856d4ac77809bd9f07f5f236c98e8574 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
@@ -28,13 +28,13 @@ quartus_copy_files =
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_pre_files =
     ../../quartus/lofar2_unb2b_adc.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2b_adc_pins.tcl
@@ -42,31 +42,31 @@ quartus_tcl_files =
 quartus_vhdl_files =
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_one_node/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_one_node/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index c8d5c25862501cf4864df9487537e0ae659b0d53..c0e0c536962548750ff278b97d2ff4b25e28a98a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -27,7 +27,7 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-  -- $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
+  -- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
   -----------------------------------------------------------------------------
 
     component qsys_lofar2_unb2b_adc is
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
index 851a631d744084345d1228d08c4c7b09bce10c5c..d4023a141d746d916951809e7cdc8dd0fafc3461 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -19,9 +19,9 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
 # unb2b_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
 #
 #=====================
 # QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
index 2a794ca3f2c2a469d9704f93add4e77116ad78c3..51d2dc58c73e41c1ec496a3eba9bdb5d90250f64 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_beamformer.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_beamformer.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -39,60 +39,60 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg
index d3bd995b59318d0e3c4e9094817e7e23b9203f16..248bb88cd7458bcb74e4feca63df06469a3a5178 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_beamformer.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_beamformer_256MHz.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -39,60 +39,60 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node_256MHz/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node_256MHz/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
 
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg
index 93d1ea62afd409353f368a40cd853112d084414e..991c0be8000070cf94101322a4371385b297c08c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg
@@ -18,8 +18,8 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../
-     $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../
+     $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
      src/data data
 
 [quartus_project_file]
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl
index da85c19f6523141cbbe5eb02ad1bd1dc0e4f2fdb..9244ccb60caff6178449688b9e70af4d40d6908f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
index 755479f56e47802b1b991541f5842c8daf91d483..b30519171a54b2ac31e23dd0fb402c0af683b83b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_filterbank.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2b_filterbank_pins.tcl
@@ -39,54 +39,54 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg
index cb30c6f69185a197ac8958b5e40d8a8a07073165..da80c20962ce0d5fd179ca3413ee574d2587d6e1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_filterbank_256MHz.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2b_filterbank_pins.tcl
@@ -39,50 +39,50 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full_256MHz/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full_256MHz/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl
index ca41236b9661ce4b9e820fd13abae9d7379e413a..e59b18c7d7dd5c57221402dab33fafca9f24fc1d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl
@@ -18,9 +18,9 @@
 # Derived from lofar2_unb2b_sdp_station_pins.tcl and unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl.
 # We cannot source unb2b_10GbE_pins.tcl as it causes synthesis errors when assignments are defined 
 # for transceiver pins that are not in the top-level design
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
 # unb2b_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
 #
 #=====================
 # QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
index 071e3cc01f4bc366b13abd17409f2577039edb8a..3f4e585e182a27faf8db6bbca618777b4e124fb1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
@@ -22,16 +22,16 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_ring.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2b_ring_pins.tcl
@@ -39,44 +39,44 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_full/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_full/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
index 5a3a7349ae3790864cc9f401557387ccbb0dfb07..dbcc6b9dde599517f4b9b4252cebdcf499ad2bee 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
@@ -22,16 +22,16 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_ring.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2b_ring_pins.tcl
@@ -39,44 +39,44 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_one/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_one/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
index fca2daaed30f712ecca86478cd0c8fbf984958fa..2369c30f370a721038c044cfba2d9b09dff6d69a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
@@ -23,7 +23,7 @@ endif
 UNB2B_BSP=lofar2_unb2b_ring_bsp
 
 # Compile directory
-BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+BUILDDIR=$(HDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
 
 
 ##############################
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
index a26be673bb31499f785593cb7defdacb6c700d78..eb495f9ccd00343e25897a5e0e4f2c6dae20db53 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
@@ -23,7 +23,7 @@
 * . Test the lofar2_unb2b_ring OpenCL application in emulator
 * Description:
 * . Run: -> make lofar2_unb2b_ring
-* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/lofar2_unb2b_ring/bin
+* . Navigate to -> cd $HDL_WORK/unb2b/OpenCL/lofar2_unb2b_ring/bin
 * . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
 * *********************************************************************** */
 #include <CL/cl_ext_intelfpga.h>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
index 736d08b812885002ead951ef1fd37bdfec638982..a134bc9977acf6e85336a29045b11945a28e2e98 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
@@ -19,9 +19,9 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
 # unb2b_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
 #
 #=====================
 # QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
index b85bc78b08035457af0eed4a6fae25007a1f4bef..950d72471a3a645c0859a472f9db36fe7140b943 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
index fc9f9b0be2067dec7d4a402040b2b2fc1bc90645..d59ee987fce4c39de513ea98c29fd2c3930d7be5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     disturb2_unb2b_sdp_station_full_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
index 689b010fb83a0f4df276dd070b6e8cc383755595..5a2689dbd5e44835cba0e120c3b23d9481bceeac 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
index c94035c6cff04e94efdb8bb8de049c37dd9465fd..58d08abe19530ec2376e4f860c46ea299f245470 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     disturb2_unb2b_sdp_station_full_wg_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 47e72aafd1e3ef6d7f7527541f4cecfea6e7f821..839400dd1f1dfbe4351b0f50ea8134bfbadece4e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -26,7 +26,7 @@ quartus_copy_files =
     ../../src/data data
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
@@ -37,91 +37,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_adc/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_adc/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
index 1951a9467db81c29743ddc496672c7fb0f0e6b41..8c991166e10986e3373925228103590dcee183ff 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
@@ -18,7 +18,7 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index cbc98f7daa43b7ab93f6e49718261afbee5402df..79b8a20c511ba74fceaf746ef6d5f17ead64e07a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -18,7 +18,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -26,18 +26,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2b_sdp_station_bf_pins.tcl
@@ -45,91 +45,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_bf/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_bf/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
index 4c0efdf4ecb475bea47c7efdb0cd104a1ffaadcd..1672b0bbb8f2606ef1b8f7de81722a0a164475ef 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index a44d4c512bf8c128077ea7ac257068af6286b2a2..dc55442463ed789d8e9411746bafa41fd473c79e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2b_sdp_station_fsub_pins.tcl
@@ -44,91 +44,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_fsub/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_fsub/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
index 1951a9467db81c29743ddc496672c7fb0f0e6b41..8c991166e10986e3373925228103590dcee183ff 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
@@ -18,7 +18,7 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
index d42226b8521136d8b3d131652da99f6ef8a14edf..7281d24cacfe157c5390f820122412baa12eb02a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2b_sdp_station_full_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
index b85bc78b08035457af0eed4a6fae25007a1f4bef..950d72471a3a645c0859a472f9db36fe7140b943 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
index 8c6453b5bb4a43f992e2397e5e589081dc3fe6fd..14859fd07351798c68b7d9c337793d8dc3ab660c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2b_sdp_station_full_wg_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
index 689b010fb83a0f4df276dd070b6e8cc383755595..5a2689dbd5e44835cba0e120c3b23d9481bceeac 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index b1e3cfd9e4be1250ed1ab05ddee127de07c10ad1..76ce67ed2052e8cb1209e069bcc274d6b45c2cc5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2b_sdp_station_xsub_one_pins.tcl
@@ -44,91 +44,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_one/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_one/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
index 1951a9467db81c29743ddc496672c7fb0f0e6b41..8c991166e10986e3373925228103590dcee183ff 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
@@ -18,7 +18,7 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
index 84b35008e1ead3ca8f609fb50ca80ea295fc43ec..aa6235c94f0a6b7c8585bc38bba5f1705b66538e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
@@ -15,7 +15,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -23,18 +23,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 # use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2b_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
@@ -42,91 +42,91 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_ring/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_ring/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
index 29347861db580a487457a4c698ccfec42f264ec0..97ab5f9c744864ebe900091b6d0e5b11f64fe9e9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
index b04f1f5de30527b0e3fc298646ff667eef02370d..bc2b72485e0ee07f630940837774e9944cecb429 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
@@ -29,10 +29,10 @@ quartus_copy_files =
     src/data data
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/lofar2_unb2c_ddrctrl_pins.tcl
@@ -40,38 +40,38 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_bsn_buf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_data_buf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_wg_wideband_arr.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_stop_in.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_io_ddr.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_bsn_buf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_data_buf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_wg_wideband_arr.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_stop_in.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_io_ddr.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl
index a1a336bbef92c7be2019871e33ede17753ca8658..9815b4c119f3974c8ea91a0d59f0c2fcebbd5b70 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl
@@ -19,7 +19,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
 
 # module I:
 set_location_assignment PIN_AP20 -to MB_I_OU.a[0]
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl
index 1ff32447a5fad88264d2db138c3d797617e339b5..6a53d3230ee3c057b06e032a83756dd241daea7c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg
index 1b5687d9fbe5e1f78983f88b5937a2de44064e0a..244663c8e8914d1db46882d2bb7823d59ab410db 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg
@@ -23,12 +23,12 @@ quartus_copy_files =
     ../../quartus .
     ../../src/data data
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_filterbank.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2c_filterbank_pins.tcl
@@ -36,50 +36,50 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg
index b9ea0422e6eaf2afca27ae8d036911be5d100bea..fe8384f70e2b669f9e9d4753f8e075d813ffd21a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg
@@ -23,12 +23,12 @@ quartus_copy_files =
     ../../quartus .
     ../../src/data data
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_filterbank_256MHz.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2c_filterbank_pins.tcl
@@ -36,50 +36,50 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full_256MHz/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full_256MHz/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl
index 603c8c45187c36227dde4d0a06bec620d857ff65..b8fa0d156c6bc6200b4179332778b577323bb3fb 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl
@@ -19,9 +19,9 @@
 # We cannot source unb2c_10GbE_pins.tcl as it causes synthesis errors when assignments are defined 
 # for transceiver pins that are not in the top-level design
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
 # unb2c_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
 #
 #=====================
 # QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg
index d5e9b8343c3ae80d9378102efc99f0e1cc6fa82a..5855e2a31fb46528e8c1561cbd1bdb4690e53f84 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg
@@ -23,16 +23,16 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_ring.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2c_ring_pins.tcl
@@ -40,42 +40,42 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_full/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_full/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg
index abd7c7dc1caa8b79bd6bf55e61298fa91e29b490..996cf1ec01796c647d4ce41c2b32c0f2a65f3d29 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg
@@ -23,16 +23,16 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_ring.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     ../../quartus/lofar2_unb2c_ring_pins.tcl
@@ -40,42 +40,42 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_one/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_one/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
index 99176de66880a3f3c752d77e371d2578c9bf6143..667bf5cd7f5bf19d3416712d831220eb63746ac9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
@@ -19,9 +19,9 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
 # unb2c_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
 #
 #=====================
 # QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
index 273a627af9469a3f619164eee8ded453c302cb7f..7c8ae9980110f1ddb02eef7f555b5bf6cf7a25b5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
index 1b6f161754fd025476117c836247694ef5ff6491..3d8521e7b5d3426e793d3ea31b1fc06965d1c40d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     disturb2_unb2c_sdp_station_full_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
index 4ceebdedad386e07a109627cae9cd0a15507fa48..538fc0a7169f482970d641b02d50cc56bca3bc93 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
index bc7d3a1b7e4959f22f31bbbd80ca7a282ee65b4e..0ef2f15b989ad654e1154212ccce2562b16937fd 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     disturb2_unb2c_sdp_station_full_wg_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
index ae6e4816942e867c8ed21c7f6dcf59681e4a9987..3974ff09a44fdc50a28a66125fcec7ec8435165e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
@@ -27,7 +27,7 @@ quartus_copy_files =
     ../../src/data data
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
@@ -38,89 +38,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_adc/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_adc/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
index b689b7d674278bcc88a9dabee9475a57fe4de9a9..1b7902b1c002bf26a66a0c676063597473ec455f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
@@ -18,7 +18,7 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
index 685ae42cc21c7ce7d31d4ea4a6ff7b60977d51c9..e2282099aa4d07b3662e917a1950b8e5801852cf 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
@@ -19,7 +19,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -27,18 +27,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2c_sdp_station_bf_pins.tcl
@@ -46,90 +46,90 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
index 64f05f663474c04abcfb73051fdc09cea1cf843c..11e645ad0edc2bbc8e9b3d3906558f3efeb1ae7a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
index 728eb3310d317b9891f2131dd22635378182690c..37e0022b42c50b17a24f465fd4ed098ca81678a6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
@@ -16,7 +16,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -24,18 +24,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2c_sdp_station_bf_ring_pins.tcl
@@ -43,90 +43,90 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
index 5a869c76f2093d4a8594508c9dbd601bea0717c4..9d10b75d99686fc5f4f641b25e2dca61a0b29c4d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
@@ -18,9 +18,9 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
index b7f54f3ab55eb7ab44c22b343344e5172a3df300..35f81be106a8d8e4ec9b71524725b8e3c047c919 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2c_sdp_station_fsub_pins.tcl
@@ -44,89 +44,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_fsub/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_fsub/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
index b689b7d674278bcc88a9dabee9475a57fe4de9a9..1b7902b1c002bf26a66a0c676063597473ec455f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
@@ -18,7 +18,7 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
index 65ebcc129efc0e4572564dfb8ed6c942ddfb0740..6c64a49c7eeb15784bb0c818488505e17bb71485 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2c_sdp_station_full_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
index 273a627af9469a3f619164eee8ded453c302cb7f..7c8ae9980110f1ddb02eef7f555b5bf6cf7a25b5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
index a410171732d585af43e09c416c83338a96453761..d76f06556d43819c49df330190c16ced4987df90 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2c_sdp_station_full_wg_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
index 4ceebdedad386e07a109627cae9cd0a15507fa48..538fc0a7169f482970d641b02d50cc56bca3bc93 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
index f0be972dafa25c7ad741cf512460045c6d0c3353..01ef5febaf54ef3a0479c448948ea7f77c8a741b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2c_sdp_station_xsub_one_pins.tcl
@@ -44,89 +44,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_one/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_one/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
index b689b7d674278bcc88a9dabee9475a57fe4de9a9..1b7902b1c002bf26a66a0c676063597473ec455f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
@@ -18,7 +18,7 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
index 159fb7bde4200cc8bb7f9c552d869ece565e9800..0cb7f8525d416ef13b2ca9a93156d67edf4010de 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
 [modelsim_project_file]
 modelsim_copy_files =
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
     # Overwrite bf weights with sim data
     ../../tb/data data
 
@@ -22,18 +22,18 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-     # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+     # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
     ../../quartus .
     ../../src/data data
-    $RADIOHDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 # use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
     ../../quartus/lofar2_unb2c_sdp_station.sdc
-    #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
index 78cb5f4e829362546751392aef42a210ad13b168..303c41785ce9d9e5e12e1087387f20bb2daf2d15 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
@@ -18,8 +18,8 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
 
 
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
index 7affbbc077a8e51ea5819184ea9ea1862d6b1ea1..a323e859c4a3699d996ab57a4c30ecb974092b57 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
@@ -28,10 +28,10 @@ quartus_copy_files =
    ./ . 
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl
index b0ce83474f44f1fb17d5c6f3c43a32dffc6efb16..09d3d0ca244a431c8b2ebfc3fd29a8c9d77378b3 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl
@@ -54,13 +54,13 @@ if {[catch {set sdk_root $::env(INTELFPGAOCLSDKROOT)} result]} {
 
 
 # Make sure RadioHDL installation exists
-post_message "Checking for RadioHDL installation, environment should have RADIOHDL_BUILD_DIR defined"
-if {[catch {set radiohdl_build $::env(RADIOHDL_BUILD_DIR)} result]} {
-  post_message -type error "RadioHDL installation not found.  Make sure RADIOHDL_BUILD_DIR are correctly set"
+post_message "Checking for RadioHDL installation, environment should have HDL_BUILD_DIR defined"
+if {[catch {set radiohdl_build $::env(HDL_BUILD_DIR)} result]} {
+  post_message -type error "RadioHDL installation not found.  Make sure HDL_BUILD_DIR are correctly set"
   post_message -type error "Terminating pre-flow script"
   exit 2
 } else {
-  post_message "RADIOHDL_BUILD_DIR=$::env(RADIOHDL_BUILD_DIR)"
+  post_message "HDL_BUILD_DIR=$::env(HDL_BUILD_DIR)"
 }
 
 # Load OpenCL BSP utility functions
@@ -99,8 +99,8 @@ if {$revision_name eq "flat"} {
 }  
  
 # Copy qsf file
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
-  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf 
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
+  file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf 
 } else {
   post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
   post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
@@ -109,16 +109,16 @@ if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_na
 
 }
 # Copy memory initialization files
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
-  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex 
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
+  file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex 
 } else {
   post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
   post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
   post_message -type error "Terminating pre-flow script"
   exit 2
 }
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
-  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
+  file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
 } else {
   post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
   post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
index d7a2b9f42b341c6577197ff099a9271af9b026e3..55b81d9db494c416a6b5974d314b52147e4742b4 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
    ./ . 
     
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     
@@ -37,8 +37,8 @@ quartus_vhdl_files =
 quartus_qip_files =
 
 quartus_ip_files = 
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
+    $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl
index 438f99f0a12e80fd74dd8ceef9eeedd90060c6d4..e9ce740ac393cb114f1d6702f125256f92009175 100755
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl
@@ -54,13 +54,13 @@ if {[catch {set sdk_root $::env(INTELFPGAOCLSDKROOT)} result]} {
 
 
 # Make sure RadioHDL installation exists
-post_message "Checking for RadioHDL installation, environment should have RADIOHDL_BUILD_DIR defined"
-if {[catch {set radiohdl_build $::env(RADIOHDL_BUILD_DIR)} result]} {
-  post_message -type error "RadioHDL installation not found.  Make sure RADIOHDL_BUILD_DIR are correctly set"
+post_message "Checking for RadioHDL installation, environment should have HDL_BUILD_DIR defined"
+if {[catch {set radiohdl_build $::env(HDL_BUILD_DIR)} result]} {
+  post_message -type error "RadioHDL installation not found.  Make sure HDL_BUILD_DIR are correctly set"
   post_message -type error "Terminating pre-flow script"
   exit 2
 } else {
-  post_message "RADIOHDL_BUILD_DIR=$::env(RADIOHDL_BUILD_DIR)"
+  post_message "HDL_BUILD_DIR=$::env(HDL_BUILD_DIR)"
 }
 
 # Load OpenCL BSP utility functions
@@ -99,8 +99,8 @@ if {$revision_name eq "flat"} {
 }  
  
 # Copy qsf file
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
-  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf 
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
+  file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf 
 } else {
   post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
   post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
@@ -109,16 +109,16 @@ if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_na
 
 }
 # Copy memory initialization files
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
-  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex 
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
+  file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex 
 } else {
   post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
   post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
   post_message -type error "Terminating pre-flow script"
   exit 2
 }
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
-  file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
+  file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
 } else {
   post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
   post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
diff --git a/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile b/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile
index 7a1ca2b4383711917a2453849b38e57cfe290c47..75d6c4bce509a3805446f940f65ada070387e725 100644
--- a/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile
+++ b/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile
@@ -23,7 +23,7 @@ endif
 UNB2B_BSP=ta2_unb2b_bsp
 
 # Compile directory
-BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+BUILDDIR=$(HDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
 
 
 ##############################
diff --git a/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp b/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp
index 4eca458dfffc455c1abff5bb81b16f76bf1dd952..4bdf25047107e1fa111241fb6286a4aa9e1f717b 100644
--- a/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp
+++ b/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp
@@ -23,7 +23,7 @@
 * . Test the ta2_unb2b_mm_demo OpenCL application in emulator
 * Description:
 * . Run: -> make ta2_unb2b_mm_demo
-* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/ta2_unb2b_mm_demo/bin
+* . Navigate to -> cd $HDL_WORK/unb2b/OpenCL/ta2_unb2b_mm_demo/bin
 * . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
 * *********************************************************************** */
 #include <CL/cl_ext_intelfpga.h>
diff --git a/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile b/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile
index cf5531d95104da9f7a01e2f0c4ad1f5c8d429971..ee717fbe16a7e75a52a9ae29623687c78f3b4d40 100644
--- a/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile
+++ b/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile
@@ -23,7 +23,7 @@ endif
 UNB2B_BSP=ta2_unb2b_bsp
 
 # Compile directory
-BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+BUILDDIR=$(HDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
 
 
 ##############################
diff --git a/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp b/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp
index 0aa76d704dba9240d636241dca85661dd66bd227..aa7d7fb0bdc257f595d792462dca8b0da8d2d68b 100644
--- a/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp
+++ b/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp
@@ -23,7 +23,7 @@
 * . Test the ta2_unb2b_qsfp_demo OpenCL application in emulator
 * Description:
 * . Run: -> make ta2_unb2b_qsfp_demo
-* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
+* . Navigate to -> cd $HDL_WORK/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
 * . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
 * *********************************************************************** */
 #include <CL/cl_ext_intelfpga.h>
diff --git a/applications/ta2/doc/README.txt b/applications/ta2/doc/README.txt
index 9edf518126488bb603158525996959150560c40e..903444cfca7c6b1cb9c2f0262a8382e30ecfe1cb 100644
--- a/applications/ta2/doc/README.txt
+++ b/applications/ta2/doc/README.txt
@@ -37,13 +37,13 @@ The ta2 project folder contains 4 sub-folders:
     export QUARTUS_ROOTDIR=$INTEL_ROOTDIR/quartus
     export QSYS_ROOTDIR=$INTEL_ROOTDIR/quartus/sopc_builder/bin
 
-    export RADIOHDL_WORK=${GIT}/hdl
+    export HDL_WORK=${GIT}/hdl
     export RADIOHDL_CONFIG=${GIT}/radiohdl/config
-    export RADIOHDL_BUILD_DIR=${RADIOHDL_WORK}/build
+    export HDL_BUILD_DIR=${HDL_WORK}/build
 
     export INTELOCLSDKROOT=$INTEL_ROOTDIR/hld
     export INTELFPGAOCLSDKROOT=$INTEL_ROOTDIR/hld
-    export AOCL_BOARD_PACKAGE_ROOT=$RADIOHDL_WORK/applications/ta2/bsp
+    export AOCL_BOARD_PACKAGE_ROOT=$HDL_WORK/applications/ta2/bsp
     export PATH=$PATH:$INTEL_ROOTDIR/hld/bin
     export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$INTELOCLSDKROOT/host/linux64/lib
     export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$AOCL_BOARD_PACKAGE_ROOT/linux64/lib
@@ -69,14 +69,14 @@ The example application used is "ta2_unb2b_qsfp_demo", this application generate
 to 40GbE and 10GbE. In emulation, this design is verified by comparing the 10GbE and 40GbE outputs to check if 
 the data is identical. If that is the case, the output will state "PASSED".
 
-- Navigate to $RADIOHDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
+- Navigate to $HDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
 - First we need to compile the OpenCL application for emulation and compile the host code. This can be done by
   the provided Makefile. Execute the command:
     -> make ta2_unb2b_qsfp_demo
 - This creates the executable "host" and the aocx file "ta2_unb2b_qsfp_demo.aocx" located at:
-  $RADIOHDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
+  $HDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
 - First navigate to that directory and then run this executable using the following commands:
-    -> cd $RADIOHDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
+    -> cd $HDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
     -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
 - At the end of the application output you should see "PASSED".
   
@@ -85,7 +85,7 @@ the data is identical. If that is the case, the output will state "PASSED".
 The example application used is "ta2_unb2b_qsfp_demo", this application generates UDP packets and outputs them 
 to 40GbE and 10GbE. On hardware, you can verify the design by connecting a PC to the 40GbE (QSFP1) or 
 10GbE (QSFP0) output and check for incoming packets using tcpdump.
-- Navigate to $RADIOHDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
+- Navigate to $HDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
 - This example design uses the "ta2_unb2b_bsp" OpenCL BSP. If you did not initialize the BSP already, 
   execute the commands below.
     -> quartus_config unb2b; run_qsys unb2b name_of_your_BSP board.qsys;
@@ -96,7 +96,7 @@ to 40GbE and 10GbE. On hardware, you can verify the design by connecting a PC to
 
 
 5. CREATING NEW OPENCL APPLICATION
-- Start by copying the example application located in $RADIOHDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
+- Start by copying the example application located in $HDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
 - rename the folder and ta2_unb2b_qsfp_demo.cl
 - If you need to use a specific OpenCL BSP, open the Makefile and change the BSP Name into the name of the BSP 
   you want to use (see OVERVIEW).
@@ -106,7 +106,7 @@ to 40GbE and 10GbE. On hardware, you can verify the design by connecting a PC to
 - With the provided makefile you can compile your application for UniBoard2b by executing:
   make myApp.sof myApp.rbf
     where "myApp" is the name of your .cl file
-- Note that by default your application is build in $RADIOHDL_BUILD_DIR/unb2b/OpenCL/myApp
+- Note that by default your application is build in $HDL_BUILD_DIR/unb2b/OpenCL/myApp
   where "myApp" is the name of your design directory file. This directory includes the 
   Quartus project for analysis using the Quartus GUI.
 - For emulation, you need to modify the host code located in host/src/main.cpp to fit your design. 
@@ -139,7 +139,7 @@ script in $UPE_GEAR/peripherals
 
 8. CREATING A NEW BSP
 - BSPs are located in "$AOCL_BOARD_PACKAGE_ROOT/hardware" which is defined as
-  "$RADIOHDL_WORK/applications/ta2/bsp/hardware"
+  "$HDL_WORK/applications/ta2/bsp/hardware"
 - To create a new BSP it is easiest to copy an existing one. In this example we would make a copy of the 
   directory "ta2_unb2b_bsp" and rename it to example_bsp.
 - inside the new folder "example_bsp" we need to change 2 files: board_spec.xml and hdllib.cfg
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
index dc445ef7c50de4c5c103da743dba49e403c0846b..3ce40bf35c775de01e226ac55e41088de7002b1a 100755
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
@@ -1,5 +1,5 @@
 post_message "Running ta2_unb2b_10GbE script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
 #============================================================
 # Files and basic settings
 #============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl
index 0efe60d92c79cd5249b817c6207a2c0cb980d56b..ca34c982b744c989362954813208f9d522ecabce 100755
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl
@@ -1,5 +1,5 @@
 post_message "Running ta2_unb2b_1GbE script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
 #============================================================
 # Files and basic settings
 #============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
index 5b31bc919ca1bfcd4977d52fe874cf745ad22b2d..a44367c0896d1df8b2d1aa4d3faf28b8e8329de5 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
@@ -20,5 +20,5 @@ quartus_copy_files =
     arria10_40g_atx_pll.ip .
 
 quartus_ip_files = 
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
+    $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
+    $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
index 9745011213d9e1a0b9541f59cb895324454f3864..84cd116af1a02e32034d547ef8bc63a3c6191df6 100755
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
@@ -1,5 +1,5 @@
 post_message "Running ta2_unb2b_40GbE script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
 #============================================================
 # Files and basic settings
 #============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl
index 703ef65a7610794cccd2386a3e4a7c6b3876b818..8327d3bcaadc29753e5968b03f6d43d43b4fad07 100755
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl
@@ -1,5 +1,5 @@
 post_message "Running ta2_unb2b_ddr script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
 #============================================================
 # Files and basic settings
 #============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
index 577113d356a650c1056e425e4fe6714670ac5955..87b4840b27806b47c720c6d54e45d335e21e1a41 100755
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
@@ -1,5 +1,5 @@
 post_message "Running ta2_unb2b_jesd204b script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
 #============================================================
 # Files and basic settings
 #============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl
index f175d824e5826c30b949c5b3772885ba397fa0ef..3b68ee9c15c03d1a522f4d534abe8b084ee11e10 100755
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl
@@ -1,5 +1,5 @@
 post_message "Running ta2_unb2b_mm_io script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
 #============================================================
 # Files and basic settings
 #============================================================
diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 567a97eff3cac97ff165a74a897ea77ec4fa7e11..2b487e3ad5a77b962bbeabd60c8d3de02351bd07 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology = ip_stratixiv
 synth_files =
     # Commented unb1_bn_capture.vhd and SOPC because only the node is reused.
     # The SOPC causes a simulation error if it not there, because it is instantiated as an entity
-    #$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
+    #$HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
     src/vhdl/unb1_bn_capture_pkg.vhd
     src/vhdl/unb1_bn_capture_input.vhd
     src/vhdl/node_unb1_bn_capture.vhd
@@ -24,27 +24,27 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    $RADIOHDL_WORK/libraries/io/i2c/tb/data data   
-    $RADIOHDL_WORK/libraries/base/diag/src/data data
+    $HDL_WORK/libraries/io/i2c/tb/data data   
+    $HDL_WORK/libraries/base/diag/src/data data
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files = 
     quartus/sopc_unb1_bn_capture.sopc .
-    $RADIOHDL_WORK/libraries/io/i2c/tb/data data
-    $RADIOHDL_WORK/libraries/base/diag/src/data data
+    $HDL_WORK/libraries/io/i2c/tb/data data
+    $HDL_WORK/libraries/base/diag/src/data data
 
 quartus_qsf_files = 
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_bn_capture_pins.tcl
     
-quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 
 
diff --git a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
index f2cfef868fd2e9047e152cf979dd87185a7828fb..24c6bc272344dc1c8eb534c961781baf92c80072 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
@@ -1,13 +1,13 @@
 # Pin assignments
 # -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 # -- 1GbE Control Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
 # -- BN_BI ADC pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
 
 
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index db644b06b44f6bcd17363e2e983e7fc2f36e9148..077e3e4c429f3c1b24afabbd283f635210d34420 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
     src/vhdl/node_unb1_bn_terminal_bg.vhd
     src/vhdl/unb1_bn_terminal_bg.vhd
     
@@ -16,25 +16,25 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    $RADIOHDL_WORK/libraries/base/diag/src/data data
+    $HDL_WORK/libraries/base/diag/src/data data
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files = 
     quartus/sopc_unb1_bn_terminal_bg.sopc .
-    $RADIOHDL_WORK/libraries/base/diag/src/data data 
+    $HDL_WORK/libraries/base/diag/src/data data 
 
 quartus_qsf_files = 
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_bn_terminal_bg_pins.tcl
     
-quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
index 0a38a91c5bde1dc5bcca249cfc476fd6cef064ad..5429d45602f00d8308953f2d234292ad28b7b56e 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
@@ -1,14 +1,14 @@
 # Pin assignments
 # -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 # -- 1GbE Control Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
 # -- Mesh pins. 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
 
 
diff --git a/boards/uniboard1/designs/unb1_ddr3/doc/README b/boards/uniboard1/designs/unb1_ddr3/doc/README
index dcc27dd23312d4c54bb469591cb58ecfe5482341..cb0a9e2e22fa22da4d700dc7bbdbea5af1d94c73 100644
--- a/boards/uniboard1/designs/unb1_ddr3/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3] in RadionHDL
 --------------------------------------------------------------
 
 Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC:
     run_sopc unb1 unb1_ddr3
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 05d368e3ebc99d39a4bf6b963926fffe32ddb6ce..4ab692dee2a31e4e350f2842a91dfbac4602ec14 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
     src/vhdl/node_unb1_ddr3.vhd
     src/vhdl/mmm_unb1_ddr3.vhd
     src/vhdl/unb1_ddr3.vhd
@@ -19,7 +19,7 @@ test_bench_files =
 modelsim_copy_files = 
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     
 [quartus_project_file]
 synth_top_level_entity =
@@ -28,17 +28,17 @@ quartus_copy_files =
     quartus/sopc_unb1_ddr3.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
 
 quartus_tcl_files =
     quartus/unb1_ddr3_pins.tcl
     quartus/unb1_ddr3_pins_constraints.tcl
     
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
index caedfb746e613f2dc41d1ef37343d7a35ee4c56f..25f3867aad50003c873dcf22fe9a2e822026a877 100644
--- a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
@@ -20,8 +20,8 @@
 ###############################################################################
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
 # -- include the clock pin
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
index 43dcd7791d203a5c3e68da9950f995b562b16edd..5b3888c84c5c1b9231c385df75423607a93b4199 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3_reorder] in RadioHDL
 --------------------------------------------------------------
 
 Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC:
     run_sopc unb1 unb1_ddr3_reorder
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
index 9834de8f9a11bb8e1edd44377744c81eec020bf8..1de832edaefcdd768cdeee1dc3bb94c4cea53fb8 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
@@ -20,7 +20,7 @@
 ###############################################################################
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 
 # -- include the clock pin
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 8d92055e78e0a50b1ff6eb8e4c7463199d13ae1b..cb54b4954d55bcf3a313483f51e485a1e81bc97b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =   
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     ../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,8 +42,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $HDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
     
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index a995636301fc5c0a3f4b3bf534d98e5ec25d8fbc..aa6cbdbaea3ce782ef648b02e54f510d1561868b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =   
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     ../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,8 +42,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
-    $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $HDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
     
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
index d2fd86f43c99b07f84b4cc3deba00f64d7de6437..7236c4c4113924743c2c913b54fcd2036655a171 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_ddr3_transpose] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_sopc unb1 unb1_ddr3_transpose
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 3c859fd55b86d0a317c5c1fcbe9d3dbec58e4b1b..67e8810fd93dd8113fd87f62b4e6929f9bde18b6 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
     src/vhdl/mmm_unb1_ddr3_transpose.vhd
     src/vhdl/unb1_ddr3_transpose.vhd
     
@@ -19,7 +19,7 @@ test_bench_files =
 modelsim_copy_files = 
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -29,7 +29,7 @@ quartus_copy_files =
     quartus/sopc_unb_ddr3_transpose.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_ddr3_transpose_pins.tcl
@@ -38,8 +38,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
index 1f162d6353dd4b10881cb3cf1c732fcd1e3a58a4..d3143f5c52b839da0cf03ab009c2aeaee1145f22 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
@@ -3,5 +3,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index 449b3d56363644be28435e243a124b71a3851b3e..1d39585b0ab2d6af7584f9b67beb9c80ec4630e6 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
     src/vhdl/mmm_unb1_fn_terminal_db.vhd
     src/vhdl/unb1_fn_terminal_db.vhd
     
@@ -24,13 +24,13 @@ quartus_copy_files =
     quartus/sopc_unb1_fn_terminal_db.sopc .
 
 quartus_qsf_files =                                                       
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_fn_terminal_db_pins.tcl
     
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_heater/doc/README b/boards/uniboard1/designs/unb1_heater/doc/README
index 4b3e99c67cbd5fb485cd35f6b531738da64745e5..9f98f9ab081f180e936b9170a2705a1d2c4b46d8 100644
--- a/boards/uniboard1/designs/unb1_heater/doc/README
+++ b/boards/uniboard1/designs/unb1_heater/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_heater] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_qsys unb1 unb1_heater
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index b142a97e96336039816c7864f34c156d0c395d34..7d927f97f91fbfbd1f807c26951dbd6cc9da609d 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     quartus/qsys_unb1_heater.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     quartus/unb1_heater_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
index ff0099460334af052cfc829b7180226b563353f8..18d3f53057c022fab462dccbff1f5ca73d9da7da 100644
--- a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
+++ b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
@@ -19,8 +19,8 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/README b/boards/uniboard1/designs/unb1_minimal/doc/README
index a0085f2f59c52ce8eb99e1dec7658b1c7d4b395d..d6d943c2fdcd7abc0acf84e9f0522bff7a613552 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/README
+++ b/boards/uniboard1/designs/unb1_minimal/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_minimal] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_sopc unb1 unb1_minimal_sopc
@@ -58,12 +58,12 @@ Convert .sof to .rbf:
 
 
 Send to LCU capture5:
-    scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/  # QSYS
+    scp $HDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/  # QSYS
     or:
-    scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/  # SOPC
+    scp $HDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/  # SOPC
 
     # Now login on capture5 and use pythonscript to program flash:
-    cd $RADIOHDL_WORK/boards/uniboard1/designs/unb1_minimal/tb/python
+    cd $HDL_WORK/boards/uniboard1/designs/unb1_minimal/tb/python
 
     # for example use frontnode 0 on uniboard 0:
     python tc_unb1_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb1_minimal_qsys.rbf   # QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
index 883ec70f72c66a37c07d1692f961fe8e4417ae53..7e1166a1613c72d24e1511912ce527632e674545 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
+++ b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
@@ -37,7 +37,7 @@ run: rm -rf ~/svn/UniBoard_FP7/RadioHDL/trunk/build/*
         ../../quartus/qsys_unb1_minimal.qsys .
 
     quartus_qip_files =
-        $RADIOHDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+        $HDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 11. For future compilations the file qsys_unb1_minimal.qsys
     (after SOPC->QSYS it is this file: ~/RadioHDL/trunk/build/quartus/unb1_minimal/sopc_unb1_minimal.qsys)
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index 83c59ab9e86d6957a7803866bc9f0a9caddf590b..f78ab28d3cb8808fe0e41c5887748c3b6deec7ab 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
     src/vhdl/qsys_unb1_minimal_pkg.vhd
     src/vhdl/mmm_unb1_minimal.vhd
     src/vhdl/unb1_minimal.vhd
diff --git a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
index ff0099460334af052cfc829b7180226b563353f8..18d3f53057c022fab462dccbff1f5ca73d9da7da 100644
--- a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
+++ b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
@@ -19,8 +19,8 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index 13fa7738f7019913ee5fa4b8f3ef809b8acf8f70..5ebd2daf7e5b624ef43ffb587f890ad9e4a280de 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
     qsys_unb1_minimal_mm_arbiter.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
@@ -32,7 +32,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index 0cb052797c19454015e07816390d3709c3ad9125..bcf12edfc3f2c547a39df61b61d4bece3208d715 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../quartus/qsys_unb1_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index ba9098f82fc57660fba7e660a29cf2b050b0ac74..980f92714ab2f87d15440cbe8a5146a93ea83c96 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     ../../quartus/qsys_wo_pll_unb1_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files =
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index 872744005aab2a2fbfdaa602f407c791f7ab6d81..38f930dfce26a6c038920ba86754436134637097 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
     ../../quartus/sopc_unb1_minimal.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_minimal_pins.tcl
@@ -32,7 +32,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index 0179234f75cf6f9636149ecf3334e126abf1e5d2..460efd6411c79ad5cac3c7aa2d2704968e41ccc2 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
+    $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
     src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -27,16 +27,16 @@ quartus_copy_files =
     src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_terminal_bg_mesh_db_pins.tcl
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index 9939ae7eeb01e10d89cb2d4e8f644b991e6eb1d0..56275c5acbb742e8328470c35665698f417521c1 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -16,16 +16,16 @@ The following revisions are available for unb1_test (see the directories in ../r
 
 
 -> In case of a new installation, the IP's have to be generated for Stratix IV. 
-   In the: $RADIOHDL_WORK/libraries/technology/ip_stratixiv 
+   In the: $HDL_WORK/libraries/technology/ip_stratixiv 
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb1
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb1
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb1
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb1
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -91,7 +91,7 @@ Convert .sof to .rbf:
 
 Send to LCU (capture5):
     # for example the unb1_test_10GbE revision:
-    scp $RADIOHDL_WORK/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
+    scp $HDL_WORK/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
 
     # Now login on capture5 and use pythonscript to program flash:
     cd unb1_test/tb/python
@@ -118,10 +118,10 @@ defining the pinning:
 2. unb1_test_ddr_MB_I_II_pins_constraints.tcl (pin attributes like termination etc..)
 
 The 2nd tcl file can be created with Quartus. Here are the steps:
-- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
+- generate the IP's by running: $HDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
 - Start synthesis in the Quartus GUI. Only the Analysis step!!
 - Then in Quartus click: Tools/TclScripts. 
-  Open the Tcl file: $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+  Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
   Click Run.
 - Then Continue synthesis with Fitter, or restart with Analysis.
 - Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
index 27ecdf6551de137050de835fe1ae7336449ccc64..5a9cbf2f0356699a9c7baa618529ff7b33d8ef5a 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
 
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index cd2f29bacfc8c8cb2c18b66b74074c865ca33dca..1557c1cb2a2781da5981e5febefc965981382072 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     quartus/unb1_test_10GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index 78d24bed859fe4c9ea2a3e876cc0430f885c0fc5..e51c661b0017a38c1a89f598e014f09dea015c52 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     quartus/unb1_test_10GbE_tx_only_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index aca536d5a71877e379626af55c4ed1fd76df1160..7f32db6b5b0ea6649ec9145093ceab63a839a361 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_1GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
index 27ecdf6551de137050de835fe1ae7336449ccc64..5a9cbf2f0356699a9c7baa618529ff7b33d8ef5a 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
 
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 1640cf177a84738ed038c0dd10f9740d4ed5fd6c..db8a29de1eb2d464a95a4d7892773d5ee73208d1 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     ../../quartus/unb1_test_pins.tcl
@@ -40,9 +40,9 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index 64c9950b5d56a1dd6efba9ba7e6bed4281667c3c..69e98d5ae952ca4c796270f15902aac19a3cff67 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
     
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_pins.tcl
@@ -40,9 +40,9 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
index bac6c86884452254d942b599d9730840d5c5c71f..ff94589debe99ae3183c9c653b722e5798ba842c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 45d53b348e9277fc93173ca4a042858dc4abde73..6af099891e04a24fadcf5af7ab5d93c43a8c2a07 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -29,10 +29,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -41,8 +41,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
index e6c6cd90d5f2e13c726c577f6cd1867edf780740..a554f7d656400d8f20d909b153b28b23162d8f76 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index e6ab3a6e1e53b21e04aec1a6e9a7174d5fef4f69..39406f4387a70b931d90f18700512e2b3827948c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
index f4fac0a19d69e96830c45895f14a46f9121e43b7..010d8290f182cc03b79169361dd8d9cfed06cc4e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index c686e3dc316267ab5b53890ceccfae883da4e143..c8da98b6d6d73ef9a43f14ade5fd2bae38d0994f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
index bac6c86884452254d942b599d9730840d5c5c71f..ff94589debe99ae3183c9c653b722e5798ba842c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index a82fc8400e3c133a771a001a9fb094a7ea87c32f..3ad90bc20925837414c182b3cd505c3ce1b0d8b8 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index 02712a8aa2a01190b75c7ac80886cbcb30bea360..0edfab36e2a4b9fec2485488deb3d990dd8606b9 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index e299f486007a5d3f5b81d89048b2e2f43e4a8e83..32662cbc7eebaddfbf935e197a99f702e37c9944 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -27,10 +27,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     
 quartus_tcl_files =
     quartus/unb1_test_ddr_MB_I_II_pins.tcl
@@ -39,8 +39,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
-    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
index bac6c86884452254d942b599d9730840d5c5c71f..ff94589debe99ae3183c9c653b722e5798ba842c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
 # -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 2fdbe5db8cf17a85abf711380108686fdff7d491..ae30f592310e6d7544636cffccd8458ba91342ad 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
+    $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
     src/vhdl/mmm_unb1_tr_10GbE.vhd
     src/vhdl/unb1_tr_10GbE.vhd
     
@@ -28,7 +28,7 @@ quartus_copy_files =
 #    src/hex/ hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_tr_10GbE_pins.tcl
@@ -36,10 +36,10 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index f9b219ceaa9478a2fb8206f4cfdcc6e9800a8ae1..1f76436ec62884558f5280b26a768859169784fb 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -43,9 +43,9 @@ synth_files =
     
     src/vhdl/unb1_board_peripherals_pkg.vhd
 
-    # For BN the $RADIOHDL_WORK/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is 
+    # For BN the $HDL_WORK/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is 
     # referred to directly in the apertif_unb1_bn_filterbank library.
-    # For FN a copy of $RADIOHDL_WORK/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+    # For FN a copy of $HDL_WORK/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
     # is taken via this unb1_board library:
     src/vhdl/node_unb1_fn_terminal_db.vhd    
     
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
index b18c31a46b325b5df7376ddc0a94f8d11c94b1c8..2ce61db040435332aa592021390dae7ce82bc119 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
@@ -23,7 +23,7 @@
 # Pin assignments
 
 # -- Common
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
 
 # -- Back Node specific
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
index c023237cd682a1c2125245d25499b8de0ab1d40a..f6814e377cf8f3a6c50707d30281912354d24616 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
@@ -23,10 +23,10 @@
 # Back node specific pin assignments
 
 # -- Backplane Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
 
 # -- FN to BN Interface added 08-01-2010
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
 
 # -- ADC Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
index fa264372aaeff6c369645f37a3d8d9bcbcd6f400..6996180edcc19c86b9ba7685ebd051cae665819f 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
@@ -23,22 +23,22 @@
 # Common pin assignments for front_node and back_node
 
 # -- General: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 
 # -- FPGA Interconnects Front-Node Back-Node
 #    Clocks only as transceiver pins are now different (08-01-2010)
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
-#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
 
 # -- 1GbE Control Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 
 # -- SO-DIMM Memory Banks I and II
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
 
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
index ba55f0e9e57578902902fe4ed35b10ed48fe5cbb..58070746bdbea8c67dcb54a3dc490792e07f0440 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
@@ -23,7 +23,7 @@
 # Pin assignments
 
 # -- Common
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
 
 # -- Front Node specific
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
index afbd717cd6e5cfbc14a7e13090d8cb109923f7b1..54c26398da5e47518e9bb6f81685e21f72eb0de8 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
@@ -23,9 +23,9 @@
 # Front node specific pin assignments
 
 # -- Front Interface (10GbE)
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
 
 # -- FN to BN Mesh Interface added 08-01-2010
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
 
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
index d2a233a4719c1fe0d84182feb09bc5a0a4de2510..c122cf2f13d7215d436457c28392378afcfd21eb 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
@@ -20,6 +20,6 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
 
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
index 856ec42e60f16f6d36698eddb61ff6f80d23e28a..04529c1da7788b599df2dcab355504ad7e27712a 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
@@ -20,7 +20,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
index 22f4d234b233f608187821f11f772e71fc37d591..6d398b9113ee2284b2ece631d7dd109cfba61860 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
@@ -20,7 +20,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
 
 set_location_assignment PIN_AA2 -to SA_CLK
 set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
index 926e243c89da0a81643c08371dd4731e6727cb25..3cfc75dd90bb6192c6c390ed310ed5f36105e974 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
@@ -20,5 +20,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
index df0879811661f91da6e42e12350bf8ac41cdcdc8..5b320e44717c05bd0a0028926a9b2eb9304f5e4b 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
 
 # Device:
 set_global_assignment -name FAMILY "Stratix IV"
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
index 98f793e9014b42b62e892550d320b1c140b2a771..311bade3cc630174220b6efaccfdd83cbf36ee00 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
 
 # This file contains includes that should be added to another project QSF before 
 # user contraints and/or QIPs are added.
@@ -48,7 +48,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
 set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
 
 # Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
+set_global_assignment -name SDC_FILE $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
 
 # Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
index 821a28fa2deba7dca47d3701f1833fe25f2969f2..61b7dcf2e6c15599092a21f3de7de5844797db30 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
@@ -22,12 +22,12 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
 #
 # This file contains includes that should be added to another project QSF after certain
 # user contraints (DDR3 timing constraints for instance) have been included. 
 
 # Post Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
+set_global_assignment -name SDC_FILE $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
 
 
diff --git a/boards/uniboard2/designs/unb2_led/hdllib.cfg b/boards/uniboard2/designs/unb2_led/hdllib.cfg
index 5ee94b1931ee6dd8e2c2229ef13d513b432ee9e5..7fbc76b0006affaab90c2526e6f6935c375e46cc 100644
--- a/boards/uniboard2/designs/unb2_led/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
 quartus_copy_files =
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
index 23bcf027b1639fd7876c128c82f3bd7f83f8ac87..ec996441dd9bdfaff06fcfd4a01ada4257f0922b 100644
--- a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_minimal/doc/README b/boards/uniboard2/designs/unb2_minimal/doc/README
index 037b0a8df8170885130d85039477ac353bf44fa8..e71eef635d36a9c883ffb48dfe3d756ec11c252b 100644
--- a/boards/uniboard2/designs/unb2_minimal/doc/README
+++ b/boards/uniboard2/designs/unb2_minimal/doc/README
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2_minimal] in RadionHDL
 -----------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
+   In the: $HDL_WORK/libraries/technology/ip_arria10
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
 
 
 2. Generate MMM for QSYS:
@@ -105,7 +105,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
+  (in $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index 93e521fbb0eb01f56f60c93e98316de8c28a1e8c..5cea81da2e2e50906b0fb1f8be7639309f317d67 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb2_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_minimal_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+    $HDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
index 23bcf027b1639fd7876c128c82f3bd7f83f8ac87..ec996441dd9bdfaff06fcfd4a01ada4257f0922b 100644
--- a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index 0dff5ebf0ab9bcd3cd838ef7ffe626ee466cf51d..b08eeacfa9bea7ca6fbe7d8a44e2e645f4599ae8 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -25,18 +25,18 @@ The following revisions are available for unb2_test (see the directories in ../r
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10 
+   In the: $HDL_WORK/libraries/technology/ip_arria10 
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -117,7 +117,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
+  (in $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
index 7df88096be123780f90fb3b696632aa8be80402c..8ae5539c0486009c9e6ee8a5437919032f0b5fce 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
@@ -19,7 +19,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 94a1d7a4b5dc81519f691645119e391a112bd0a6..795ac88ce98f8ea5519a153dba247e6a1538ca01 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -44,11 +44,11 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
     quartus/unb2_test_10GbE.sdc
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_test_10GbE_pins.tcl
@@ -56,7 +56,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $HDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
index e14bd851bb3d3458c1a4d10dfb7bdc0f3a7b3fe7..74d121cc3a6dd4cb157b374fb0cbddd8e6ec59d4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index 71f2e12e3d263d1c5694968f434eae78e10aaec4..f88850166ff2ac7c8b94bc23592dc296fdaaab6a 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_test_1GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $HDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
index 23bcf027b1639fd7876c128c82f3bd7f83f8ac87..ec996441dd9bdfaff06fcfd4a01ada4257f0922b 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index 980805831d7e154500d89e17e353eca603cb1ff6..f22d623cee5874130101d0e97046ab9548f7da1e 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -49,11 +49,11 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_sdc_files =
     quartus/unb2_test_10GbE.sdc
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 quartus_tcl_files =
     quartus/unb2_test_all_pins.tcl
@@ -61,7 +61,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $HDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
index f979adc2ee27b8dc6aca7f6e739fa141e5005e2f..e28eaa9bd8db2660a96b9cf418be6bd8a1e0b1f4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
@@ -19,6 +19,6 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 0e60dc6cc014f1f1c2b984b2e25f322851d903a0..74da1480cd2074e1dc5bd65705a41ea5d25a33cc 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl    
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl    
 
 
 [quartus_project_file]
@@ -33,16 +33,16 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 quartus_tcl_files =
     quartus/unb2_test_ddr_MB_I_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
index 1830b7b880bf62e41a8118175db3260dbe2407f9..c6ac15c9b4961bbdf37ea1e686bfdf2179c8b241 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index 2d80edfff0b5a8c85243997e0a3afb648702ba4f..93d869361489b73b2f5c83199ba485412867f6de 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,16 +33,16 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 quartus_tcl_files =
     quartus/unb2_test_ddr_MB_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
index 1830b7b880bf62e41a8118175db3260dbe2407f9..c6ac15c9b4961bbdf37ea1e686bfdf2179c8b241 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 69ccd15818216ce41350817cb15f3085964681e2..8404211bf7f7fe2a89c42edbdcd96ba2c7b0d899 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,16 +33,16 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+    $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 quartus_tcl_files =
     quartus/unb2_test_ddr_MB_I_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+    $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
index 1830b7b880bf62e41a8118175db3260dbe2407f9..c6ac15c9b4961bbdf37ea1e686bfdf2179c8b241 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 94e14c4340bb227b0f9498d0fe4f79d587cd5a69..5e5c7a8b7bdffd82eb4477d2a2a6f8ad0e6e3463 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2_test_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-  -- $RADIOHDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
+  -- $HDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
   -----------------------------------------------------------------------------
   
     component qsys_unb2_test is
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
index 0cedbdb8b49254da80e38e190d33249cce216b4d..c64bca4f5b21f71326c05802bdce93c096bc552e 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
 
 # Device:
 set_global_assignment -name FAMILY "Arria 10"
diff --git a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
index 8788e379fa87b9245e747a06d0a90b8250953e68..0a9d91210c8c21cd15e163cf6ba45f70643c5aaf 100644
--- a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
 ------------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
+   In the: $HDL_WORK/libraries/technology/ip_arria10_e3sge3
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
 
 
 2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+  (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 606ea20f76bfe81095761ae13c27bce1653b5027..6650fbad385e8ae29b75456eed7f1edc0b9cab0e 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb2a_heater.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_heater_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
index 3374b678b991559244f05d0b42f393cde9f1c345..1a90a0c0ba0563d793e70cd40c4e5f62c5644c6f 100644
--- a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
index 9d75b890c296ee991fcb46050c4b5fd41e2387b8..5aad148bc901358ce6daee9c29541eef9457c461 100644
--- a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
 quartus_copy_files =
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
index 3374b678b991559244f05d0b42f393cde9f1c345..1a90a0c0ba0563d793e70cd40c4e5f62c5644c6f 100644
--- a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 37859f9f848528b736ddcff61a7073495f38679f..01048d3872085fdb876aa0a9bb9ab2890d37b637 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -2,19 +2,19 @@ Quick steps to compile and use design [unb2a_minimal] in RadionHDL
 ------------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
+   In the: $HDL_WORK/libraries/technology/ip_arria10_e3sge3
    directory; run the bash script: ./generate-all-ip.sh
    -> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
-      cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+      cd $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
       ./run_patch.sh
 
 -> In case of a fresh compilation, delete the build directory.
-    rm -r $RADIOHDL_WORK/build
+    rm -r $HDL_WORK/build
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
 
 
 2. Generate MMM for QSYS:
@@ -63,7 +63,7 @@ In case of needing the Quartus GUI for inspection (this starts the Quartus 15.1
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal) for each FPGA
+            Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2a/quartus/unb2a_minimal) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
@@ -98,7 +98,7 @@ For generating a Factory image .RBF file:
 
     run_rbf unb2a --unb2_factory unb2a_minimal
 
-The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal
+The .RBF file is now in $HDL_WORK/build/unb2a/quartus/unb2a_minimal
 Now copy the .RBF file to the LCU host with 'scp'
 
 (b)
@@ -109,7 +109,7 @@ Program User image:
 Program Factory image:
     python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_minimal.rbf
 
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
 
 To start the User image:
     python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
@@ -146,7 +146,7 @@ Then program the .JIC file (unb2a_minimal.jic) to EPCS flash:
 
 (*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
      right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-     (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+     (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 
 
 7.
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index d06919a710843ba166221d78b5ce75b37da04d48..2254a2298d257ab714d64a3b62b713e11a834ce1 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb2a_minimal.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_minimal_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
index 3374b678b991559244f05d0b42f393cde9f1c345..1a90a0c0ba0563d793e70cd40c4e5f62c5644c6f 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/doc/README.txt b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
index ce1710cbd2aebe9cd61b66a764df3f084920776f..e386edeb682c11182862d6d44efafcbb96394e5d 100644
--- a/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2a_test (see the directories in ../
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
+   In the: $HDL_WORK/libraries/technology/ip_arria10_e3sge3
    directory; run the bash script: ./generate-all-ip.sh
    -> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
-      cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+      cd $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
       ./run_patch.sh
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_...) for each FPGA
+            Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2a/quartus/unb2a_test_...) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
 
     run_rbf unb2a --unb2_factory unb2a_test_[revision]
 
-The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_[revision]
+The .RBF file is now in $HDL_WORK/build/unb2a/quartus/unb2a_test_[revision]
 Now copy the .RBF file to the LCU host with 'scp'
 
 (b)
@@ -117,7 +117,7 @@ Program User image:
 Program Factory image:
     python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_test_[revision].rbf
 
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
 
 To start the User image:
     python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 
 (*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
      right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-     (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+     (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 
 
 7.
diff --git a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
index c0483d1585c6903e1a6ef07e604873f630100286..782190450d9a28a4b77e5e0dea3306609be1f0ca 100644
--- a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
@@ -19,7 +19,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 22976e6d86bea2e9b8fe53ef5d166601ae00d822..e1e4a6879c4aaf63ef9c35d30361f61345cfdd69 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -44,14 +44,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2a_test_10GbE.sdc
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_test_10GbE_pins.tcl
@@ -59,7 +59,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
index 7e83e4b07c8a8ecd7eae37b78eaf47d226a87dfd..f21f96082e771a5163c42a56316952d0194c5036 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index 2baa5dd51a0ad479ea5cc15519f5bd702740f8e3..20f578e03161a9639bcae078617c8f573412466c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_test_1GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
index 3374b678b991559244f05d0b42f393cde9f1c345..1a90a0c0ba0563d793e70cd40c4e5f62c5644c6f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index c0fe8620de3c10a9e101470d6829d8d73ed8aff2..b6728643131f9d08c13b64fc7af39ec2af45ef2d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -50,11 +50,11 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_sdc_files =
     quartus/unb2a_test_10GbE.sdc
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 quartus_tcl_files =
     quartus/unb2a_test_all_pins.tcl
@@ -62,7 +62,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
index 91f930b06b77c363b07479fb494161c03431cd09..48d76653cdaf6bc7229c63ad7b04ae5c1cee74d8 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
@@ -19,6 +19,6 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index 5886fa177c2ae9fa67c24c3f81e271a094f9a3cc..ae89579bba778a851e37cda5bd3e75182e4fa609 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -34,16 +34,16 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_I_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
index edf1e7422d1190e0e7b53dc03940471734b2bf3c..9eef78491c72c920c39a56ce64ddb275b2127b3d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index e15377b23d0e850669dfedb634769c2ab1640e00..b4c532fc7f16564da9fd0ea2de4e1dcfb9057152 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -34,16 +34,16 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
index edf1e7422d1190e0e7b53dc03940471734b2bf3c..9eef78491c72c920c39a56ce64ddb275b2127b3d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index fd9199ad99711573ad4fd40353e70e67f06ec4ff..3d19a04a358348790912930c7642f0aee0628ec2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -34,16 +34,16 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+    $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
 
 quartus_tcl_files =
     quartus/unb2a_test_ddr_MB_I_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+    $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
index edf1e7422d1190e0e7b53dc03940471734b2bf3c..9eef78491c72c920c39a56ce64ddb275b2127b3d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 2f6c0284ea27441c28ec06739627665859e87e86..012aacd3968f4cb21fdeeea3d80884ed1261f450 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2a_test_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-  -- $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
+  -- $HDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
   -----------------------------------------------------------------------------
   
     component qsys_unb2a_test is
diff --git a/boards/uniboard2a/doc/unb2a_release_notes.txt b/boards/uniboard2a/doc/unb2a_release_notes.txt
index 18a1851942d8120cc527dd467a50a9df6d12f9a8..4b8c0889c200971c87e101c74812ada4a97aebfe 100644
--- a/boards/uniboard2a/doc/unb2a_release_notes.txt
+++ b/boards/uniboard2a/doc/unb2a_release_notes.txt
@@ -10,15 +10,15 @@ Date: Tue Apr 26 11:25:24 CEST 2016
   This means that the firmware already flashed still shows a Uniboard 1 version in the python scripts.
   -> So it will be good to re-flash unb2a_minimal. 
   The new .rbf file (factory image) is added in the build directory and the excisting .jic file is removed.
-  Look at  $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt  Section 6b how to flash
-  Also see $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
+  Look at  $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt  Section 6b how to flash
+  Also see $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
 
 
 Date: Mon Apr 25 11:29:31 CEST 2016
 
 - Added functionality to write to EPCQ flash.
   Now it is possible to write a Factory- and User image
-  See $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+  See $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
   for instructions how to prepare images and how to write them in the flash
 - Added functionality to perform Load from Flash with the REMU (remote update)
 
@@ -32,15 +32,15 @@ In this directory the following designs can be found:
 - unb2a_minimal
   a minimal design which is also programmed in the onboard EPCS flash.
 
-  See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
-       $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+  See: $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
+       $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
 
 
 
 - unb2_test
   a test design with revisions testing each subsystem. Currently only the DDR4.
 
-  See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+  See: $HDL_WORK/boards/uniboard2a/designs/unb2a_test/doc/README.txt
 
 
 
@@ -49,7 +49,7 @@ In this directory the following designs can be found:
   an Altera reference design originally downloaded from
   www.alterawiki.com/wiki/High_Speed_Transceiver_Demo_Designs_For_Current_and_Older_Families
   
-  See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
+  See: $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
 
 
 
@@ -58,9 +58,9 @@ In this directory the following designs can be found:
   ddr4_micron46_mbIIskew
   based on Altera's reference design, autogenerated from the QSYS IP-catalog in Quartus
 
-  See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
-       $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
-       $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
+  See: $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
+       $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
+       $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
 
 
 
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
index b0c03d5eff46b363a242433100bb16c597aa2cb6..7b6403b3950993d0b329701a31c540600783cc08 100644
--- a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
 
 # new in Quartus 16.0:
 set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/doc/README b/boards/uniboard2b/designs/unb2b_arp_ping/doc/README
index eb5cae66ce7da505c28e903530687f401ab34072..0bb92470bef5795022c93b2cf141fbcb03af4c0e 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/doc/README
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/doc/README
@@ -5,19 +5,19 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
+   In the: $HDL_WORK/libraries/technology/ip_arria10
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 -> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
 
 -> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
 
 # 2. Generate MMM for QSYS:
 #     run_qsys unb2b unb2b_minimal
@@ -59,7 +59,7 @@ Synthesis
 - Open the unb2b_minumal quartus project from the build directory.
 - Open the qsys_unb2b_minimal.qsys file from the build directory.
 - Generate the HDL files for the qsys using the GUI.
-- "cd $RADIOHDL_WORK/build/unb2b/quartus/unb2b_minimal"
+- "cd $HDL_WORK/build/unb2b/quartus/unb2b_minimal"
 - "cp qsys_unb2b_minimal/qsys_unb2b_minimal* ."
 - "run_app unb2b unb2b_minimal use=gen2"
 - In Quartus, click the play button to compile the design.
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg b/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg
index fac36717d8499735875610e368a919446edb7c57..84065beb37d6c04a6b898c22742c8664f9c7ebe8 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
     quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     quartus/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl b/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl
index 7f9cb9420ae22e25a7b89c6c0d0bc20bbd787b35..f4f902325007674050bb4ab26adaab8b5dd0965b 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
index b2f7defb7b919f496224df583014d5a518879179..fa00229b73abc56eb5ab54f428ea0967f3786393 100644
--- a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
 ------------------------------------------------------------------
 
 -> In case of a new installation, the IP's have to be generated for Arria10.
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
+   In the: $HDL_WORK/libraries/technology/ip_arria10_e1sg
    directory; run the bash script: ./generate-all-ip.sh
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
 
 
 2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
 - right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+  (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index 9d8ad666907f428c808f9f26c63ddfb733b227c9..52b01f7dd24ff4b7c03202d99c575528393d5590 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     quartus/unb2b_heater_pins.tcl
@@ -34,31 +34,31 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
     
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
index 8201bf923e35a7c5fa2e76a0e58ce644e2e24f34..61b11c1c4c6880c4455d898a55bd5048a327ed2d 100644
--- a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
@@ -18,4 +18,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 ###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
index 72f15b0a7355071c4a5a74cf6d1de598c7acb6b3..dc01f1470182e33f393473bf917dc96820c9928c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
@@ -34,6 +34,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
 
 
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
index de64e7f039857c34c7c167c537c039e51f63e04c..a357b0ac5c8ffa6ef1463cbd2ebe4368caff8858 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
 
 
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
index 324205ffa195e1ea2ed9d019b1b02b9e267c5834..d4b0c462fc557de1074c6a6147c62b7b61267b45 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
 
 
diff --git a/boards/uniboard2b/designs/unb2b_minimal/doc/README b/boards/uniboard2b/designs/unb2b_minimal/doc/README
index cc12cf8fa0470d5e5882c4c8bd9d252739269fc3..c8fe1e8592a26f1f22c0fb375395720138fa2f5a 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/doc/README
+++ b/boards/uniboard2b/designs/unb2b_minimal/doc/README
@@ -11,7 +11,7 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
    generate_ip_libs unb2b
 
 -> For compilation it might be necessary to check the .vhd file:
-   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+   $HDL_WORK/libraries/technology/technology_select_pkg.vhd
 
 -> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
 
@@ -62,7 +62,7 @@ Synthesis
 - Open the unb2b_minumal quartus project from the build directory.
 - Open the qsys_unb2b_minimal.qsys file from the build directory.
 - Generate the HDL files for the qsys using the GUI.
-- "cd $RADIOHDL_WORK/build/unb2b/quartus/unb2b_minimal"
+- "cd $HDL_WORK/build/unb2b/quartus/unb2b_minimal"
 - "cp qsys_unb2b_minimal/qsys_unb2b_minimal* ."
 - "run_app unb2b unb2b_minimal use=gen2"
 - In Quartus, click the play button to compile the design.
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 24d3d4a0fa856f4ddc48a4d1bb8568daa7237ab9..d6d7154a939fa33b766bcf5f740590d4c1c9fae9 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     quartus/unb2b_minimal_pins.tcl
@@ -34,31 +34,31 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
index 7f9cb9420ae22e25a7b89c6c0d0bc20bbd787b35..f4f902325007674050bb4ab26adaab8b5dd0965b 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
index 87c0b0f7ef2fcca0f763c79bcc2638e713407e21..cf2059e4e1d639dacbab2eb62a3ef4e895b6de94 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
@@ -22,14 +22,14 @@ quartus_copy_files =
      ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2b_test_10GbE.sdc
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     ../../quartus/unb2b_minimal_pins.tcl
@@ -37,31 +37,31 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal_125m/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal_125m/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2b/designs/unb2b_test/doc/README.txt b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
index 31575a05f4f73a2f8f1fbb071b9fc92b8054415e..913f0b1333e5961dc5a41ed34db24376b242a233 100644
--- a/boards/uniboard2b/designs/unb2b_test/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2b_test (see the directories in ../
 
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
-   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
+   In the: $HDL_WORK/libraries/technology/ip_arria10_e1sg
    directory; run the bash script: ./generate-all-ip.sh
    -> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
-      cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
+      cd $HDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
       ./run_patch.sh
 
 
 
 1. Start with the Oneclick Commands:
-    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
-    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
+    python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+    python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
 
 
 2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_...) for each FPGA
+            Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2b/quartus/unb2b_test_...) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
 
     run_rbf unb2b --unb2_factory unb2b_test_[revision]
 
-The .RBF file is now in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_[revision]
+The .RBF file is now in $HDL_WORK/build/unb2b/quartus/unb2b_test_[revision]
 Now copy the .RBF file to the LCU host with 'scp'
 
 (b)
@@ -117,7 +117,7 @@ Program User image:
 Program Factory image:
     python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2b_test_[revision].rbf
 
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
 
 To start the User image:
     python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 
 (*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
      right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-     (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2b_board/quartus)
+     (in $HDL_WORK/boards/uniboard2/libraries/unb2b_board/quartus)
 
 
 7.
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
index 5269edaf0fd693245a55f2f84d03611f7048942a..b4d826aa22e05bbf0662484c0279b44640d750fc 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
@@ -19,7 +19,7 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
 
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
index cdaa8c7e78ccaf4d769d221ef8e076539d9866b4..0a7892e5bea4f33110784591d1ecfb858bec6594 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
@@ -45,14 +45,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2b_test_10GbE.sdc
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     quartus/unb2b_test_10GbE_pins.tcl
@@ -60,7 +60,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
index 7e83e4b07c8a8ecd7eae37b78eaf47d226a87dfd..f21f96082e771a5163c42a56316952d0194c5036 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
index c016fc4ec9b69ec7a190cc2e1facc56efc26b3ab..98a33faf400fd55678f66fb835d2cc35eaa9a55e 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
@@ -19,7 +19,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -30,70 +30,70 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/qsys_unb2b_test/qsys_unb2b_test.qip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/qsys_unb2b_test/qsys_unb2b_test.qip
 
 quartus_tcl_files =
     quartus/unb2b_test_ddr_MB_I_II_pins.tcl
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
index aeb8fe68eb623924631547feac91c3f4b6adc796..08edf304fe6a75e4efb3cdd99b92c523b182e113 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index fd2eb8444522bd7663aa95f1aa2caa6ac144037a..6b87cf4f530bd40cf9621cd6d9903eb712c8985b 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2b_test_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-  -- $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
+  -- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
   -----------------------------------------------------------------------------
   
     component qsys_unb2b_test is
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
index d9e35c4adaac2c6b54d33c8506d25733219adee2..7f9274079ac9011188310aea74cd94fded01db22 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
 
 # new in Quartus 16.0:
 set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
diff --git a/boards/uniboard2c/designs/unb2c_led/hdllib.cfg b/boards/uniboard2c/designs/unb2c_led/hdllib.cfg
index 4db139612d1a187acd92ee3b22fb8eb07862592d..5d047967376093325faf476189dbb12853c69ea8 100644
--- a/boards/uniboard2c/designs/unb2c_led/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_led/hdllib.cfg
@@ -19,10 +19,10 @@ synth_top_level_entity =
 quartus_copy_files =
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl
index ae417258f888c910d593c6ab6e5117615ebbd36f..62e37ddc54eb8d1cf28d5f50d376e0c80c4b97b6 100644
--- a/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt b/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
index 33bcfbb2bea24b1b243692647afb3352831b1516..3c7e4f13a71ca58fb6610a548957ccccbae1837d 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
@@ -14,8 +14,8 @@ Steps to go:
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
 
-     echo $RADIOHDL_BUILD_DIR         # should be something like /home/user/git/hdl/build
-     rm -r $RADIOHDL_BUILD_DIR/unb2c  # optional
+     echo $HDL_BUILD_DIR         # should be something like /home/user/git/hdl/build
+     rm -r $HDL_BUILD_DIR/unb2c  # optional
      compile_altera_simlibs unb2c
      generate_ip_libs unb2c
 
@@ -56,7 +56,7 @@ load the project now from the build directory.
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
+            Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
diff --git a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
index 2989dd33acad28ddc1d8ab0d7a5dfee2babd006b..97eb7c5537430b4fadb116a9c49e30f1362ebdb9 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
@@ -25,10 +25,10 @@ quartus_copy_files =
     quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_minimal_pins.tcl
@@ -36,29 +36,29 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
index ae417258f888c910d593c6ab6e5117615ebbd36f..62e37ddc54eb8d1cf28d5f50d376e0c80c4b97b6 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/doc/README.txt b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
index dc0de17d70dd756403477ee6653b1d3148289f9f..d05dc3625f520184080224d9a995e608d03edad0 100644
--- a/boards/uniboard2c/designs/unb2c_test/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
@@ -21,8 +21,8 @@ Steps to go:
 
 -> In case of a new installation, the IP's have to be generated for Arria10. 
 
-     echo $RADIOHDL_BUILD_DIR         # should be something like /home/user/git/hdl/build
-     rm -r $RADIOHDL_BUILD_DIR/unb2c  # optional
+     echo $HDL_BUILD_DIR         # should be something like /home/user/git/hdl/build
+     rm -r $HDL_BUILD_DIR/unb2c  # optional
      compile_altera_simlibs unb2c
      generate_ip_libs unb2c
 
@@ -67,7 +67,7 @@ load the project now from the build directory.
 ----------------
 Using JTAG: Start the Quartus GUI and open: tools->programmer.
             Then click auto-detect; (click 4x ok)
-            Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
+            Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
             Select the FPGA(s) which has to be programmed
             Click 'start'
 Using EPCS: See step 6 below.
@@ -93,7 +93,7 @@ For generating a Factory image .RBF file:
 
     run_rbf unb2c --unb2_factory unb2c_test_[revision]
 
-The .RBF file is now in $RADIOHDL_WORK/build/unb2c/quartus/unb2c_test_[revision]
+The .RBF file is now in $HDL_WORK/build/unb2c/quartus/unb2c_test_[revision]
 Now copy the .RBF file to the LCU host with 'scp'
 
 (b)
@@ -104,7 +104,7 @@ Program User image:
 Program Factory image:
     python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2c_test_[revision].rbf
 
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
 
 To start the User image:
     python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
@@ -138,7 +138,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 
 (*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
      right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-     (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2c_board/quartus)
+     (in $HDL_WORK/boards/uniboard2/libraries/unb2c_board/quartus)
 
 
 7.
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 9ef2e859c0b40381b7be2f658235b69743ad4207..2a380a453bd59f404fa56583cefe9278727e639c 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -46,14 +46,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2c_test_10GbE.sdc
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_test_10GbE_pins.tcl
@@ -61,72 +61,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl
index 23b93a5ba24914c770c2271751032099af2807d1..d0fd38cd8ad6e7e6685dae14cce15c05871c165f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
index 5e52adba61d3d532022099791d3595e85c91e66c..3ceaa62dc2af9dfa8ec6869fe74552499de9f199 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
@@ -26,13 +26,13 @@ quartus_copy_files =
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_pre_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_test_1GbE_I_pins.tcl
@@ -40,72 +40,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
index ae417258f888c910d593c6ab6e5117615ebbd36f..62e37ddc54eb8d1cf28d5f50d376e0c80c4b97b6 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
index cbeea04e78c6229e6df47973b2e8fd103c8ba85d..8a8afc0da544486bdaa15060119b4214cc60ec7a 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
@@ -26,13 +26,13 @@ quartus_copy_files =
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_pre_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_test_1GbE_II_pins.tcl
@@ -40,72 +40,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
index ae417258f888c910d593c6ab6e5117615ebbd36f..62e37ddc54eb8d1cf28d5f50d376e0c80c4b97b6 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
index e922d19d8950ad51c21407c22aa116d21a268f8b..6d3ea7c1f0f1889b8077bc97282c8c11b39ba696 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
@@ -32,14 +32,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2c_test_ddr.sdc
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_test_ddr_pins.tcl
@@ -47,72 +47,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
index e659f0faffad73a6e2a5757603a28ac1ffd82176..7411b8fb2fb9f7c56b1fe4e4586e47d4b623cf5f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg
index 05fda726d03ecaa75e70a78a485a8f8f63a8dcc3..a482d069257253a798fb284197b5de0cee7e160c 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg
@@ -48,72 +48,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr_16G/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr_16G/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
index fea6d6b87148f98902e699b2ad2468291d33d716..7f34f3c3e2f86ba15239d78f79a05d84cf637ff3 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
@@ -30,14 +30,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2c_test_heater.sdc
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_test_heater_pins.tcl
@@ -45,72 +45,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
index ae417258f888c910d593c6ab6e5117615ebbd36f..62e37ddc54eb8d1cf28d5f50d376e0c80c4b97b6 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
index 2e6ecb15828c5f04dbf13c536134b4ed36a24ae9..a6572309f87729bd77d3506f702d55e9d01cf40a 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
@@ -29,14 +29,14 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_pre_files =
     quartus/unb2c_test_jesd204b.sdc
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_test_jesd204b_pins.tcl
@@ -44,72 +44,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
index face7edbab0533e03b9f71a50811fa4417845901..1bf7adba9f95a9aa7d92c318cc12dd577c8a7b23 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
@@ -19,5 +19,5 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
index ebf094c08a24bdc31eb9c18e7bb52bacde00a331..58c95fbe7faf60bba98621717a1eb20843b39809 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
@@ -25,13 +25,13 @@ quartus_copy_files =
     ../../quartus .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
 
 quartus_sdc_pre_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+    $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
 
 quartus_tcl_files =
     quartus/unb2c_test_minimal_pins.tcl
@@ -39,72 +39,72 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/qsys_unb2c_test/qsys_unb2c_test.qip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/qsys_unb2c_test/qsys_unb2c_test.qip
 
 quartus_ip_files =
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+    $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
index ae417258f888c910d593c6ab6e5117615ebbd36f..62e37ddc54eb8d1cf28d5f50d376e0c80c4b97b6 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf b/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
index 2eae7412c73c7fb885a5b9af3ee264b8590772f1..b803224f2a724ea46882e6c51754ad1c6f28fd3b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+++ b/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
@@ -22,7 +22,7 @@
 # This QSF is sourced by other design QSF files.
 # ==============================================
 # Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
 
 # new in Quartus 16.0:
 set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
diff --git a/doc/erko_hdl_design_article.txt b/doc/erko_hdl_design_article.txt
index a1d25804418a727c6f4a7d6d870ea380037f3396..d3409551764d346aa5e6320af97b6b8e8cfe4d0c 100644
--- a/doc/erko_hdl_design_article.txt
+++ b/doc/erko_hdl_design_article.txt
@@ -1,7 +1,7 @@
 
 Reset : asynchronous or synchronous ?
 
-$RADIOHDL_WORK/applications/lofar2/doc/prestudy/
+$HDL_WORK/applications/lofar2/doc/prestudy/
 
 Ref:
  $RADIOHDL/tools/oneclick/doc/desp_firmware_dag_erko.txt
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 0ef7c01829d3a3d951b209419db85fe8621af460..b60d6352af82b88beb876c037f76562c963af792 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -54,12 +54,12 @@
 
 > . ./init_hdl.sh
 
-  * init_hdl.sh defines:
+  * inHDL_WORKines:
     - RADIOHDL_WORK directory for where the source code resides
-    - RADIOHDL_BUILD_DIR directory for where the targets will be build
-    - HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim for simulating with Modelsim using file IO
+    - HDL_BUILD_DIR directory for where the targets will be build
+    - HDL_IOFILE_SIM_DIR=${HDL_BUILD_DIR}/sim for simulating with Modelsim using file IO
 
-  * init_hdl.sh copies git user_components.ipx into Altera dir's
+  * init_hdHDL_WORKit user_components.ipx into Altera dir's
     - cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
 
   * init_hdl.sh automatically also sources ../radiohdl/init_radiohdl.sh if necessary
@@ -71,7 +71,7 @@ source also radiohdl tools
 
   * init_radiohdl.sh defines:
     - RADIOHDL_GEAR directory of where the init_radiohdl.sh is located
-    - RADIOHDL_BUILD_DIR = ${RADIOHDL_BUILD_DIR}/build if not already defined
+    - HDL_BUILD_DIR = ${HDL_BUILD_DIR}/build if not already defined
     - RADIOHDL_CONFIG = ${RADIOHDL_GEAR}/config if not already defined
 
   * init_radiohdl.sh extends:
@@ -198,7 +198,7 @@ sdp_firmware.py --host 10.99.0.250 -n 0:3 --write --image USER --file ../upe_gea
 sdp_rw.py --host 10.99.0.250 -r firmware_version
 sdp_firmware.py --host 10.99.0.250 -n 0:3 --reboot --image USER
 sdp_rw.py --host 10.99.0.250 -r firmware_version
-
+HDL_WORK
 
 *******************************************************************************
 * RadioHDL with SVN
@@ -838,7 +838,7 @@ When screen is started, it reads its configuration parameters from
 Screen settings according to our preferences using the .screenrc file.
 Here is a sample ~/.screenrc configuration with customized status line and few
  additional options:
-
+HDL_WORK
 ~/.screenrc
 # Turn off the welcome message
 startup_message off
@@ -850,11 +850,11 @@ vbell off
 defscrollback 10000
 
 # Customize the status line
-hardstatus alwayslastline
+hardHDL_WORKlastline
 hardstatus string '%{= kG}[ %{G}%H %{g}][%= %{= kw}%?%-Lw%?%{r}(%{W}%n*%f%t%?(%u)%?%{r})%{w}%?%+Lw%?%?%= %{g}][%{B} %m-%d %{W}%c %{g}]'
 Copy
 
-* uex in screen lijkt eerst niet op te starten,
+* ueHDL_WORKijkt eerst niet op te starten,
   matlab wel dus het ligt niet aan GUI, daarna lukts uex wel.
 * :kooistra@dop386:~/git/hdl>  --> in gewone terminal
 * ::kooistra@dop386:~/git/hdl> --> in screen terminal
diff --git a/doc/erko_radiohdl_article.txt b/doc/erko_radiohdl_article.txt
index 58b182f243ea6b85dd967e1df00f1145376b0f47..80e895d8c419cf4fc1d1a12e98faa6792cbdfb2c 100644
--- a/doc/erko_radiohdl_article.txt
+++ b/doc/erko_radiohdl_article.txt
@@ -57,7 +57,7 @@ Features:
 *******************************************************************************
 * Open issues:
 *******************************************************************************
-- Support more roots in RADIOHDL_WORK for searching HDL libraries 
+- Support more roots in HDL_WORK for searching HDL libraries 
 - Central HDL_IO_FILE_SIM_DIR = build/sim --> Project local sim dir
 - avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR
   copies the last <buildset>, using more than one buildset at a time gices conflicts.
@@ -145,7 +145,7 @@ are then used by the other libraries.
 * Simulation using file IO
 *******************************************************************************
 
-HDL_IOFILE_SIM_DIR is set to ${RADIOHDL_BUILD_DIR}/sim and defines where Modelsim simulation
+HDL_IOFILE_SIM_DIR is set to ${HDL_BUILD_DIR}/sim and defines where Modelsim simulation
                    will keep temporary file IO files.
 
 
diff --git a/hdl_user_components.ipx b/hdl_user_components.ipx
index 4823cbc15af5e791566def51860e88e74611825d..f9d2121fe9ee93f65aa8c5d42fceb1fd1f14dc87 100644
--- a/hdl_user_components.ipx
+++ b/hdl_user_components.ipx
@@ -6,5 +6,5 @@
  <!-- 0 in D:\svnroot\Uniboard\9.0 -->
  <!--  -->
  <!-- D:/svnroot/Uniboard/9.0 -->
- <path path="$RADIOHDL_WORK/libraries/**/*" />
+ <path path="$HDL_WORK/libraries/**/*" />
 </library>
diff --git a/init_hdl.sh b/init_hdl.sh
index a64c66de2f4dd00de2ea1d65ddd56f24443f9c90..6c72df6cdd5cf80d24b4e79f02f0182de24133d6 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -43,19 +43,19 @@ if [ -z "${ALTERA_DIR}" ]; then
 fi
 
 # Figure out where this script is located and set environment variables accordingly
-export RADIOHDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-echo "HDL environment will be setup for" $RADIOHDL_WORK
+export HDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+echo "HDL environment will be setup for" $HDL_WORK
 
 # setup paths to build and config dir if not already defined by the user.
-export ARGS_WORK=${RADIOHDL_WORK}
-export RADIOHDL_BUILD_DIR=${RADIOHDL_WORK}/build
-if [[ ! -d "${RADIOHDL_BUILD_DIR}" ]]; then
+export ARGS_WORK=${HDL_WORK}
+export HDL_BUILD_DIR=${HDL_WORK}/build
+if [[ ! -d "${HDL_BUILD_DIR}" ]]; then
     echo "make buil dir"
-    echo "${RADIOHDL_BUILD_DIR}"
-    mkdir "${RADIOHDL_BUILD_DIR}"
+    echo "${HDL_BUILD_DIR}"
+    mkdir "${HDL_BUILD_DIR}"
 fi
 # modelsim uses this sim dir for testing
-export HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim
+export HDL_IOFILE_SIM_DIR=${HDL_BUILD_DIR}/sim
 if [[ ! -d "${HDL_IOFILE_SIM_DIR}" ]]; then
     echo "make sim dir"
     echo "${HDL_IOFILE_SIM_DIR}"
@@ -71,12 +71,12 @@ fi
 for altera_dir in ${ALTERA_DIR}/*; do
     if [[ -d "${altera_dir}" ]] &&  [[ ! -h "${altera_dir}" ]]; then
         echo "copy git hdl_user_components.ipx to ${altera_dir}/ip/altera/user_components.ipx"
-        cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
+        cp ${HDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
     fi
 done
 
 # source also radiohdl and args tools
 . ../radiohdl/init_radiohdl.sh
-if [[ -d "${RADIOHDL_WORK}/../args" ]]; then
+if [[ -d "${HDL_WORK}/../args" ]]; then
     . ../args/init_args.sh
 fi
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index 81f4422437440dab0b384a21efbc319818696ad5..a5aa29dd847a6d1e7d10bfa45e04b7bd8a7366c0 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = 
 
 synth_files =
-    $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd
+    $HDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd
     src/vhdl/common_str_pkg.vhd
     src/vhdl/common_mem_pkg.vhd
     src/vhdl/common_field_pkg.vhd
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index cca9e1d6c59f63fdec3a256a14aac90d4d87515c..984cb4c6f568996b03762fb57d876291d4974c2c 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
     src/vhdl/mmm_unb1_dp_offload.vhd
     src/vhdl/unb1_dp_offload.vhd
 
@@ -26,8 +26,8 @@ quartus_copy_files =
     src/hex hex
 
 quartus_qsf_files = 
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
     
 quartus_tcl_files =
     quartus/unb1_dp_offload_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 5ec867ca066b2db19741171d7cf07c4b948cccd6..4dae8aaf5b0a36e222d57a27bafbac5ff5b5c32c 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -426,4 +426,4 @@ regression_test_vhdl =
 
 [quartus_project_file]
 quartus_copy_files =
-    $RADIOHDL_WORK/libraries/base/dp/quartus_unb2c  quartus_unb2c
+    $HDL_WORK/libraries/base/dp/quartus_unb2c  quartus_unb2c
diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index 724281760afb7b26b69150853ab1ca7d9f862780..5ca2d878af2ffa44d6ee9d79af58536e7993bb19 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -47,7 +47,7 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index e424ea9d5ff2530cbdd61574854fe100f054329f..a4ae352d909aedcfdca715dd100a334639b6cc2f 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
     src/vhdl/mmm_unb1_fn_bf.vhd
     src/vhdl/node_unb1_fn_bf.vhd    
     src/vhdl/unb1_fn_bf.vhd
@@ -24,14 +24,14 @@ synth_top_level_entity =
 quartus_copy_files = quartus/sopc_unb1_fn_bf.sopc .
 
 quartus_qsf_files =                                                       
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_fn_bf_constraints.tcl  
     quartus/unb1_fn_bf_pins.tcl
     
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index 04101e79bec296013ae70c6fb821b98e4a5babff..8e19ad708ffd36e01ea5eb231c04996538e13f45 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
+    $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
     src/vhdl/mmm_unb1_correlator.vhd
     src/vhdl/unb1_correlator.vhd
     
@@ -23,7 +23,7 @@ quartus_copy_files =
     quartus/qsys_unb1_correlator.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_correlator_pins.tcl
@@ -31,7 +31,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index 896a25a6ad54492a1512ac30d3c01c25dc1cd90b..63d1a25edcac752b2c30258deed171a48e825f76 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -266,7 +266,7 @@ BEGIN
     g_sim            => TRUE,
     g_pass_through   => FALSE,
     g_rec_not_play   => TRUE,
-    g_rec_play_file  => "$RADIOHDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
+    g_rec_play_file  => "$HDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
     g_record_invalid => FALSE
   )
   PORT MAP (
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 785430c6b0eed06f91fe6aa92a884cb690527afd..03e4b1cd5b7ea6e1c68a8bde1cf45e1951623cd7 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -26,7 +26,7 @@
 --   The g_data_file with input and expected output data is created by the
 --   Matlab script:
 --
---     $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+--     $HDL_WORK/applications/apertif/matlab/run_pfft.m
 --
 --   yields:
 --
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
index 6c155ee41d06019287272c604f1800f9e34fe903..dbc4808a25880cc600390cac8a22ec3053fd6113 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
@@ -22,7 +22,7 @@
 -- Purpose: Multi-testbench for fft_r2_par using file data
 -- Description:
 --   Verify fft_r2_par using and data generated by Matlab
---   $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+--   $HDL_WORK/applications/apertif/matlab/run_pfft.m
 --   
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index ba5514038feb271e308a479e1a4e1959f447af46..34a0dd394e0446cd68a748e63c2f0ca5cf3f5f56 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -22,7 +22,7 @@
 -- Purpose: Multi-testbench for fft_r2_pipe using file data
 -- Description:
 --   Verify fft_r2_pipe using and data generated by Matlab
---   $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+--   $HDL_WORK/applications/apertif/matlab/run_pfft.m
 --   
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index 9c2132abc6726e4f55a46d391649827f1d5fd1fb..bb9bd24684766b682f4dec4e1599618058ea6adc 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -23,8 +23,8 @@
 -- Description:
 --   Verify fft_r2_wide using and data generated by Matlab scripts:
 --
---   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
---   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft_complex.m
+--   - $HDL_WORK/applications/apertif/matlab/run_pfft.m
+--   - $HDL_WORK/applications/apertif/matlab/run_pfft_complex.m
 --
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/filter/src/python/diff_lofar_coefs b/libraries/dsp/filter/src/python/diff_lofar_coefs
index 529bf5381fb43b31da9a5dcc4768102bff4793a3..7b82cee17338eb5b8ce23e2e3ead0ea9ab174a02 100755
--- a/libraries/dsp/filter/src/python/diff_lofar_coefs
+++ b/libraries/dsp/filter/src/python/diff_lofar_coefs
@@ -31,81 +31,81 @@
 #   the subband statistics will not peak low to 0 dB.
 
 echo "1) Check that copies of LOFAR FIR coefficient reference files are equal"
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
 
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat 
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat 
 
 echo "2) Check that the local stored LOFAR FIR coefficients mif files are the same as in apertif_unb1_bn_filterbank"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-diff coefs_wide4_p1024_t16_0.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff coefs_wide4_p1024_t16_1.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff coefs_wide4_p1024_t16_2.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff coefs_wide4_p1024_t16_3.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff coefs_wide4_p1024_t16_4.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff coefs_wide4_p1024_t16_5.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff coefs_wide4_p1024_t16_6.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff coefs_wide4_p1024_t16_7.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff coefs_wide4_p1024_t16_8.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff coefs_wide4_p1024_t16_9.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff coefs_wide4_p1024_t16_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff coefs_wide4_p1024_t16_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff coefs_wide4_p1024_t16_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff coefs_wide4_p1024_t16_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff coefs_wide4_p1024_t16_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff coefs_wide4_p1024_t16_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff coefs_wide4_p1024_t16_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff coefs_wide4_p1024_t16_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff coefs_wide4_p1024_t16_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff coefs_wide4_p1024_t16_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff coefs_wide4_p1024_t16_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff coefs_wide4_p1024_t16_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff coefs_wide4_p1024_t16_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff coefs_wide4_p1024_t16_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff coefs_wide4_p1024_t16_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff coefs_wide4_p1024_t16_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff coefs_wide4_p1024_t16_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff coefs_wide4_p1024_t16_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff coefs_wide4_p1024_t16_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff coefs_wide4_p1024_t16_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff coefs_wide4_p1024_t16_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff coefs_wide4_p1024_t16_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff coefs_wide4_p1024_t16_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff coefs_wide4_p1024_t16_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff coefs_wide4_p1024_t16_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff coefs_wide4_p1024_t16_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff coefs_wide4_p1024_t16_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff coefs_wide4_p1024_t16_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff coefs_wide4_p1024_t16_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff coefs_wide4_p1024_t16_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff coefs_wide4_p1024_t16_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff coefs_wide4_p1024_t16_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff coefs_wide4_p1024_t16_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff coefs_wide4_p1024_t16_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff coefs_wide4_p1024_t16_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff coefs_wide4_p1024_t16_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff coefs_wide4_p1024_t16_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff coefs_wide4_p1024_t16_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff coefs_wide4_p1024_t16_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff coefs_wide4_p1024_t16_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff coefs_wide4_p1024_t16_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff coefs_wide4_p1024_t16_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff coefs_wide4_p1024_t16_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff coefs_wide4_p1024_t16_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff coefs_wide4_p1024_t16_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff coefs_wide4_p1024_t16_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff coefs_wide4_p1024_t16_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff coefs_wide4_p1024_t16_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff coefs_wide4_p1024_t16_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff coefs_wide4_p1024_t16_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff coefs_wide4_p1024_t16_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff coefs_wide4_p1024_t16_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff coefs_wide4_p1024_t16_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff coefs_wide4_p1024_t16_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $HDL_WORK/libraries/dsp/filter/src/hex
+diff coefs_wide4_p1024_t16_0.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff coefs_wide4_p1024_t16_1.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff coefs_wide4_p1024_t16_2.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff coefs_wide4_p1024_t16_3.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff coefs_wide4_p1024_t16_4.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff coefs_wide4_p1024_t16_5.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff coefs_wide4_p1024_t16_6.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff coefs_wide4_p1024_t16_7.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff coefs_wide4_p1024_t16_8.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff coefs_wide4_p1024_t16_9.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff coefs_wide4_p1024_t16_10.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff coefs_wide4_p1024_t16_11.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff coefs_wide4_p1024_t16_12.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff coefs_wide4_p1024_t16_13.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff coefs_wide4_p1024_t16_14.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff coefs_wide4_p1024_t16_15.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff coefs_wide4_p1024_t16_16.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff coefs_wide4_p1024_t16_17.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff coefs_wide4_p1024_t16_18.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff coefs_wide4_p1024_t16_19.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff coefs_wide4_p1024_t16_20.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff coefs_wide4_p1024_t16_21.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff coefs_wide4_p1024_t16_22.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff coefs_wide4_p1024_t16_23.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff coefs_wide4_p1024_t16_24.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff coefs_wide4_p1024_t16_25.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff coefs_wide4_p1024_t16_26.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff coefs_wide4_p1024_t16_27.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff coefs_wide4_p1024_t16_28.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff coefs_wide4_p1024_t16_29.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff coefs_wide4_p1024_t16_30.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff coefs_wide4_p1024_t16_31.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff coefs_wide4_p1024_t16_32.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff coefs_wide4_p1024_t16_33.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff coefs_wide4_p1024_t16_34.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff coefs_wide4_p1024_t16_35.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff coefs_wide4_p1024_t16_36.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff coefs_wide4_p1024_t16_37.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff coefs_wide4_p1024_t16_38.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff coefs_wide4_p1024_t16_39.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff coefs_wide4_p1024_t16_40.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff coefs_wide4_p1024_t16_41.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff coefs_wide4_p1024_t16_42.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff coefs_wide4_p1024_t16_43.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff coefs_wide4_p1024_t16_44.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff coefs_wide4_p1024_t16_45.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff coefs_wide4_p1024_t16_46.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff coefs_wide4_p1024_t16_47.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff coefs_wide4_p1024_t16_48.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff coefs_wide4_p1024_t16_49.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff coefs_wide4_p1024_t16_50.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff coefs_wide4_p1024_t16_51.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff coefs_wide4_p1024_t16_52.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff coefs_wide4_p1024_t16_53.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff coefs_wide4_p1024_t16_54.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff coefs_wide4_p1024_t16_55.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff coefs_wide4_p1024_t16_56.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff coefs_wide4_p1024_t16_57.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff coefs_wide4_p1024_t16_58.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff coefs_wide4_p1024_t16_59.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff coefs_wide4_p1024_t16_60.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff coefs_wide4_p1024_t16_61.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff coefs_wide4_p1024_t16_62.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff coefs_wide4_p1024_t16_63.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
 
 echo "3) Verify that the created reference LOFAR FIR coefficients mif files are equal to the local stored mif files"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+cd $HDL_WORK/libraries/dsp/filter/src/hex
 diff Coeffs16384Kaiser-quant_4wb_0.mif  coefs_wide4_p1024_t16_0.mif
 diff Coeffs16384Kaiser-quant_4wb_1.mif  coefs_wide4_p1024_t16_1.mif
 diff Coeffs16384Kaiser-quant_4wb_2.mif  coefs_wide4_p1024_t16_2.mif
@@ -172,142 +172,142 @@ diff Coeffs16384Kaiser-quant_4wb_62.mif coefs_wide4_p1024_t16_62.mif
 diff Coeffs16384Kaiser-quant_4wb_63.mif coefs_wide4_p1024_t16_63.mif
 
 echo "4) Verify that the created reference LOFAR FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant_4wb_0.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant_4wb_1.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant_4wb_2.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant_4wb_3.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant_4wb_4.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant_4wb_5.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant_4wb_6.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant_4wb_7.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant_4wb_8.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant_4wb_9.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $HDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant_4wb_0.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant_4wb_1.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant_4wb_2.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant_4wb_3.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant_4wb_4.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant_4wb_5.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant_4wb_6.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant_4wb_7.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant_4wb_8.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant_4wb_9.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant_4wb_10.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant_4wb_11.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant_4wb_12.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant_4wb_13.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant_4wb_14.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant_4wb_15.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant_4wb_16.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant_4wb_17.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant_4wb_18.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant_4wb_19.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant_4wb_20.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant_4wb_21.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant_4wb_22.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant_4wb_23.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant_4wb_24.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant_4wb_25.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant_4wb_26.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant_4wb_27.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant_4wb_28.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant_4wb_29.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant_4wb_30.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant_4wb_31.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant_4wb_32.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant_4wb_33.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant_4wb_34.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant_4wb_35.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant_4wb_36.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant_4wb_37.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant_4wb_38.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant_4wb_39.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant_4wb_40.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant_4wb_41.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant_4wb_42.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant_4wb_43.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant_4wb_44.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant_4wb_45.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant_4wb_46.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant_4wb_47.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant_4wb_48.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant_4wb_49.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant_4wb_50.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant_4wb_51.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant_4wb_52.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant_4wb_53.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant_4wb_54.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant_4wb_55.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant_4wb_56.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant_4wb_57.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant_4wb_58.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant_4wb_59.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant_4wb_60.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant_4wb_61.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant_4wb_62.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant_4wb_63.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
 
 
 echo "5) Verify that the created reference LOFAR No DC FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
 # To create the *.mif use recreate_pfir_mifs or directly use:
-# python $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif  $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
+# python $HDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+cd $HDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif  $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
 
 
 echo "6) Set script exit directory"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
diff --git a/libraries/dsp/filter/src/python/diff_pfir_coefs b/libraries/dsp/filter/src/python/diff_pfir_coefs
index 84b0765968753f3634d7cd4b6869324a5d76a793..55e74a18af4c3c6c00bd77c6a4e5b363059098ae 100755
--- a/libraries/dsp/filter/src/python/diff_pfir_coefs
+++ b/libraries/dsp/filter/src/python/diff_pfir_coefs
@@ -9,16 +9,16 @@
 #
 #   Expected result is that this diff_pfir_coefs script does not report diff's
 
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat                ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat          
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat                 ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat           
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat            ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat      
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat          
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat          
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat  
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat  
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat          ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat    
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat           ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat     
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat                ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat          
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat                 ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat           
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat            ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat      
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat          
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat                ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat          
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat  
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat        ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat  
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat  ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat          ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat    
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat           ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat     
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat      ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
diff --git a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
index 2b18c920e5b1e75750c46d6c2db88efc2c1af1d5..003a49c3def042efa653411138af07434b848c86 100644
--- a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+++ b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
@@ -43,10 +43,10 @@
    line argument and is only used to identify the input dat file.
    
    A pfir_coeff_*.dat file can be created using Matlab:
-   > $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coef.m
+   > $HDL_WORK/applications/apertif/matlab/run_pfir_coef.m
    
    The result is then (dependend on the actual settings in run_pfir_coef.m):
-   > $RADIOHDL_WORK/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
+   > $HDL_WORK/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
    
    This coefficients dat file needs to be copied to the local ../hex directory,
    because both the dat and the MIF files sare used in the VHDL testbenches.
diff --git a/libraries/dsp/filter/src/python/recreate_4wb_mifs b/libraries/dsp/filter/src/python/recreate_4wb_mifs
index f285a59c2bb0720165df5d1c104e5f8ae3922243..80899c648dcb131f9a3b44cb3248dbd39714ed1b 100755
--- a/libraries/dsp/filter/src/python/recreate_4wb_mifs
+++ b/libraries/dsp/filter/src/python/recreate_4wb_mifs
@@ -2,7 +2,7 @@
 #find . -name "*4wb_0.mif" - print
 
 # It appears they only are created in the filter library:
-#cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex/
+#cd $HDL_WORK/libraries/dsp/filter/src/hex/
 #ll *4wb_0.mif
 # yields:
 #    run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b_4wb_0.mif
@@ -23,7 +23,7 @@
 # any Python scripts that Hajee made to access the FIR coefficients in apertif_unb1_bn_filterbank
 # will still also work for wpfb_unit_dev.
 
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
 
 python fil_ppf_create_mifs.py -f ../hex/run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b.dat           -t 16 -p   32 -w 4 -c 16
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat         -t 15 -p  128 -w 4 -c 16
diff --git a/libraries/dsp/filter/src/python/recreate_pfir_mifs b/libraries/dsp/filter/src/python/recreate_pfir_mifs
index 05bcc11aa0bb3e6690b3cfa32c32ce2993e36585..2cda88e4e3eabc9c0a88d8978516a7637585fed5 100755
--- a/libraries/dsp/filter/src/python/recreate_pfir_mifs
+++ b/libraries/dsp/filter/src/python/recreate_pfir_mifs
@@ -17,7 +17,7 @@
 #   > svn status -q ../hex
 #
 
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
 
 # run_pfir.m
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat          -t 15 -p  128 -w 4 -c 16
@@ -37,9 +37,9 @@ python fil_ppf_create_mifs.py -f ../hex/run_pfb_complex_m_pfir_coeff_fircls1_16t
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat              -t 16 -p 1024 -w 4 -c 16
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat        -t 16 -p 1024 -w 4 -c 16
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat        -t 16 -p 1024 -w 4 -c 16
-python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
 
-python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
                                                                                 
 # run_pfir_coeff.m : channel filterbank (wb = 1)
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat                  -t  8 -p   64 -w 1 -c 16
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index 11a108d75c59d6afb1af7f1490c1a6b88c46b627..73c91c43ee66d4467ece66e24267d25f86903e04 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -68,11 +68,11 @@
 --
 --   The reference dat file is generated by the Matlab program:
 --
---     $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coeff.m
+--     $HDL_WORK/applications/apertif/matlab/run_pfir_coeff.m
 --
 --   The MIF files are generated by the Python script:
 --
---     $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+--     $HDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
 --
 --   The reference dat file and the MIF files use the same g_coefs_file_prefix.
 --   For the reference dat file this prefix is expanded by nof_taps, nof_bands
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index c56ad139456fca352a11729aafb6b2b6254b18bf..819536b860dc015f3cc8864a9cc781f1eec41d5f 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -29,7 +29,7 @@
 --   The g_coefs_file_prefix dat-file and g_data_file dat-file are created by
 --   the Matlab script:
 --
---     $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
+--     $HDL_WORK/applications/apertif/matlab/run_pfir.m
 --
 --   yields:
 --
@@ -51,7 +51,7 @@
 --   The MIF files are generated from the g_coefs_file_prefix dat-file by
 --   the Python script:
 --
---     $RADIOHDL_WORK/libraries/dsp/filter/src/python/
+--     $HDL_WORK/libraries/dsp/filter/src/python/
 --      python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 1 -c 16
 --      python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 4 -c 16
 --
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
index 68d13225235664348fd416716f9517c83147c72e..8d35654818be45697c91908302665fca08663399 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
@@ -22,7 +22,7 @@
 -- Purpose: Multi-testbench for fil_ppf_wide using file data
 -- Description:
 --   Verify fil_ppf_wide using coefficients and data generated by
---   Matlab $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
+--   Matlab $HDL_WORK/applications/apertif/matlab/run_pfir.m
 --   
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/verify_pfb/hdllib.cfg b/libraries/dsp/verify_pfb/hdllib.cfg
index 66bab97861d9fda3ffde307fe8c3488c1245e710..30d4c61348cecf40c3622b34422d25c5ff726dd2 100644
--- a/libraries/dsp/verify_pfb/hdllib.cfg
+++ b/libraries/dsp/verify_pfb/hdllib.cfg
@@ -21,14 +21,14 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-    # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../
+    # Note: path $HDL_WORK is equivalent to relative path ../../../
     ../../base/diag/src/data   data  # WG
     # APERTIF wpfb
     ../filter/src/hex    data   # PFIR filter coefficients
     ../wpfb/tb/data      data
     # LOFAR1 pfs + pft2
-    $RADIOHDL_WORK/applications/lofar1/RSP/pfs/src/data data    # FIR filter coefficients
-    $RADIOHDL_WORK/applications/lofar1/RSP/pft2/src/data data   # FFT twiddle factors
+    $HDL_WORK/applications/lofar1/RSP/pfs/src/data data    # FIR filter coefficients
+    $HDL_WORK/applications/lofar1/RSP/pft2/src/data data   # FFT twiddle factors
 
 [quartus_project_file]
 
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
index 1d46215a1a3ab228128cffe664a713fd3a7a2727..24c2ae21fd4697d6b734d0339e8b73fa30dfe539 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
@@ -3522,19 +3522,19 @@ cd /dop466_0/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/apertif/m
   --> run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_16b.dat
   --> run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_18b.dat
 
-cp data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_fircls1_16taps_1024points_18b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_18b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_18b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_fircls1_16taps_1024points_18b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_18b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_18b.dat $HDL_WORK/libraries/dsp/filter/src/hex
 
 cd /dop466_0/kooistra/git/hdl
 . ./init_hdl.sh
 cd /dop466_0/kooistra/git/upe_gear
 . ./init_upe.sh
 
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
 
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat -t 16 -p 1024 -w 1 -c 16
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_18b.dat -t 16 -p 1024 -w 1 -c 18
@@ -3545,8 +3545,8 @@ python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_1
 
 11 jan 2021: Create FIR bypass coefficients for LOFAR PFB:
 cd /dop466_0/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/apertif/matlab
-cp data/run_pfir_coeff_m_bypass_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cp data/run_pfir_coeff_m_bypass_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cd $HDL_WORK/libraries/dsp/filter/src/python
 python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_bypass_16taps_1024points_16b.dat -t 16 -p 1024 -w 1 -c 16
 ll ../hex/run_pfir_coeff_m_bypass_16taps_1024points_16b*
 -rw-r--r-- 1 kooistra kooistra 18236 Jan 11 16:35 ../hex/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb_0.mif
diff --git a/libraries/dsp/wpfb/hdllib.cfg b/libraries/dsp/wpfb/hdllib.cfg
index 52de82f92c3db94b347fb636c2b15fa35f4b699f..a604bf3dc6ca801753be52cc9717318540ec1efd 100644
--- a/libraries/dsp/wpfb/hdllib.cfg
+++ b/libraries/dsp/wpfb/hdllib.cfg
@@ -23,14 +23,14 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-    # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../
+    # Note: path $HDL_WORK is equivalent to relative path ../../../
     modelsim/wave_tb_mmf_wpfb_unit.do     .
     ../filter/src/hex                     data
     tb/data                               data
     ../../base/diag/src/data              data    # WG
     # LOFAR1 pfs + pft2
-    $RADIOHDL_WORK/applications/lofar1/RSP/pfs/src/data data    # FIR filter coefficients
-    $RADIOHDL_WORK/applications/lofar1/RSP/pft2/src/data data   # Twiddle factors
+    $HDL_WORK/applications/lofar1/RSP/pfs/src/data data    # FIR filter coefficients
+    $HDL_WORK/applications/lofar1/RSP/pft2/src/data data   # Twiddle factors
 
 [quartus_project_file]
 
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
index c76e25a5c80ea78416b0292cabbc09bb31d4601b..4b681cf63c11cc43337bf5c237cad8b32763f3ee 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
@@ -23,8 +23,8 @@
 -- Description:
 --   Verify wpfb_unit_wide using and data generated by Matlab scripts:
 --
---   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
---   - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
+--   - $HDL_WORK/applications/apertif/matlab/run_pfb.m
+--   - $HDL_WORK/applications/apertif/matlab/run_pfb_complex.m
 --
 -- Usage:
 --   > as 4
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index caa83e1592b49ac73aadcebf2c52fc65a1d80159..15516c1b90a06fcdfae05dccf9f4f9404b3ace35 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -25,8 +25,8 @@
 -- Description:
 --   This tb uses the Matlab stimuli and expected results obtained with:
 --
---   $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
---   $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
+--   $HDL_WORK/applications/apertif/matlab/run_pfb.m
+--   $HDL_WORK/applications/apertif/matlab/run_pfb_complex.m
 --
 --   For more description see:
 --   . tb_fil_ppf_wide_file_data.vhd
diff --git a/libraries/io/ddr/hdllib.cfg b/libraries/io/ddr/hdllib.cfg
index 5855c3eb57edb5ad056e465440dfc3c22ee1503e..8bb8fa2a509c1298653e8d937fca1f57a27d32b7 100644
--- a/libraries/io/ddr/hdllib.cfg
+++ b/libraries/io/ddr/hdllib.cfg
@@ -23,11 +23,11 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl  # 4GB DDR3 model
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl               # 4GB DDR4 model
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl          # Unb2b 4GB DDR4 driver
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl          # Unb2b 8GB DDR4 driver
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl          # Unb2c 8GB DDR4 driver
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl  # 4GB DDR3 model
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl               # 4GB DDR4 model
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl          # Unb2b 4GB DDR4 driver
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl          # Unb2b 8GB DDR4 driver
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl          # Unb2c 8GB DDR4 driver
 
 
 [quartus_project_file]
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index fddc99e9c4871d33aa29a5f3d6e20bec8bca5a54..22aced656c14ddb13743075eaf201b8420387042 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,13 +28,13 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
-    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
-    $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+    $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
 
 modelsim_compile_ip_files =
-     $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-     #$RADIOHDL_WORK/libraries/io/ddr3/src/tcl/compile_ip.tcl
+     $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+     #$HDL_WORK/libraries/io/ddr3/src/tcl/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index aaca3d6c3c297d021b996ec3ac83b6c7d366c6be..a45392e234e98478c7c185e2fdab4c8b6252cb18 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
 
   CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);  
   
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (
diff --git a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
index a090ba6f04d48dfe58337b270c1ba2f97924e5e1..fe613ff4ae6c0f8dffdfa7d93cf9a656d10981f5 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
+++ b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
@@ -21,15 +21,15 @@ synth_top_level_entity =
 quartus_copy_files = quartus/qsys_unb1_eth_10g.qsys .  
 
 quartus_qsf_files = 
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_eth_10g_pins.tcl
     
-quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
 
 quartus_sdc_files =
-    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index 39fcfc924d6665a6a0352057d1689ac17fb4937a..ef29caf98d50561a9867acc8475e4682deb03264 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -58,10 +58,10 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
-    src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+    src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 [quartus_project_file]
 quartus_copy_files =
-    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
-    src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+    src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 5c3918e3df7432b2df1aed3160ad926036667211..dd866335787f732b23f24ddb8d2acf7483e243eb 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
   
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
   PORT (
     pll_ref_clk                	: IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
   PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
   COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e3sge3
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e1sg
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -604,7 +604,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index ebbb325b5f1d9bcd5e6c1e9d2a636582b02596b6..5d89d1ff0aebd6353c714686132a00689342b917 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
   ------------------------------------------------------------------------------
   
   -- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
-  -- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+  -- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
  
   COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
   GENERIC (
@@ -86,7 +86,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
   ------------------------------------------------------------------------------
   
   -- Manually derived VHDL entity from ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd in:
-  -- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
+  -- $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
   COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq IS
 	PORT (
 		mem_ck      : in    std_logic_vector(0 downto 0)  := (others => '0'); -- mem_conduit_end.mem_ck
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index 09ec26b81ae0122136ebdc626accce7595a535c4..02e4adb554aec475da941a60d7c76bd2fd9e58b9 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
 
 synth_files =
     technology_pkg.vhd
-    $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 
 test_bench_files =
 
@@ -16,10 +16,10 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 
 
 
 [quartus_project_file]
 quartus_copy_files =
-    technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index 44f305f0b19f6ef32390f5eeb7759da1d56089b6..5e5795ffacb7327cc1fb4ee1c912613d8e7685ea 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index 102fa8aac0ac209cbf88c0c064ea56ce7b698256..f3f1864993b8f4c18f939a5939cb80f1a5ff0fe5 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/complex_mult/README.txt b/libraries/technology/ip_arria10/complex_mult/README.txt
index c9a33bbdfc0710640b0f4e967376ce8a5627e40e..2e863c2d4bc14d7e9cd91d360150bfc69e948cda 100644
--- a/libraries/technology/ip_arria10/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 55e6320c95cadb8c1e631eb0410f1f2a1e1a8c01..43acb41dbef0fb27a4faaabf1a7ba7b8f4b8cab6 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index 962d1268caa23270815d53c69e3a8a9bc9abf2bb..3dd7b59b6710a4c9e813d8db06c36fa04cb5010d 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddio/README.txt b/libraries/technology/ip_arria10/ddio/README.txt
index 1823e822ffac72fd6dfccb16917ab9972bed2a75..7ea3cfffa4c932d75e3ec2d52c01d41e8b1fc5ad 100755
--- a/libraries/technology/ip_arria10/ddio/README.txt
+++ b/libraries/technology/ip_arria10/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index ea28f210cf233f23315cc1a15bb5e51d5a893a41..5b113d828257fe40f688b3669895b2b57fbd17da 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} {
 
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
+    set IP_DIR "$env(HDL_BUILD_DIR)/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_150  ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
 } else {
 
     # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
-    set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/sim/"
+    set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10/ddio/sim/"
     
     vcom "$SIM_DIR/ip_arria10_ddio_in_1.vhd"
     vcom "$SIM_DIR/ip_arria10_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index 79383ba97bf08f642c78a955cea688ea13047174..312ee40a8f53ba2fc3c9804752891c496627e3f2 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/ddio/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 3e5f93390f573a7c8bd58ac855451a4e7b25d748..92b736708c5f397f2669fcabf33f23930c10c4fb 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index b83177faa5b1cb8f7914cb1aa5a44381e85bac22..fca54fa81397d5fe2fed6c83f43174c445ec9dc3 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index d6d5dd48ae0a9eab63eb23186b74e24c96c9e4ed..64e5fd4f764d3fafa0677451c686e5e0a410d29d 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index fb90cea0b32e3e6c69cbfa4a139c5aedb996f4ba..ec106dc119f0b937632a4dc67aff6a1c8d679b91 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index 0126c5c44fc2f14013aa65c8faba90359ffef766..e0de434cf68a2b36abac305aa1295db9bf676ed6 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index 558f712cc221547a469ef2c8f0431ab9b44a2fad..08ffba7d5dd990bbb1eff8e50909b546886d9b78 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index 297be0f53261b7a31f47ff06a12584e606729f1c..748f3779e18a424294a431e7b32a6f6b27d11bf9 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index 7987c4b82e1ccf4ae922a03fb5720433a2e5a129..dca56d5c3c797d693a1497ee635df4ba72270577 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 1687d60fabd5619c6ebdb3e158bdc9233d646d35..c39af9c022dcb8e20e4ebaa036885b2fb374668c 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
index 4921c9d617ae8bda0524b60e8a2633082c6931a2..910c06603239a87453b5dfa728fe917216a5c2b2 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
 
 1) DDR4 memory simulation model
 2) Automated scripts and one time manual actions
@@ -11,7 +11,7 @@ README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
 The DDR memory model is obtained from the example design that can be generated with Qsys when a DDR IP component is defined.
 The first DDR4 component that was created is available via:
 
-  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
+  $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
 
 Unfortunately the example design needs to be created via the GUI by pressing the 'Example Design...' button, because the qsys-generate command
 that is used in ddr4_4g_1600/generate_ip.sh to create the component does not have an option to also create the example design. After that the
@@ -21,20 +21,20 @@ memory model have been copied to a fixed location in SVN. In this way it is no l
 
 In the example design for ddr4_4g_1600 the generic core files of the DDR model are located at:
 
-  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
+  $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
 
 The size specific entity of the DDR model is created in:
 
-  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+  $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
 
 The generic core files of the DDR memory model are the same for every DDR size. These files only depend on the Quartus tool version as indicated by 141
 (Quartus 14.1) in their name. Therefore the generic core files have been copied to:
 
-  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
+  $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
 
 The size specific DDR component file is copied to:
 
-  $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+  $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
   
 and other size DDR component files can be store there as well.
 
@@ -49,7 +49,7 @@ but it is good to manually check with Linux 'diff' as in diff_mem_model.sh that
 
 2) Automated scripts and one time manual actions
 
-Relative to $RADIOHDL_WORK/libraries/technology/ip_arria10/:
+Relative to $HDL_WORK/libraries/technology/ip_arria10/:
 
 - ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys : Qsys definition file for size and speed specific DDR4 controller
 - ddr4_4g_1600/generate_ip.sh               : Use qsys-generate to create the size and speed specific DDR4 controller
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
index 94d8e8d0c54deb3d953c9755d69035224bb106ed..821fd74386176873cf6f7a1a9ace05f2a08c582f 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
@@ -20,9 +20,9 @@
 #
 #------------------------------------------------------------------------------
 
-# This file is based on Qsys-generated file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
+# This file is based on Qsys-generated file $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
 # 
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141"
+set IP_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141"
 
 # Assume library work already exists
 vmap ed_sim_altera_emif_mem_model_core_ddr4_141 ./work/
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
index bd39700d7f2aafbd6471f4e1a67d27461681c523..68e362d61e8b7d6e8ff9cd4ef69f8370598a0eb8 100755
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
@@ -31,7 +31,7 @@
 #
 #   eg:
 #
-#   ./diff_mem_model.sh $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
+#   ./diff_mem_model.sh $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
 #
 
 EXAMPLE_DESIGN_DIR=${1}
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
index bdd0226b2496dfdc4ee354d1d3a436e73ad11878..40a46f994f928dfa379f8aa7f3ae05ccd745bac7 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
index 6db25b6412e89ebde6decb09c13f7e14890315b0..bcf8b55de24242e455a4481c6c64b948f0d04797 100755
--- a/libraries/technology/ip_arria10/fifo/README.txt
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index 32237451dc2c302dfa68b638e5fb4c47de711e66..7ad84ee07bff1ab5473c734fc53609797e73dec8 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
 
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index a9fea8a6d5126608839e13ef938e3796fa2e82b4..2cb9e180fa245e4936faf756687c4aff8f395833 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index bd002e349294ad0e46ca0d6166e1e395cb9f5213..46836c839335b0c1a9a26c7f65d7bd45452a9657 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 vmap ip_arria10_remote_update_altera_remote_update_core_150  ./work/
 vmap ip_arria10_remote_update_altera_remote_update_150       ./work/
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index 32cacf3e6b3bb947f5dfa6fc67d9f72d6584545f..19f16cd59f45a498f1f347959d497eea6b7cd5a6 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 851350a43c6ceabe3919511133fe33ecbaa440b8..80a62c66728cbf85d97b24a84daed153673028b7 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index f413ae490ea9623608adbb9260f991cb125cb117..1fad6fdf3e4d79a70a360171d82eac2ded6bb8bc 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 48d30f0d8919ce779bf57581ade5ba02a20a5242..8d2f641fcc8860bd127d95f956d2d36c11d49292 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 1f2b25388914d39d7d2c0486ea5f93ada251af38..fc70aa70a00928b813293643fcb3f9a6e174e2d8 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/mac_10g/README.txt b/libraries/technology/ip_arria10/mac_10g/README.txt
index c775402d02b409cbc5f046ee91549577ddf8c52a..0f920fa60eb1bb158995b720f14582422039bcec 100644
--- a/libraries/technology/ip_arria10/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index a8883cc13242d13d7bc792f260482f06265a8b70..1865ab2bb04acaf84406cb094a18d831a8c38a89 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
-set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index 6a1b1dd972a06c768520590e73255fa3830b7b84..7c805fde975a1b02cace9f340042a682ba409af6 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
index 464263f96b1dc6127b43eaa84d9440869022c315..abd378c32926a532ff549a61e9201a405c7319b1 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index 794ca94e334b853ceac9fcdbd9c00627f740e324..05fdc5ebb71331a4d596bfed14fbfb75e1abe958 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index dc9cdc38dd58ba6d12a5f4c992fd4ac58860dd2f..52a125e4fe15954d70ef24d4f874415ebaf37579 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index f40fb259020f09cd98abb04e913637bf5dcc2099..4df7738bdcbbb9259a5ad46048c80e97ed3fa5b6 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index 574c29ca06bc1e882bad82ee4c5f757b3b0352f6..13f8d55b36903a35f43daf343d0b2f9e4a895026 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index 182a93de25363bf55ff70897678dabe73007b3e8..5ef95c261f33071aa5333527bd61316d970b3c45 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index 7aa111c072e30c79be6f672dae7d9af8723b0ad9..ff54a5ae25861bc3b98c8f4b23ad317edb600446 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index 740989b1157c49f8004d0af278671c8d27f7e628..4df2e0bdecb96b8ef473082f28af7a7b09c5bf41 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index 6438682b22c6a49d814176ab71d0968518c8daba..8a8e3288b3c9092ceb8f5fa0f3fa714af4325c07 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 2cf8040b19ec0dd8b4cbc9453bec69898deaa865..53e06e4de13144c7d5f04c48b2a3668b4b0b3ab3 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index d280316c1bd341663c279b03e817751788409eb4..81b716642904ab48606f4af1eb033b94524dd55a 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index e66921e0b330ede9a74a01ad878abc7446256f22..ca650eea03c441dd28c7d1db95fe5858d2e1b2b9 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index b6b6d86efd6e6d11947dafbbe66f1e17ec5dc36f..19d0725eca41854f382871c3466f8c3692a0db8e 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index 9a1b5855e11f4642ceeaf023fb66cd9a8e04fb01..88558ac77859eb3864cb9657e3f8c21539db39b1 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index c3b7fa01be56d79d4a118130f428532ce0100e25..24e8de5690eb887f4543074b33f6e70895cf6142 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index 58312af4c266a64f2cd82253ff649fd40604440c..65f55bd48db30500ebe48bf5dc93e019d032d020 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index 3a1a86267ad5ef185233f4727447e4ed23fafb95..87db4a4444bec3e8739540078cade2d292ee5215 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index d31c8671a798c3899e189cbc4f0d354d1543cd3f..20e438b4c19e1e7c1aca450ab6bc3e439f4c0d49 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index 7fb31eb197dcae6f23a2ffcb726990a76db3eb0a..0727a293418c1605beb867447a83d2a6fa371fb0 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ram/README.txt b/libraries/technology/ip_arria10/ram/README.txt
index 24ad4ab94e542bd2d642eaa079f4e18624d8c163..bb10b060478b5b615634aedfea779ac31cbf3845 100755
--- a/libraries/technology/ip_arria10/ram/README.txt
+++ b/libraries/technology/ip_arria10/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index 6404a59d660ea18074ae67b68286650006d74aa0..e24b47eab8f26f11b277087e52befb7ed06a3160 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 7712a5afed2dcd740381c1f2dc839598a742e8ed..42636b22f56dcd1d6e6439155629240c91648828 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 950a6849abb5d59accb772d44b93e8a962de330c..0ca0862832784bf6d305b2a30503b0e76fd964ee 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index ab125a22db26bb1d563ea3d2274aff56b83b9026..d0e4500787881fdbe1c402b32070bfd5d5316970 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index 0b48cda572c2a91c92702b6908cd6530a72d1d3a..ede7525a7c82aea577cfeb7fb9f0a8aba1d026b8 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 45b9e866eae9942cf3067f8354e1afb0e98770d2..e4ca47ead5e5a0c96792d4400f588e14c29204ef 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index 0b9fd32f8156d0df118951b96bc7c0681f8740de..7e487453a1f8d57295d9203d6868e04cc2895739 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index 8cb43574cbfe737753d50b05a3c84c40e9737e5d..fed5346f932671d2f0f6e84a38b2fe721e2f989a 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index a98ab3b9500f226f4dadf17ce07fd14fe87ca004..4b2d7cd58b179c78354392060a21f5d418fd7e4f 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index 02bdc47594ad88707371e661ab1b51ca9eb77a90..2cee6ec36d4567a9e81f63d1ca68103854ccff2d 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 8f4d76ddf3b165426aa469b62198d437460441a8..2adc9e61a6b8385bc9d5604eeaa9ec630c71e2ef 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index e2f5fe2620de365fe520ca0d5de24f117305495a..789b6203dbd223217e08f0817e3a4f6dfa435080 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index a4a6db128f22937079b2c51574d5f89130519edf..89dc59e26a28cf196eee9369a1512982901dc64f 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index 9e5de0cc3ee075243e0c11f59caddaf215236116..22b2c4dba3500cc499b6301bb3f2cd4f87f1b4a8 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
index fa105db173e0dc963f59b1e10b143cf5cc782167..8b2022353701472bac9f6210d3711db0e1f06574 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
 
 The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
 
 The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
 
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index 3f4f14a00e3d83e3c7df35ee5d745895e54b6f4e..97a8f992de1d36397fcd1fb8d80bbec7c3e8806a 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index f4b67edbe25a7ec4e13713480126b85b45a7aa1a..640aca230599c092013b0a507ccfc1615b38565c 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
     
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
index ae9545e000d01218915aa99cdf67e00146add477..0f0e3a326637b6afb5166ca429c719d69136ae75 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
 
 Contents:
 1) Porting
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index a22e115699c0346b81882fc18f14b319b1de139f..a9062836f7bbd80f60938f94448f21f763016b54 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index a9294f7aa9bf5704a24bcfda2c8824ce78627957..2a6caff441563d95a9b4c48e07b1c791b085000b 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index fd90e1ac9c90092e50f26c10a30467166ed8cad4..03e7c495f2853b87e59a0b396d86a7b86da4b0db 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index bd24313b8416514d4deb34db07a2f44fe9c2d7bf..dadb8b1d8d2eae5a4af282ac11bf375cb9150d3a 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 [modelsim_project_file]
 # There is no simulation model for the FPGA voltage sensor IP
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
index ffa123ac217c86efde7d6de9ab386fa0714560c8..d2c1cac94d7a915467598e00158b226912f78133 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
 
 vmap alt_em10g32_180 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
index 62619e221dc75d4ca1d7cb15e2757190ce02eba6..908a9e55be9f71e2b0e09ac56a1b282d494c5a9b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
index 564cbf1d9c3f4b62d7fadea5308fa980386646df..48b8eadb18ffe222be00011f1a9d45c2e88cd8a9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  alt_mem_if_jtag_master_180            ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg
index 21f6ab7cfc4cffde8b55b9d3ca430d1bcad81d5b..af862f267bb056c41c2d12d0e033a30076e9b74e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
index b8ff2a3d814ebf9bb58af5ffc17637361cd6eae9..0fdc6a880e087a7f252a0ffa7071d286d0bdc84f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
 
 vmap altclkctrl_180 ./work/
   vcom  "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_uuznxiq.vhd" -work altclkctrl_180                                           
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg
index d16da4aa988dfc2369d7c330401fcc33f33b53b9..867cff8d22706bf22bb732d0570357a5785933f6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
index e1847b95f20bbae0aeccb8b696cbc90929c3e893..d6b2ba13b801ab542ffb812499cd045bcd976b4a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
 
 vmap altera_asmi_parallel_180 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg
index 6a653a16896034a3253bb38ef3bab954c82c9e07..50a05632b52a3f1aaf2ec38244c714ddf7d00fcb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
index eafa959867e1a4c01ae8e165643abd814f48bbb5..af0c7159fd9aeb9898dd708d829011e65639f3e7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
 vmap  altera_avalon_mm_bridge_180         ./work/                       
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg
index 97f5b33a724769d4ddab878d345300ced1ec6cf7..7b00cb0add776df427ffd1b9100b8fdbe99900bd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$HDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
index 25d72fb06ab3e3840de87530222a59396bf54d70..edf94714dd03299d19c6edb8b7e661399c6246a8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
@@ -30,16 +30,16 @@
 #
 vmap  altera_avalon_onchip_memory2_180    ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
                       
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg
index 3f74f6bb1421b14d8938d11829b1827cd0925ee3..2e8201b860c22edcc1af638c147813b103462960 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
index f9b6566b8737158a23387418ddcfaa01f06b9103..db85d837ed13d5ed34522941592c314fd4cd9a4c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
                 
 vmap  altera_avalon_packets_to_master_180   ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg
index 3289315446cc383f3eeb84c3163a1cea5dcd7233..e4cee3f822611a68afa069a7630a012e051504b4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
index 3f67e1b1cea65400bf28774c3e96a3d3fdffc38c..ee66c060b0e7e1ca395e7dae50698d29a8bd7cdb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_sc_fifo_180  ./work/
   vlog      "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v"  -work altera_avalon_sc_fifo_180            
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg
index 7bf034a3bcb61e092a479771a27ec097eb27b481..ed16e284a770883d87f7fdb9468f09e0cf8a9937 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
index a2defb493fec5579e0e6139e52298a412daade71..1a6e4e1ee4bb0e5a2c60a0180f457e2140ab51eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_st_bytes_to_packets_180  ./work/
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg
index 55d4345da94d771253e6f80c9d5db7ed48c57449..03860ad79b74489d5e29d906f7fd3c6895c2e9af 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
index fa3ff32e9a3eae243226670d61ef1034926bd801..5399369f80dc9e53407739de92814c1c9cc6cd84 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR  "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR  "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 vmap  altera_avalon_st_packets_to_bytes_180 ./work/
    
   vlog  "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v"  -work altera_avalon_st_packets_to_bytes_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg
index 3b7ae8e33f1351b8105bf70fffe638ce1b9c9f38..a854bb9e76dc29acd439faaf288c2c853843a7f5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
index 924011817811ef6e8b5e06f9d1ac3dbe6fdaa5b8..e9fe426fe4f1667c8b02624e6e1adf0ecb98765d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
@@ -29,34 +29,34 @@
 #vlib ./work/         ;# Assume library work already exist
 #
 vmap  altera_avalon_mm_bridge_180         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v"  -work altera_avalon_mm_bridge_180
 
 
 vmap altera_emif_arch_nf_180 ./work/
 # ddr4_4g_1600
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_180
   vcom      "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.vhd"                   -work altera_emif_arch_nf_180
 
 # ddr4_4g_2000
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_180
   vcom      "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.vhd"                   -work altera_emif_arch_nf_180
 
 # ddr4_8g_1600
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_io_aux.sv"             -work altera_emif_arch_nf_180
   vcom      "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama.vhd"                   -work altera_emif_arch_nf_180
 
 # ddr4_8g_2400
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_180
@@ -102,62 +102,62 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv"                                                         -work altera_emif_arch_nf_180
 
 vmap  altera_reset_controller_180         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vlog      "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v"                                               -work altera_reset_controller_180
   vlog      "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v"                                             -work altera_reset_controller_180
 
 vmap  altera_mm_interconnect_180          ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
 vmap  altera_avalon_onchip_memory2_180    ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
 
 vmap  altera_emif_cal_slave_nf_180        ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
 
 
 vmap  altera_emif_180                     ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_dzobyri.vhd"                                     -work altera_emif_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_lwknerq.vhd"                                     -work altera_emif_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_gt57qoa.vhd"                                     -work altera_emif_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom      "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_nz3mdxa.vhd"                                     -work altera_emif_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg
index 1be2e657dcd3e50cddf8cd74456d08a8d04445e0..924e8424e8ec3f22e5133e638f5f7fb97ec75017 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
index fa00f3d2fb36bb6a7d745a58d26434b69709fd73..f242ec4ebb2730911f3f97b6f1e31a2f9564163f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
@@ -30,28 +30,28 @@
 
 vmap altera_emif_arch_nf_180 ./work/
 # ddr4_4g_1600
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_180
   vcom      "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.vhd"                   -work altera_emif_arch_nf_180
 
 # ddr4_4g_2000
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_180
   vcom      "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.vhd"                   -work altera_emif_arch_nf_180
 
 # ddr4_8g_1600
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_io_aux.sv"             -work altera_emif_arch_nf_180
   vcom      "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama.vhd"                   -work altera_emif_arch_nf_180
 
 # ddr4_8g_2400
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv"                -work altera_emif_arch_nf_180
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
index 6a6fb2b5794a0f12129400737b18c42dc5fb34c1..0dc6055232f40935b39ce3f031d658673e9ca83c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
index 9e8e93ee026ef285ce6a9ea9c28c7a548d4159d5..71d21df766031a097ee638fb55a457938c5528eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
@@ -30,16 +30,16 @@
 #
 
 vmap  altera_emif_cal_slave_nf_180        ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom       "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom       "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom       "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.vhd"           -work altera_emif_cal_slave_nf_180
 
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg
index 56092a8285d28e0679f1fb45189e4e253d6cd5c5..abbd88a2b6f673922a4ca6558c9f1c7284223aed 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
index cff47b359f6891ed690a27c43d6451c3d446f064..a5c3c36590b3094a82f565e9245dee42e7ecbd76 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
@@ -31,10 +31,10 @@
 vmap  altera_eth_tse_180                     ./work/
 
 # tse_sgmii_gx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 vcom         "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_dm7dxyq.vhd"            -work altera_eth_tse_180     
 
 # tse_sgmii_lvds
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vcom         "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_zsww75y.vhd"          -work altera_eth_tse_180                   
             
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg
index 06e083362fff352f9c6b5ab461ee3e50bb7e1bf5..dbd706bacf868e5855d1c60b19bd3d07efd3e4f1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg
@@ -21,7 +21,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
index 9f48b1b749250a738f695bb7ce7bc2c69f59118d..ebfe3676cb19cb08a431b9203e96a6590c0d6bfe 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
@@ -28,6 +28,6 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 vmap  altera_eth_tse_avalon_arbiter_180      ./work/
   vlog      "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v"                                                   -work altera_eth_tse_avalon_arbiter_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg
index dfd8b2b09dd4a031fbf041cc21478ce7c319d34b..c7ddc2cc43d40a5a79a14697204544d96a402127 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
index 7253272d7084058511d59a5d0af08740a7b5bc40..358035beda539eb04f5474b0b081a44f89b8bf16 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
 vmap  altera_eth_tse_mac_180                 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg
index 3ca851ab1d2ef90e6cf2b0b793c6710e42756364..b5ac49ae697fd0b1a92f682449138f6f41228271 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
index 325af551d7de32b53e49add90339e834acc14c18..7bb7d7873ed59c1df6cc54ff92de5c988dd65190 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vmap  altera_eth_tse_nf_lvds_terminator_180 ./work/
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg
index 6cc184f5c60d447b5e774aa90425e71ae846bc61..0faae4f5e71372033e852f32418c1f1f7279c66e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
index 15cf56df5c4669ec66a27e29622bdb5898b2b7bc..01f18f57979d83e0f571442af961ae5312ee8a2a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
 vmap  altera_eth_tse_nf_phyip_terminator_180 ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg
index 20e2f82c822650dffeb230becfa7416a1a49e5fd..5ca54798714f047615e8205596609a3caaef9d0e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
index 490a07462d595096e527514d0faac94024bbd17b..5f0cbdfbe7f9ec6e8e393ea20b8a4590cd96e6ea 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
     
 vmap  altera_eth_tse_pcs_pma_nf_lvds_180    ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg
index e32f89526d82d3d49ee09b86d0a44e44fe2f2420..efaa584853d297175315e30042ffa55c2f762307 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
index 55ca36b48bc56676a2f54a39c67217684a57ad27..c5d8719befd1072ee3d2bd73432fe5b382afa189 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
               
 vmap  altera_eth_tse_pcs_pma_nf_phyip_180    ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg
index 37eeea420586c91ae99ab0d51d5bc775c2eb8b77..9eeb5dab0196721dee069213df2899a3ed4748b9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
index 9b2f11d2d4a4b97ca45ada28cdd022c960594ee0..63926ceb2f04ac81eec037e3c1653d710c2f0f17 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
@@ -31,13 +31,13 @@
 vmap  altera_iopll_180           ./work/
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_fp6fpla.vo"  -work altera_iopll_180         
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_abkdtja.vo" -work altera_iopll_180          
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180          
 
 # # Refreshing /home/hiemstra/git/hdl/build/unb2b/modelsim/ip_arria10_e1sg_jesd204b/work.ip_arria10_e1sg_jesd204b_rx_core_pll_200mhz(rtl)
@@ -48,6 +48,6 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 # ** Error (suppressible): (vsim-3584) /home/hiemstra/git/hdl/build/unb2b/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo(155): Module parameter 'prot_mode' not found for override.
 #    Time: 0 fs  Iteration: 0  Instance: /tb_tech_jesd204b/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_corepll_freqsel/u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz/iopll_0 File: /home/hiemstra/git/hdl/build/unb2b/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
   vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo" -work altera_iopll_180          
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg
index cd252f68f6b28d98d5fbc0fd5431ecccac466b12..6516cce8a60292241fe8b82c28363b51fe71160c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
index 369e946de1c7ebdf482d7ad2e17ccc7939515c3b..376779b230d63fde3e96d2a3b14fcbaeba3df1f0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_ip_col_if_180 ./work/
                                               
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg
index b1a0d1270bbb14678cfde8fdbdb9f8679955b2db..024a208bafc944a66ad98fd734894051eb05501a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
index 845d83faa1b8d7bc4b4ea7fa2e28501c68660a66..91cbbc1e60e660ee7fe85f06cf7229e69e8ec74e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
@@ -30,12 +30,12 @@
 
 vmap  altera_jesd204_180           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
   vcom         "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_jesd204_180_3rumeui.vhd"   -work altera_jesd204_180
 
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
   vcom         "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_180_too2kia.vhd"   -work altera_jesd204_180 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
index fe8c51f3ddffcde0b3e41eb6d6496cc67ae77d01..358aee47eb74510ca136f0bdf68c792a2487b947 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
index 116a846afa7dbe6d51d8ffd81fd356d8571c17cd..b4a09da3ddca81fd81772e01c2e7fbd7c5baaec4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
@@ -30,10 +30,10 @@
 
 vmap  altera_jesd204_phy_180           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
   vcom         "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_jesd204_phy_180_wv3zwea.vhd"   -work altera_jesd204_phy_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
   vcom         "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_phy_180_s336zrq.vhd"   -work altera_jesd204_phy_180
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
index fccfb8daffbc53e40d49e78a63fb1b15514a0dde..f8876e64a4868581e2b1c5ca002e79d16bbfbbe3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
index bb1159b2e0b6ab73dd415a81e3cb60dc56a8d5e1..597e45ada39afe2d029125076c64247c705f8be9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 
 vmap  altera_jesd204_phy_adapter_xs_180           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
 
   vlog         "$IP_DIR/../altera_jesd204_phy_adapter_xs_180/sim/mentor/altera_jesd204_phy_adapter_xs.v"          -work altera_jesd204_phy_adapter_xs_180  
  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
index 703a6aa2e01ff24a116c47118c470aa51ef06bea..0f1de0165dcc95bd664ccd37749b7a142c7610b5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
index 93fceea38fb20d022f8e89f494b8ddd3f9c77e95..6b267b590f8967b01420f7e14b2d431815e1fe65 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 
 vmap  altera_jesd204_rx_180           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
   vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_base.v"                -work altera_jesd204_rx_180   
   vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_csr.v"                 -work altera_jesd204_rx_180   
   vlog         "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_ctl.v"                 -work altera_jesd204_rx_180   
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
index c780bea06580973990e2e1b303a4fdc298fbfe2e..abaf70661d8d5b7b493d54596c5e5804b03cd10b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
index 354a1a282cddfe3a04ba5265eb3ee232ca843fb3..4d4ba7db94f72384e9d2074fb4b92ba9328b5587 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 
 vmap  altera_jesd204_rx_mlpcs_180           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
 
   vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_dec.v"          -work altera_jesd204_rx_mlpcs_180  
   vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_rx_mlpcs_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
index 14bea6845303cee00d39f819b4b1798eaeae0de8..cfc479206af7ddac5a07c5eb91868d7ff90e090c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
index 6886f04bce27b4e594faa0a43b734c51aad4de93..20cfae71a6d603bcc1a995a059f08f4095dec766 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
@@ -31,7 +31,7 @@
 vmap  altera_jesd204_tx_180           ./work/
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
 
 
   vlog         "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_base.v"          -work altera_jesd204_tx_180 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
index 427108eab82ca9f44e552a0771b752f5e74e7086..23c41baba7cfb4b56a7d8f72d77d2dcbcf71e99c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
index 95fa227480c611f04cb84ba53b1ce8af0ba06a69..68f07f1a547014ec41dc90fd2e24a523ecd40db2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
@@ -31,7 +31,7 @@
 vmap  altera_jesd204_tx_mlpcs_180           ./work/
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
   vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_enc.v"          -work altera_jesd204_tx_mlpcs_180  
   vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_tx_mlpcs_180  
   vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_pcfifo.v"             -work altera_jesd204_tx_mlpcs_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
index cf8d72f457987196322df731e3642000a0fddc3b..87b69774b9181d6a9baea1d3e02495b3ee6ad74e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
index 74c891aeba6bf0dd16b62025009fe212598b2216..7855db26f8e5a63f80266935f967b88efec513a8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  altera_jtag_dc_streaming_180          ./work/
   vlog      "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v"                                             -work altera_jtag_dc_streaming_180         
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg
index 9ab2d1bf1181f09457185a3c2c3c31397b7f9184..bad1021d85ae30172b1cf87c053f10688ca78608 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
index 27e323677c47e105f8741a7bb15a1a7ad2d90f2b..0638a7a9520818a6dc10f6621e4bd549eee72d7a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vmap altera_lvds_180                 ./work/
   vcom         "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_og2byry.vhd"                -work altera_lvds_180  
   vcom         "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_zfbfxeq.vhd"                -work altera_lvds_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg
index c9f081b5e9ab2420e0ff9abfd97dbfa7984e8743..7918f7e5b6e061f7374a1cc338145378a5108d7d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
index c349496c4228765340b65ce927357d1c8bc0e4b9..763b27886008cbbb58ceef4c7af44f8475861e43 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
 vmap  altera_lvds_core20_180                ./work/
 
   vlog -sv  "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv"                                       -work altera_lvds_core20_180               
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg
index 7c32b3d8096cb666f8cd6647647cf80f5da0055d..45552c10d28c721fb911864848a2041ce4160688 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
index d94285a791912268da4ba249b191284fcff83aa5..80bd106da1914b57491732edf57ce30133229073 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist      
 #
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
 vmap  altera_merlin_master_translator_180 ./work/
         
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg
index 2b22aa3b9bab2038ce187766a3eeed776b5dc003..0458c0d485ce69a1802f5d9ae60321bde99b75bf 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
index 5556de9e14d841053e4568950bfa4c549a6a8395..abeccdc26435224da3598c2864522aa281d814b5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
  
 vmap  altera_merlin_slave_translator_180  ./work/
                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg
index 91f77c91d4b20c333d22748539109255b9ec0980..ef0408552afc60655882324df3a66e4b642c6616 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
index 2b1c5214731b4c8bbb98b4887fe4705a3dcf24b0..260516ca230f890a50041bc00838d86108f880ff 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
@@ -30,16 +30,16 @@
 #
                                                       
 vmap  altera_mm_interconnect_180          ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd"             -work altera_mm_interconnect_180
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd"             -work altera_mm_interconnect_180
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg
index 73f5fa237c14155ceb1562acc27f9bc2365ad5b7..90c355771690727296aafe534936e93637f13527 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
index d884da7788a187319b1370e4c7af6e946d9feca8..4923e9411fd1cb74b2162c30701fad84431b389b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
 
 vmap  altera_remote_update_180      ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg
index 699861d08871f499d913760cc635f80cf95fce69..d3736e725ba85b71339504990cfe7de80807fdc3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
index 3f761c4a642e4aaf370045f295053240950688e9..27a2935517fe106c7374ae001c78310471dcb8ea 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
 
 
 vmap  altera_remote_update_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg
index 92dcbaea09fc47c3e4c54fa832a508ad6a2001b6..9aeb845fa91601af9463e374ea04a545046b381c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg
@@ -9,4 +9,4 @@ synth_files =
 test_bench_files = 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
index 072c34aed34eda1c0bd9b4e1883a46904e422a28..56f7ad4cbbda4691a6b9506ad554fb48c9be9d4b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
  
 vmap  altera_reset_controller_180         ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg
index 048e59748f41635bcb9512ae33b540ae59b466aa..58c720a92304fef5d3aa02befc89bcfa5ddc86a6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
index 1353d920fcc1f2d3afac96c67688b5fbc0a8fc76..febef6eaa2f475652e933e63f2595e10203ef49a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 vmap  altera_reset_sequencer_180         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
  
 
   vlog     "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_controller.v"                -work altera_reset_sequencer_180 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
index 9efd3399747fde2a163f95b811613fb7b535e7d4..d60aa5a141de4689b9dabd94ebc4b2f485600ca0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
index 0a291e94b1ffa4e695a43cd793fa1cf539edfab9..abf16a6330d3a5ff6fe320552e9448b3621d882f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
 
 vmap  altera_common_sv_packages           ./work/
 vmap  altera_xcvr_atx_pll_a10_180         ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg
index 595a260842eec6a10f6cce32b8b94699306e5160..6486c0dda2f9524f983bb7edaf4f2e408669e9f3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
index 16078458ea96afd0cb2f880fd0ee92ce1ad0688c..278e32120b0b7699dc9134174091aababe1f8232 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
 
 vmap  altera_xcvr_fpll_a10_180             ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg
index 06f182471af951ce942b9aacb024d1315fa19bf0..05f9d5098a20dfa5a4a8eba6ebb76562609dd81a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
index 90bc5aa8c7c5d0fce9d428878f287120693a595a..da4753a079155f5b9fbfc64e48713918a0d513a7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap  altera_xcvr_native_a10_180       ./work/
 vmap  altera_common_sv_packages        ./work/
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
 
 # common dependencies
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv"                                                               -work altera_common_sv_packages       
@@ -68,41 +68,41 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_24
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_12
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_4
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_180     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r_3
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_180     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # phy_10gbase_r
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv"    -L altera_common_sv_packages -work altera_xcvr_native_a10_180   
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180 
 
 # tse_sgmii_gx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv"     -L altera_common_sv_packages -work altera_xcvr_native_a10_180            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # jesd204b rx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_180_vcpx3ja.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_180            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # jesd204b tx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_xcvr_native_a10_180_q3qhp5a.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_180            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg
index eb5db3082a4b3930a9ea7375cadc8d1603538fca..8e2b4740c0b63c284291ea28b76ba0e307b3fae7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
index c99889b4826946bc97e0ef6eda25f2e85b688849..687d9bf2eb56786c3ce70397b91a7cc46b65b486 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
 
 vmap  altera_xcvr_reset_control_180                  ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg
index fe27ceef663f34a181c37534217f083153ea9d5c..f5e465258199a0c888a20238e28e3b9e6ade54d5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
index ec2dcbbcdf6a8a6288914d8cf48694a1eab0760b..f9bc5424735a0fd5d4670c4ccb7053b31d0a9e6d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
@@ -29,11 +29,11 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
 
 vmap altmult_complex_180 ./work/
 
   vcom  "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.vhd"        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
   vcom  "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_27b_altmult_complex_180_ylvsosy.vhd"        
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg
index 215374a05666f20500de476a8ae10a96c4b9ae1f..f90fb7bea47a63787221744a47fe1d0161b7c1f0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
index d1c2e5c5d8fb7766f9ccff03c03eb0f1f805d928..79d78a02f240dca1c415e8d0655f644126eb3838 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  channel_adapter_180                   ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg
index 553bb719ff1707b0b57f6d5102ec0cfac0e1ec79..73a67fbf08fa8cda55bf65b207ccab0b4f70113a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
index de74d47a27b7611fd6c31a50270f4365e6272498..dd0ebe9a6983d3c418dc741ba141c5c6e0a65899 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 vmap  timing_adapter_180   ./work/
                   
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg
index 342089f106b5e0e44d6519ee855b20169b767440..c9c52e6799aaf12195e1aafdfa00d6eb03affbff 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 73fa9937b39cc9564aa048bfcfa3f8c1d74cd0b3..3d395b250cfca9e836d1b0c2b0e1ad56f47e5551 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
 
   vcom  "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"                                             
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 322c95752d30393b5c846493dbd185c391a9840d..a196b03871ea23d180b721073cff64f608986fc5 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
index c9a33bbdfc0710640b0f4e967376ce8a5627e40e..2e863c2d4bc14d7e9cd91d360150bfc69e948cda 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index 45d5f65a6e8e781a09c623d0ec324bdd6f429e17..0ded9b559a3a90c4a8c83df6cb08940fba10bdce 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,8 +29,8 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
   vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd"
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
   vcom "$IP_DIR/ip_arria10_e1sg_complex_mult_27b.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index 6debfcd8fea764673a7c664cb7da54ab1a96bac5..338467998b1d670198aa8c6637bd4d1eae0a7479 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -11,13 +11,13 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult_27b/ip_arria10_e1sg_complex_mult_27b.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult_27b/ip_arria10_e1sg_complex_mult_27b.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/README.txt b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
index 1823e822ffac72fd6dfccb16917ab9972bed2a75..7ea3cfffa4c932d75e3ec2d52c01d41e8b1fc5ad 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index 5e3fcefa5ebb64853c8ee2693f32028036218fc7..0e0549cce0cd7c45f96bd6334d93e572aa5364a6 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} { 
     # OUTDATED AND NOT USED!!
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
+    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_180  ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
     vcom     "$IP_DIR/ip_arria10_ddio_in_1.vhd"                                                                                               
 
 
-    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
+    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
 
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
@@ -60,7 +60,7 @@ if {$IPMODEL=="PHY"} {
 } else {
 
     # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
-    set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
+    set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
     
     vcom "$SIM_DIR/ip_arria10_e1sg_ddio_in_1.vhd"
     vcom "$SIM_DIR/ip_arria10_e1sg_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 6fdd643351675e042111525e1af727a64e93267e..7ded757226f3fcd58109dd2dcd4aa7529804bf3d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -13,13 +13,13 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
index fa2a0fbf160c94be212b1cd575ac68ba073288bf..8b009fb307a072e8786283739d595242d0402518 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
                     
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_16g_1600.vhd"                                                                              
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl
index b6d7c0dbb9fcc6c2fc33dee4ecf6dbb234260556..2df17149740cf5cc60ee53b6dcccfd9de7aa199a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg
index 4c7c7b3043c3f807960e25c6112e09d414d3514d..9d2597334a1531418906da3aaa2dd9ce46c06ca1 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
+    #$HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/ip_arria10_e1sg_ddr4_16g_1600.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/ip_arria10_e1sg_ddr4_16g_1600.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 7b57f32c77761658d8555f5a962322a97d802a08..45e98a1c47c1cdb750252cbc8127c4b8c522e99b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
                
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index 47c09e91fb01920240b2719cc1f44c792e6ee159..12bfe4edd85f7431f3cf28e11fb28d97e4472c05 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index c6034f2bd565ec0f957a3fcce1d75dd18d786a8b..25e96f38fda10e912e34b8c0a45543e38f8377d4 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index 2b8a534222f35b96791c2559589a67326042e0fd..1650d44f51fa3f3044d92b4f95ef255c00257cbf 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
               
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"                                                                                       
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index c41260fe481c9987eb3cded67b7ac30caa72ae5c..b24051e068f14967a92b74c10155334377eba57e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index a22ea2e96a16c47ff1d501631aaa9a10d8346d67..1721b0eb3558f81b4aff29bd9169e9501ec3cb66 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index fbbcfe7aac13c0e04a0262d21120cd98db2afbcc..2cfbbd059dcf6e3019c3a096a5a80134b437337d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
                     
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"                                                                              
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index 8a8cad31d528913d98c75e06c867b6c292a8f002..070ac6b40e4c33fe35f6bf1963f5cf08fecad9b3 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index bff7f43f6487d547b5ba08de983cc04b19c503ef..e4d7e55c3d5f742a4021a0dcbebf5063c15de4d3 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 6655a839f81d14880840d7b9b039a945e1d917ed..2638a04129dcefb3efba4a0a34592ae7cba6381d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index 48548cc80da7a8ce8c67542c159ba02dc1c81897..6a9ec1a2de3a13c82802a334714e3777cbfc3e94 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index b203d90d95a6e4a324cdc2b1380fc5af116b6dce..0d73d17460de58499f0d513e22f3b0a1b82f1b1a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/README.txt b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
index 6db25b6412e89ebde6decb09c13f7e14890315b0..bcf8b55de24242e455a4481c6c64b948f0d04797 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index a4c21a5083b10e01b62e4451a94e5766422c8b79..a708e8034288473042353c0399da5b1e911d2580 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
 
 
   vcom  "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"                                                                
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index 802d7bc9b687d0c6d345be36d44179dff86f293f..9b31c2fc1378d1880e9e500fb47e67e0ba777f72 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index d721b04349295f70c6feb364690f5fa363d657e3..1f003afd9b87762c816f1489a7b13e2a25cbca59 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
 
  
   vcom  "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 64c28833bdbc85573cfff07c1d63f99545b94319..9ded3d115113876e415cf5bf606134a88f432c1e 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index 1c55491d25b7e57b72491e61b9262f450aa97709..f93c3aa93962977cf4ee463ef6f74334ac921081 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
          
   vcom   "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"                           
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 9ad42d42523220226ea426fbdd7e07e353e7fe58..1360add5dd6b91430e277e6b90d4f1fc965d8925 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index d62136904bc45e1c2a440bd325bc8bcf125a8bf0..7d453434694e4580eae0dce1ddcac777a90d8d72 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"                            
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 28bf7f6a7871285ce62baa8d8848b319ce4a19aa..7b9aa4a0ec7c7e09cc29f1a701293b0c7f131350 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
index fb6b4c779d484603cb58acb8025a5b0e3e228b89..44dc6479f435a9b926f797bafdd13b0c3643e02b 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
@@ -29,17 +29,17 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
   vcom         "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_200MHz.vhd"                            
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
   vcom         "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.vhd"                            
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
   vcom         "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_reset_seq.vhd"                            
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/sim"
   vcom         "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.vhd"                            
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
   vcom         "$IP_DIR/ip_arria10_e1sg_jesd204b_tx.vhd"                            
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index e218af49fac038b6f6da9ed00c42b42f03674de0..33d3183e33517dbf202c9ff51cfba91e832f48b5 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -12,17 +12,17 @@ synth_files =
 test_bench_files =
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
 
 [modelsim_project_file]
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/ip_arria10_e1sg_jesd204b_rx_200MHz.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_tx/ip_arria10_e1sg_jesd204b_tx.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/ip_arria10_e1sg_jesd204b_rx_200MHz.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_tx/ip_arria10_e1sg_jesd204b_tx.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
index c775402d02b409cbc5f046ee91549577ddf8c52a..0f920fa60eb1bb158995b720f14582422039bcec 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index 86cfa6cac3c69e353b5a784aca3cf3bd6a80312b..1c211f6ce77eab1736f2cdb2293dc4304b866453 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
 
      
   vcom     "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"                                                                                        
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 508bbebf1f01513b700caab82607c0759bd84917..f93698397985ca0f3a00dba920a6256930fdbc70 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -9,17 +9,17 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index 82202caa753d96f5ef579124ae82e43b3d062924..8d098b26ceb1370b059ca79aa43962b836ce3e2e 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
 
 vmap  ip_arria10_e1sg_mult_add4 ./work/
 vmap  altera_mult_add_180       ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index 0aca429ea06daa64dbeee3b3526c124b987b3c21..ea8fcb393b6adc0ff7a367cbc523904718395e74 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"                                                                                                  
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 9af7dc8bc851932be599d09748e903f5a873853a..4bee4b5e5ba13a7a861a94daa7487beb5b37ab46 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 4aa3d0288ed14c3bce53ac2a3c11d3913d7e008b..2736172286780eef136f59560c695e36175ecae3 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
 
     
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"   
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index 0d284db59b6114f7e109e7eb08c3ff3ec0d00d57..627972c121fd15d8a9e0428a83d73fcfa84ef91f 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index fa35c21f357b100a23edbea6db7b1bcf373465c3..94616624b526848a0e4b0c8717d4689323dc6a03 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"         
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index f46a87107adc6133923eabbaaff96cd4b6239de7..95ba59732ee2ae6ef7a89ebf2c000bbc1c78d223 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 81251469c69078e91f865c2c074261af7a3a9c51..3a060c4715c7aba668425aa5038bd97499e30e4f 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index bae65c01609d3ae0bf94ac6bceb8de6dfa71c83b..da507aaada2a6feb08bc0030b0fc8c6bdaae50d5 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index e52b7142990360c4c48a38be38c05d0e0d1da9a6..31257d769e70a8d1dd370da0c2fa8117d34d8af6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 05e6b863a664e8947477ad9bf568462b647b486d..0e8778478e9dffb7998ddd6fe195e98f012335bb 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 555bdfed731f97884e1219dd24461a6d0819c5d0..1343afc3b59a5e9269152b2004812ae90625603b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
 
     
   vcom      "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"                                                                    
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index ea4dd7440b6c716e40eb8d91e646aa46a2a11fec..6bd52a5a257a6a85e4ab4241468fd93d9d392293 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index f6712cdd63d903940460fe8a517e0d37b48f0ff0..d18342e3f5b6c088b1bf6e2fd5d7c3c7c8052276 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
    
   vcom     "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"                                              
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 5bb0972c0c04b8179ff312a03df21d2736016582..550e96a1f9c24d6b6e6697cc15f2edfefc0699fb 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index f7f3cec7ac4e866c30234a7afc26b74bdb89557b..edfbbf4c076bd1b13d4585581613c7852b6f8a5c 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
   vcom  "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"                                           
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index d745852618bbeee287e3b2689f96251f8d822716..282fcaa525d1ba7b1c88f9a9bd790307247482fd 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 710e0dcc0043d4ed1605d5433ba0a1d176171d15..40eb599bd5eeca7d2b25ad20a2ecbd476ff9b671 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
 
      
   vcom  "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"                                        
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index c06945b319b0a50b94941c2d38e3bb90993fbbae..cc5c3236778881116aeb14e0033cc465e20f4420 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 27231003981fb24e6f906b909c4bbb1aca3d5839..054104dc07c3b24b524a7788406455f2a9fb01f3 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"                              
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index fb2761f88131214772cd9868a54bcd1b000deb87..97be02852a283fcff204f07badd09c52a65c7fd4 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/ram/README.txt b/libraries/technology/ip_arria10_e1sg/ram/README.txt
index 24ad4ab94e542bd2d642eaa079f4e18624d8c163..bb10b060478b5b615634aedfea779ac31cbf3845 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 77ca49010cf8cdb964e013ae3a0260553f0b0a6e..f8fb076632d1d86a5d74b02e2955fba283668de2 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
 
 vmap  altera_temp_sense_180      ./work/
 
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 71ad52e9e476160785b73d430afb8c6854a29d31..00b0c605f5dd5dc8a2c6d507bef3fad7c37ef436 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files = 
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index fcb30bbd9025a5c32590682c384e5a89cd0d75b8..e62b1ca32fe1b8a4193c2430560173f2a1683a2b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
 
   vcom       "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"                                                                                                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 30c1dbc1e5e3c7ae96ab91f8dfee2fc24cb3d439..3a524095edc9c2290da77e052521cc119ee6253a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
 
 
 [generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index 076177e1677f824bd02fea3cd99eee0e0b69df54..11105df2aa676cf5ba385c58df0d9d1baaf61c13 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
 
                
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 42274baf396d77d0428e286103dfd6f66c02f127..5c73b7e94a9ee1c42ca40fa26c5dad911d123b52 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index aba40145fdc83925800ffb409387d493c517079d..a708530bf8c518ffe2fde52eb1429107c1e0e8bc 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"                      
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index ae5ebcdb13bbf401b52c605b3d643e8222956c5d..9e85b27173db97bc284a57c58696a3901dd0025b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 70970628ba950e5063873ceefa755e70f4060e9b..87293d4a5f12876019d2b7d5d54a5d096f152139 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
 
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"                    
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 6e0d258dfbf6de1499e5e57ab45b86111ad2ad31..3e4bf12806f71860b61e4f2d7c41158b18dc6c4c 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index 64f9f0b300fa79d4a20ef439e8b5ddd23d70d403..a1f71285b5e64a3f00788fa4c6b41d89ff31c8bb 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 8a9a5c4f5f71d953174b78c3422b507622e4d9b6..69c5ad040c1d5a8e0f2ca22e6c496eddd26e186a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index f939d89ec657fa800c5cd20c6dcaaa3a8bd750d9..d8cfa66c847d5e9da0d6eb5ed42b1ed9796760f3 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 6871a530371cefb160aaf96111960e1869182062..4c64d9980e16f35d091a3b08ad4cf65977f4123e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 6450d4dd24dbb605c5b4bf3e2c3fcd7e06cac3f8..cf074f0e1289216d80eb041de92b8aa70362d851 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
 
                  
   vcom      "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"                     
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index f24fde1a35d33190f400bbe21ef804f02a4f91b0..127f8b08aee4a4d71b16ab9473d118050c6596ce 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
index fa105db173e0dc963f59b1e10b143cf5cc782167..8b2022353701472bac9f6210d3711db0e1f06574 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
 
 The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
 
 The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
 
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index f195da292399416ce68ae5dd5610297ddcc43e21..33ff4e89d52bf16f33c80575ded3d2fa8b12e1ca 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
 
   vcom         "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"        
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 6b6ad07b4ca2a22bbe83e592a3873fc0466af76b..3b3cd4c3a6abe7a6503d91e6a31bc29054e0a4cd 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
     
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
index efe749e3a03ff7e95c29fd5bfc6bb62ae55040a2..2272417d950803e9bf009b24dc20bc41ba38a416 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
 
-See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
   
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 3b2fffc3b6b66c1c07faa9935a77768f3bf02ce4..bb52a542f9bafa95f952930ec469aad1dd88f17f 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
         
   vcom         "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 0496ed8bd15cfc12b6dddc52c61f9b8fca70456e..27b20a3b05fc570f07d55cd4a1e3559f4e1de90d 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
 
 
 [generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 1be59a86e78fdeefbe27c6b3750c369389304f73..0d545f56085d38f564ecf515fb55d4b47b39aab2 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
 
 vmap  ip_arria10_e1sg_voltage_sense          ./work/
 vmap  altera_voltage_sensor_180              ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index a6cb5882e899f8467809c7c9057056237266fd4c..55c47eef1606f687ef42decfd54d9cd90fe876ce 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
 [modelsim_project_file]
 # There is no simulation model for the FPGA voltage sensor IP
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files = 
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
index bbaaa7d7bd3941d35d8300ca4b6e6f708fff89f8..5fab512f1ff958678c3ab7b87329284860cc992a 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
 
 vmap alt_em10g32_1930 ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
index 4f6dac9d7070fb4627d0d8f456b2b7668311dbc3..3df0b854b0232b85bcd5c869d03a08a32d28597b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
index 6a422a978dc5ca152613cc38dced494d251d1a94..5f7bc2d6f226db39186fb87c0f664dbe578e54ba 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
@@ -30,17 +30,17 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  alt_mem_if_jtag_master_191            ./work/
 
   vcom         "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_8g_1600_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191           
 
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom         "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191           
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom         "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191           
   
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
index 6bd31de18b90b6965bdbb37310a610c74d501f6b..373f4f13c88b445680a0a16326c0496dadf6315d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
index e58f06f5877094ba211095c133a4975cd36348b8..89958dcb4908d3c53fbaebd5d3f7d307064396d9 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
 
 vmap altclkctrl_191 ./work/
   vcom  "$IP_DIR/../altclkctrl_191/sim/ip_arria10_e2sg_clkbuf_global_altclkctrl_191_njwbsri.vhd" -work altclkctrl_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg
index 869930dac5f0ed5c59c9002c7a17b84586cbedbf..900b436173146bfcf311c20983d22371e3127923 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
index 00bd880cea1552a27552b4dbf4ae6a23d56744a8..bebfc84a70f35f833a677cfd1bd1a23471a24f1d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
 
 vmap altera_asmi_parallel_1910 ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
index cb81ea68e169fa09afce37ccf944670699a36bc5..b55caa82d66dcb7b7741133b823c55b6ffaa1a7c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
index a98ab0bd16fb736775391e787972653c3746f196..021361dd58716463d0a58b5d0ee8bffe44528e8e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
@@ -28,17 +28,17 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_mm_bridge_191         ./work/                       
 
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191                                                        
 
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191                                                        
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191                                                        
   
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
index a61c85e5fddbfe5347e92eeeee5d51ad1334a3d8..b146a2e536f964da03f84eff452f039e1152b093 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/generated_tb/generated/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+    #$HDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/generated_tb/generated/sim/ip_arria10_e2sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
index 87be9c3c25dbbb0f90789be7bde4ae1b4e044370..6378d89b52e1eaed7d2c3537f633a38936ff07d7 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
@@ -30,15 +30,15 @@
 #
 vmap  altera_avalon_onchip_memory2_1920    ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
   
 # copy previous 'set' and 'vcom' lines to include more ddr4 variants
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
index ef094f0cafe442967fe3ca5f864f7c751eca1488..1f9f1929d3aae1974c7d8069d5f5d75c76b07779 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
index e66734a9bef98a0d3decb419cdc7ad84b7a3875b..877ab950d0a736de6a623a2716b60d3067a4bb75 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
                 
 vmap  altera_avalon_packets_to_master_1910   ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
index 94aa08893925788d8d9339e91491a72a3dc16a07..b5c2eb97a853b4cc25dc9d87eb96cdd0d52db8ce 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
index 53adedc0d332eae89b71cdaf8d9047a0f76004d8..bb10bc66925dda784a8a46e68b4e26757b2939fc 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
@@ -30,17 +30,17 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_sc_fifo_191  ./work/
   vlog      "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_sc_fifo_191_e5eqkcq.v"  -work altera_avalon_sc_fifo_191
 
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vlog      "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_sc_fifo_191_e5eqkcq.v"  -work altera_avalon_sc_fifo_191
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vlog      "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_sc_fifo_191_e5eqkcq.v"  -work altera_avalon_sc_fifo_191
     
                       
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
index 431d59b521707d1f8515f28ccc1bf281dfbe9817..d3c83534c48a7cee3b4b86bca0b23ba6846dc19b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
index 0e6cdc7f45f2f0a8e71096de6b9e7083903e7120..a3426d99093cafe19d9499be5066cb4ef277697b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_st_bytes_to_packets_1910  ./work/
                                                       
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
index 963c12636c1ed46559a5c016310ee8485b3b1f35..16af62b209226f24fe297658a483684374ff684d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
index 98ea21838ab1831f4f142a190d807c0d24c7f5fc..a0e16162bb881b2bf2237cb4b0d9a25ad4a22ef7 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR  "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR  "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 vmap  altera_avalon_st_packets_to_bytes_1910 ./work/
    
   vlog  "$IP_DIR/../altera_avalon_st_packets_to_bytes_1910/sim/altera_avalon_st_packets_to_bytes.v"  -work altera_avalon_st_packets_to_bytes_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
index dd502e7d10f2c6cd32b23420579e9cd7a3398f9b..7f851296a854a376023254be14cf5ed30c09e5cb 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
index 3c2347f5cff73270de8a1d3176b97c06cef2b8dc..4d9fd39c9c45b99d46a5e0e4fb06c73a7f3c6bc8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
@@ -32,20 +32,20 @@
 vmap altera_emif_arch_nf_191 ./work/
 
 # ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_top.sv"           -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_io_aux.sv"        -work altera_emif_arch_nf_191
   vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy.vhd"              -work altera_emif_arch_nf_191
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_top.sv"           -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_io_aux.sv"        -work altera_emif_arch_nf_191
   vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy.vhd"              -work altera_emif_arch_nf_191
 # ddr4_8g_1600
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv"                -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv"             -work altera_emif_arch_nf_191
@@ -94,72 +94,72 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 
 
 vmap  altera_reset_controller_191         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_controller.v"                                               -work altera_reset_controller_191
   vlog      "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v"                                             -work altera_reset_controller_191
 
 vmap  altera_mm_interconnect_191          ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd"          -work altera_mm_interconnect_191
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_3yb4cia.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_monheay.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_dexdb4a.vhd"          -work altera_mm_interconnect_191
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_3yb4cia.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_monheay.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_dexdb4a.vhd"          -work altera_mm_interconnect_191
 
 
 vmap  altera_avalon_onchip_memory2_1920    ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
 
 
 vmap  altera_avalon_mm_bridge_191         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191
 
 
 vmap  altera_emif_cal_slave_nf_191        ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
 
 
 
 vmap  altera_emif_1910                     ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910_jhcj6zy.vhd"                                  -work altera_emif_1910
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_1910_rvperma.vhd"                             -work altera_emif_1910
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910_3t6zvqq.vhd"                             -work altera_emif_1910
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
index 96efe3d56e9b95724750618eb86aa259f0ed21c2..75b7420dd96af01c2fa200764f0d0d320ecd6ff8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
index 12bd8a8fab12aa8ba5970e83c2c90b1d57d67028..68a13ded35bfe47496193ad266d40c45986233b2 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
@@ -31,21 +31,21 @@
 vmap altera_emif_arch_nf_191 ./work/
 
 # ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_top.sv"           -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_io_aux.sv"        -work altera_emif_arch_nf_191
   vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy.vhd"              -work altera_emif_arch_nf_191
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_top.sv"           -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_io_aux.sv"        -work altera_emif_arch_nf_191
   vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy.vhd"              -work altera_emif_arch_nf_191
 
 # ddr4_8g_1600
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv"                -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv"             -work altera_emif_arch_nf_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
index 64324b44d8c135eb63b55760d99e2292228d2007..a3f3cd3698cfae484c61d87c5f5122f8efc5658e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
index 56bd8a7c2171aee9e7b9e6a5d9036179bfba681a..59c175d3b6bab20a20e84899d6e6b149e1711af4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
@@ -31,15 +31,15 @@
 
 vmap  altera_emif_cal_slave_nf_191        ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd"          -work altera_emif_cal_slave_nf_191
 
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_cal_slave_nf_191_rmzieji.vhd"          -work altera_emif_cal_slave_nf_191
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_cal_slave_nf_191_rmzieji.vhd"          -work altera_emif_cal_slave_nf_191
   
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
index f8b87b4e791ced87e285e0c0d42484e58a160a07..c352940d5cecf0faabe4d5257300a407128168af 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
index 95930d53addf1fee79f8fe026be3fd4b35f74e6e..c6d46013172b987b3f6e5cbb2a8f670d680c2def 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
@@ -31,9 +31,9 @@
 vmap  altera_eth_tse_1940                     ./work/
 
 # tse_sgmii_gx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
 vcom         "$IP_DIR/../altera_eth_tse_1940/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_1940_gpmdicy.vhd" -work altera_eth_tse_1940
 
 # tse_sgmii_lvds
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
 vcom         "$IP_DIR/../altera_eth_tse_1940/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_1940_m7xbdka.vhd" -work altera_eth_tse_1940            
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
index 4b557fb62b77636488aa7c5764d41ed1a531eec5..14db726367a9f132365e4284f8a58293abfde9f8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
@@ -21,7 +21,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
index 9e546e6e0fb1c0cc8586d04ae5ef4db26dadd51a..d917e61c352ac314a308ab24ff0241f57adf129b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
@@ -28,6 +28,6 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
 vmap  altera_eth_tse_avalon_arbiter_1940      ./work/
   vlog      "$IP_DIR/../altera_eth_tse_avalon_arbiter_1940/sim/mentor/altera_eth_tse_avalon_arbiter.v"                                                   -work altera_eth_tse_avalon_arbiter_1940  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
index 049eaf9ba49e58035bb241312c2d39db6449b678..585d9f86832bf12b7c0bc3ddf87b8c1473bf202d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
index 96706c0c3f8c99ee8b91aee3e72858e17247238c..aed3e1b91c53232fcf7ed5257591d17746146233 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
 
 vmap  altera_eth_tse_mac_1940                 ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
index 29fc00d6811d87ca322b58c17ddb7556720f1d2c..c20fff2490f0c27f835b98ca176b93cd297f37e7 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
index f22ce117cae8d7765c878c6e49ee7fe4e6a91b06..61f4579291795058d4bd6cf240610595eddb6656 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
 vmap  altera_eth_tse_nf_lvds_terminator_1940 ./work/
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
index 01efe26fe3cbf6ec20f994874132202a4e0e7cc9..03c93273a656896edd0c247590c6b413ec8e857e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
index a19f408746d8f7e2cc91cec319fc40a364b91ce3..5d0e40dc84c753538a2a2b2b5027e9a2038bd296 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
 
 vmap  altera_eth_tse_nf_phyip_terminator_1940 ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
index 6bc962ea4aa17e7993b44642497d4a89cb3e59ce..8dd291f50b4da0a52f24caca41b77ab00c5e967f 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
index 0c0ed04c18522fbee84e585e3a578c3c46587d9c..27b587f453f212ac81d435b276f944b04e7124ff 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
     
 vmap  altera_eth_tse_pcs_pma_nf_lvds_1940    ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
index 15e2f2fc7cf48a2f18dd15e1769f9a7e222547a9..130c99cb7648a2367f5a12f006d99c17d7c198e5 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
index e192256e386eed22e376c243d092b3a9c29b454c..fa922381c026eedc06951122083f29e5dd7295ec 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
 
               
 vmap  altera_eth_tse_pcs_pma_nf_phyip_1940    ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
index d2816a9060329b9ae2b388f003bb4ecc54f9fe5d..b70e0a234a69dd4ec99b3da82af5199543d3fca0 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
index 147ba350e453da698b24460e923557ddf92f557e..9cfc4211b4d17c6a86e3bda6f3c86fd631cc4caa 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
@@ -30,16 +30,16 @@
 
 vmap  altera_iopll_1930           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
   vlog  "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_pll_clk25_altera_iopll_1930_4orwjna.vo" -work altera_iopll_1930
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
   vlog  "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_pll_clk125_altera_iopll_1930_rnfwfny.vo" -work altera_iopll_1930
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
   vlog  "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_pll_clk200_altera_iopll_1930_f63mvhq.vo" -work altera_iopll_1930
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
   vlog  "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz_altera_iopll_1930_ibzmqny.vo" -work altera_iopll_1930
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg
index c27a65e0dc41ceafab724103e066d7c7259959cc..267debb7ca3ac9b5954676fcb100d4772884b046 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
index 34e538bd85aec1d045b646af3d4d0f25fa4d25c4..f628b02f2b52eda985839f79e8bb544cf2e9915b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
@@ -30,17 +30,17 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  altera_ip_col_if_191 ./work/
                                               
   vcom  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_191_k6i7ubq.vhd"  -work altera_ip_col_if_191                 
 
 # ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_ip_col_if_191_k6i7ubq.vhd"  -work altera_ip_col_if_191                 
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_ip_col_if_191_k6i7ubq.vhd"  -work altera_ip_col_if_191                 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
index 6b3ebc9cb79598a489c118a6c9f747ba7df33c8b..998e657abd38d54a84314fa1b769df61a76e0098 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
index 7ca664bc197ed775809f6c1c4bf8b8d725e31fb0..8884239d6de92699ae1546302be5edb362d36e77 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
@@ -30,11 +30,11 @@
 
 vmap  altera_jesd204_1920           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
   vcom "$IP_DIR/../altera_jesd204_1920/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_jesd204_1920_humwsma.vhd"   -work altera_jesd204_1920
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
   vcom         "$IP_DIR/../altera_jesd204_1920/sim/ip_arria10_e2sg_jesd204b_tx_altera_jesd204_1920_xrjkkdy.vhd"   -work altera_jesd204_1920 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
index 7e2c7b6c993ca124d3f2424e705ca0dd411a34df..a5d2dffcdc9f0cc65220a86dc61a67a273d9a647 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
index 9fd2ce4a80c890da419303cd1e79ad8fe898c5eb..2a83b600c4a4c32267a61e3e801fee37dbe5ff88 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
@@ -30,10 +30,10 @@
 
 vmap  altera_jesd204_phy_191           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
   vcom         "$IP_DIR/../altera_jesd204_phy_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_jesd204_phy_191_qtzjdri.vhd"   -work altera_jesd204_phy_191
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
   vcom         "$IP_DIR/../altera_jesd204_phy_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_jesd204_phy_191_iu47x7q.vhd"   -work altera_jesd204_phy_191
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
index 7a3f243be3fd335fef577676156c69b02da81744..0cef42c20a98d9447216fb167684f1958c96f9c4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
index 24d021d788ba02269c63ac79b09d7a48811b9db6..be638256e0edf6373bfb67eff67e501b5f7c25da 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
@@ -30,7 +30,7 @@
 
 vmap  altera_jesd204_phy_adapter_xs_191           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
 
   vlog         "$IP_DIR/../altera_jesd204_phy_adapter_xs_191/sim/mentor/altera_jesd204_phy_adapter_xs.v"          -work altera_jesd204_phy_adapter_xs_191  
  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
index 019f8fa154a10ea1689f605868c2ac9d74d4479d..85d31379e2ca04f823d6a2226dbdad1e29658f5a 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
index fda853dc06b0251b06d9025ec857c84d9ca11c72..4a9c9506dbb8626f886bdc8fe8d02e05d4665091 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
@@ -30,7 +30,7 @@
 
 vmap  altera_jesd204_rx_191           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
   vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v"                -work altera_jesd204_rx_191   
   vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_csr.v"                 -work altera_jesd204_rx_191   
   vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_ctl.v"                 -work altera_jesd204_rx_191   
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
index f1cbfa6e1be20d92eb261d39f06ca1f9a54c986a..de7eeb1be7d3d6383d784f806f18d671bfded022 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
index 7c98851c07679f4b153916791c38b20d0f7ec759..0cede8fb11d09dd40813a1e179d2c1889728dcee 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
@@ -30,7 +30,7 @@
 
 vmap  altera_jesd204_rx_mlpcs_191           ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
 
   vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_8b10b_dec.v"          -work altera_jesd204_rx_mlpcs_191  
   vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_rx_mlpcs_191  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
index 1a66738823cc329530b7d8aa5f88029bd67fb13d..c3911c4f9b22c1c108d51f76e90041f7cc7466ba 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
index 2dedec0639be7abf5f49853367bfed27dc0396cf..f0d6789053335f25026c4fc78aba6ae1496ccd62 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
@@ -31,7 +31,7 @@
 vmap  altera_jesd204_tx_191           ./work/
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
 
 
   vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_base.v"          -work altera_jesd204_tx_191 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
index 175fe361dadb1d5b0bba9b2daa3fabd64dce856c..c213dc409db0a198e3c50ccc9713d22a9356184b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
index 060df7feea16ec18e67f989fb0d56522b1111aac..97381478a41fa97e526ccebbc419a2d1a25628fd 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
@@ -31,7 +31,7 @@
 vmap  altera_jesd204_tx_mlpcs_191           ./work/
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
   vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_8b10b_enc.v"          -work altera_jesd204_tx_mlpcs_191  
   vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_tx_mlpcs_191  
   vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_pcfifo.v"             -work altera_jesd204_tx_mlpcs_191  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
index 27f636b09b0e7153e3752ad9a3bc9fba84682b63..b9879ac843f23ab4b3b65b3f5a93fb041b1b02d4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
index 924628ab6f768bb2fe5170abbc889f18dca479dd..8d3e1b4e1890ee0e0a68aa88ea40d7512dce1b8d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  altera_jtag_dc_streaming_191          ./work/
   vlog      "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v"                                             -work altera_jtag_dc_streaming_191         
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
index 50e59bccc7e2a1ddcd8f912a14da7c16eddfb0bf..cec06d2e028fd1990d33d7d1c87391a07e9995ba 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
index 83823e0425236c0e30bddde595d518ccd9fb82a8..069822f13e5a34bd290f2517e1a69573882df4e4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
 vmap altera_lvds_1930                 ./work/
   vcom         "$IP_DIR/../altera_lvds_1930/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_1930_7egaewa.vhd"                -work altera_lvds_1930  
   vcom         "$IP_DIR/../altera_lvds_1930/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_1930_w33qkcq.vhd"                -work altera_lvds_1930  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
index 73192d67a858ec01f75c46856e59e6494fb549d4..abee9b51f29a676659c9954614f90d97afc35468 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
index b2d60572fedd92d34b0a2553427b6b73f3fdcadf..d3580dc299f6b2e357256ac8b02f618143bdcef4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
@@ -27,7 +27,7 @@
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
 vmap  altera_lvds_core20_191                ./work/
 
   vlog -sv  "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20.sv"                                       -work altera_lvds_core20_191               
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
index 475ac60eb42e946304848dbc5ffe6f86bf922e7d..7eedc2e8b1f71662eb0ac2b9f0a3b12591591181 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
index c98fe5bf241bc5822d1f010c72a40abaa683dc7c..9d24715fb0da5a99e3cc30c9f10ce5f8ec5acb08 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
@@ -28,16 +28,16 @@
 
 #vlib ./work/         ;# Assume library work already exist      
 #
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  altera_merlin_master_translator_191 ./work/
         
   vlog -sv  "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_master_translator_191_g7h47bq.sv"   -work altera_merlin_master_translator_191
 
 # ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vlog -sv  "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_merlin_master_translator_191_g7h47bq.sv"   -work altera_merlin_master_translator_191
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vlog -sv  "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_merlin_master_translator_191_g7h47bq.sv"   -work altera_merlin_master_translator_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
index 96a1f18f72835b1c95d663ac74605cd7135d5d30..d73f59d6e482e417f4d8c10b5b9beee00da49a0a 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
index 56f6eb803f9f2ec0c35861671af2e9af6c3df52c..f0b32531080513c0e9cd90539f646d32eb80d774 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
@@ -29,16 +29,16 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
  
 vmap  altera_merlin_slave_translator_191  ./work/
                                                       
   vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 
 
 # ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
index c3f96d2542cd54cd8164b9720e5106eb6e78663c..fc81ff2faae1d667de32498a072131657edd34c5 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
index 7d2bdac3477728b18fe38b870156dcd13d1aed1f..492c5ae0c43e5efd222c49688d44b19636ca4ec2 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
@@ -31,18 +31,18 @@
                                                       
 vmap  altera_mm_interconnect_191          ./work/
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd"             -work altera_mm_interconnect_191
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_3yb4cia.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_monheay.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_dexdb4a.vhd"             -work altera_mm_interconnect_191
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_3yb4cia.vhd"             -work altera_mm_interconnect_191 
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_monheay.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_dexdb4a.vhd"             -work altera_mm_interconnect_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
index 2ddb7be05602d7f9405d1054c51142f5387fb161..6fdd884a0f944edc6dfa01d7dd19d0da4fb1473d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
index 674161ae5ece6f98194c85df0ed45301de9f85f2..9b124aeee40aa003c243d361ed26215b2b3a0b39 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
 
 vmap  altera_remote_update_1910      ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
index a2f283a8aede6dbcde55a1179273fa3b4bac258d..83a19e1b246e72236be1eed67d13ec305050deaa 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
index 00107fb7202c55df8c8d2a9581eef5045d1c7f96..41bea969d2a7353840feacfd2ed38f9bcc3d3143 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
 
 
 vmap  altera_remote_update_core_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
index 8e1035e07542a46108ca17663a0ebe6485b4ac80..40bf22c31b8a243034de98bdd7811a45bb19ec51 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
@@ -9,4 +9,4 @@ synth_files =
 test_bench_files = 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
index 1f4efd6bea044d87b79c503534f4889deebadaa5..54d6f0d11ddb41a24630f61eb2fe653e727482e8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist      
 #
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
  
 vmap  altera_reset_controller_191         ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
index fb7cfdeab2ad303c80779772060156dbfeb64aa6..94aa5e58861d16f65d1a988dcddcfd2a249d0714 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
index 20acf8a3b7153b8f53315f2f740b7d7f6e04115c..5668f65951b7bce29601bfc8ddcd3d775cd1ef34 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 vmap  altera_reset_sequencer_191         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
  
 
   vlog     "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_controller.v"                -work altera_reset_sequencer_191 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
index 74ffede0c2e7bac51a55bf87eb479c66c8cb99a4..c97dcfbd0e1b8f6da0097916a8d219e616acfded 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
index 34e8546b799c343698618ecd71ae47e0e1577edf..9a48a1d3ec0d39d64c5a55605e02f5216176c2fd 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
 
 vmap  altera_common_sv_packages           ./work/
 vmap  altera_xcvr_atx_pll_a10_191         ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
index 8bc95d11ae128bccb78c265a48f9719944ee7ef7..403fb400459baf9add480d00d7f8e86195a88670 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
index 93a8770a67536124874c64ce9b732c2a6c5055a5..263063868eba95b59c68e320230c1e4740495c8f 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
 
 vmap  altera_xcvr_fpll_a10_191             ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg
index 9d51eea5a35ceebb753de0ad11df7df63832de41..55e602c9fcdb15f0fc6a81bf5af7a0a495b69f3c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
index e8a8b744ffd4c43a5bc1628abfdb805c0a2ab153..65bcc42ce730f6a6707a1fedc4028c1fd99f9ba6 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap  altera_xcvr_native_a10_191       ./work/
 vmap  altera_common_sv_packages        ./work/
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
 
 # common dependencies
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv"                                                               -work altera_common_sv_packages       
@@ -68,41 +68,41 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_x2zy5gq.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # phy_10gbase_r_24
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_xj4rzbi.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # phy_10gbase_r_12
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191      
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_vvjuhsq.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # phy_10gbase_r_4
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191_nx522la.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_191     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_nx522la.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # phy_10gbase_r_3
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191_ofoefcy.sv"  -L altera_common_sv_packages -work altera_xcvr_native_a10_191     
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ofoefcy.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # phy_10gbase_r
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191_ng5d5fy.sv"    -L altera_common_sv_packages -work altera_xcvr_native_a10_191   
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ng5d5fy.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191 
 
 # tse_sgmii_gx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_xcvr_native_a10_191_fbxkdmq.sv"     -L altera_common_sv_packages -work altera_xcvr_native_a10_191            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_fbxkdmq.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # jesd204b rx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_191_pebno5q.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_191            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_pebno5q.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # jesd204b tx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_xcvr_native_a10_191_wjipjey.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_191            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_wjipjey.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
index 534c0be3c2776e8d79a0dfca24f35f9d0afc62e5..cd422900db9e1165c4f5c39199dc0cf1afe59ce6 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
index 042ffaf53677c362ddfa4012f5398c523d462263..e3253b9e54e2f0d392666862423ae292bb6ebd83 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
 
 vmap  altera_xcvr_reset_control_191                  ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
index 491e0f63367356422aec458fe1dbe545f878a07f..2a93709c429d47e3818661a22e3c0bf16c0e47a8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
index 39828d81ea79a18a8433195dd133b677b5b3737e..142d72c9079008ad28ea6651d7cfad6eff07137e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
@@ -29,12 +29,12 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
 
 vmap altmult_complex_1910 ./work/
 
   vcom  "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
 
   vcom  "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_27b_altmult_complex_1910_ecifj3y.vhd" -work altmult_complex_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
index 3880a880c2d0606923a8551ca6a4fb7c4407848e..ae671bcf73534bf57c0d449d0ea4c6e2525428f6 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
index f353879770158c680a5df433fb00e25216ad0ba9..0f50ea7b02e236e2d97c906f3a629d4e1409120d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
@@ -30,7 +30,7 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  channel_adapter_191                   ./work/
 
@@ -38,12 +38,12 @@ vmap  channel_adapter_191                   ./work/
   vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_191_uc27kqq.sv"    -work channel_adapter_191              
 
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_channel_adapter_191_cco4x3a.sv"    -work channel_adapter_191                  
   vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_channel_adapter_191_uc27kqq.sv"    -work channel_adapter_191              
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
    vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_channel_adapter_191_cco4x3a.sv"    -work channel_adapter_191                   
    vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_channel_adapter_191_uc27kqq.sv"    -work channel_adapter_191                                                                       
  
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
index 88a5792a4cec3fe87c69e209689762497addd60d..5e364403a37d2b1daf07273d8196a327874c13ab 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
index c3391288492d335e62dc7b415c653eafac48beff..607a591d1c4e9b703f5aa897219740b727b3e44e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
@@ -30,18 +30,18 @@
 #
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  timing_adapter_191   ./work/
                   
   vlog -sv  "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_timing_adapter_191_rrgemwi.sv"  -work timing_adapter_191                   
 
 #ddr4_16g_1600_64b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
   vlog -sv  "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_timing_adapter_191_rrgemwi.sv"  -work timing_adapter_191                   
 
 # ddr4_16g_1600_72b
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
   vlog -sv  "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_timing_adapter_191_rrgemwi.sv"  -work timing_adapter_191                   
   
                                                       
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
index c9632755d6806adf04140fc59c6b0ba9f3e54511..6596692db8ad1c41e0d69693784bbbfed8f3f93f 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
index 1f8b03270d5107bf7f50aa5701219c59c3fcfa87..0348ce429958767345640f75d1ddd926482d969d 100644
--- a/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
 
   vcom  "$IP_DIR/ip_arria10_e2sg_clkbuf_global.vhd"                                             
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
index b2efd5ef0fb096c9ae965d25f5a790613c525450..db471cadfb34174054284875879faac183d167f7 100644
--- a/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_clkbuf_global/ip_arria10_e2sg_clkbuf_global.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_clkbuf_global/ip_arria10_e2sg_clkbuf_global.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
index c9a33bbdfc0710640b0f4e967376ce8a5627e40e..2e863c2d4bc14d7e9cd91d360150bfc69e948cda 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
index cc565f44e87cb7f58bd2efde48a9b764ca3da5d2..885e2180ad220dbc6d883af5aec5319fdd4073d7 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
@@ -29,9 +29,9 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
   vcom "$IP_DIR/ip_arria10_e2sg_complex_mult.vhd"
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
   vcom "$IP_DIR/ip_arria10_e2sg_complex_mult_27b.vhd"
 
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
index c2162613d96f940cea3d3be82cd5713a76a5eda9..bcfa7d31abdebfa71a6cff9e1f60fe0ac0932ad9 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
@@ -11,13 +11,13 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult/ip_arria10_e2sg_complex_mult.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult_27b/ip_arria10_e2sg_complex_mult_27b.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult/ip_arria10_e2sg_complex_mult.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult_27b/ip_arria10_e2sg_complex_mult_27b.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/README.txt b/libraries/technology/ip_arria10_e2sg/ddio/README.txt
index 1823e822ffac72fd6dfccb16917ab9972bed2a75..7ea3cfffa4c932d75e3ec2d52c01d41e8b1fc5ad 100755
--- a/libraries/technology/ip_arria10_e2sg/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
index 47f7f739d8e509a81e8229944922c62d3404e9b5..dcdf1277683d338702bffb0aa057b512f8ed7ddc 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} { 
     # OUTDATED AND NOT USED!!
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_in_1/sim"
+    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_in_1/sim"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_191  ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
     vcom     "$IP_DIR/ip_arria10_ddio_in_1.vhd"                                                                                               
 
 
-    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_out_1/sim"
+    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_out_1/sim"
 
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_out_1_altera_gpio_core_191 ./work/
@@ -60,7 +60,7 @@ if {$IPMODEL=="PHY"} {
 } else {
 
     # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
-    set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e2sg/ddio/sim/"
+    set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10_e2sg/ddio/sim/"
     
     vcom "$SIM_DIR/ip_arria10_e2sg_ddio_in_1.vhd"
     vcom "$SIM_DIR/ip_arria10_e2sg_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
index de54715d174262878a4e05717035444a6644a34f..6b69fa3fea5dbc07c17c1414691d41d0238d0663 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
@@ -13,13 +13,13 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_in_1/ip_arria10_e2sg_ddio_in_1.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_out_1/ip_arria10_e2sg_ddio_out_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_in_1/ip_arria10_e2sg_ddio_in_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_out_1/ip_arria10_e2sg_ddio_out_1.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
index e37e82f8080b33986b609e906bde5c530d69407c..dd80bc54a49906a6be01e0967bef58bda147d8b5 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
                     
   vcom         "$IP_DIR/ip_arria10_e2sg_ddr4_16g_1600_64b.vhd"                                                                              
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl
index 7e60bb27c51a8b43ba2c20bc1ef394aa3e0e2ea3..cce047a3565edab9a40116dcf325fc98cf4bf754 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg
index d7cb9b0f2ef7410230433805d47d7d6330793fe0..72d7324ae78b32b66a1b19814c6e63d0dddf22ea 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/ip_arria10_e2sg_ddr4_16g_1600_64b.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/ip_arria10_e2sg_ddr4_16g_1600_64b.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
index d021871f8ca0150fb53be48100b927cd15f9718d..c449e8db04e84ee1a8f07060fbe487651cdb4bd7 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
                     
   vcom         "$IP_DIR/ip_arria10_e2sg_ddr4_16g_1600_72b.vhd"                                                                              
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl
index 7b32ef533783b95792fd0f4c46e5f93d17669ab1..38ca19826b8c49c3bfd1d45b4f77467cb2271f3e 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg
index 7b322559d7d2fa036e715f928ad34a420680dd32..588759f4af02a96987b993c601d97c587f731f2e 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/ip_arria10_e2sg_ddr4_16g_1600_72b.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/ip_arria10_e2sg_ddr4_16g_1600_72b.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
index d88b025be7ce9f6f9b057c2d7e4d564d18ab0815..2b7d97f8b482fc40878c3a24928b9f30b695c982 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
                     
   vcom         "$IP_DIR/ip_arria10_e2sg_ddr4_8g_1600.vhd"                                                                              
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
index 3cc009c6f57631515644dee02a115d1ec0ceb55a..26a2e26754a26684eaa5be4c6594921c2625dfc6 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
index eb13535a2f69106e0e057d11e530d3b08a240233..54138be3e0c2744d38dbedb37e309559e8003af9 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/README.txt b/libraries/technology/ip_arria10_e2sg/fifo/README.txt
index 6db25b6412e89ebde6decb09c13f7e14890315b0..bcf8b55de24242e455a4481c6c64b948f0d04797 100755
--- a/libraries/technology/ip_arria10_e2sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
index 923d3754c63c8123bf538e26b1d7ba55c1644d29..d14407ec43819d25f028e97d1dd64f2497e1b21e 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
 vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
 
 
   vcom  "$IP_DIR/ip_arria10_e2sg_asmi_parallel.vhd"                                                                
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
index bb9e88dd544f8c635c4f7137b18e3d3275f1b19c..474a468c1eb0fc088b5b0ebc0d330c1d91ffa92e 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_asmi_parallel/ip_arria10_e2sg_asmi_parallel.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_asmi_parallel/ip_arria10_e2sg_asmi_parallel.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
index a0166b1708199ec0bb38af3cac4a487ebbda1db4..b09588eeedf252361be202f66eded3f05ec45875 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
 
  
   vcom  "$IP_DIR/ip_arria10_e2sg_remote_update.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
index 7f228c3292a4aa81ff38b466590cb7473620acb8..d699858547cda662671410e916de6b4c582272b5 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_remote_update/ip_arria10_e2sg_remote_update.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_remote_update/ip_arria10_e2sg_remote_update.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
index 4fe3b4783ebc95f1a5fdd8354121b8e20993494b..4ac3d050ca374447e5dac05293975b43d9ac5887 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/sim"
          
   vcom   "$IP_DIR/ip_arria10_e2sg_fractional_pll_clk125.vhd"                           
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
index 0ee356783ae798286a987b95dc84e8a36a67d965..9ee4652660a2f2793090ed0e5282e6b72662d728 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
index 4f8725a2e4aba75800497c381b74e774529e3296..cf9bd0719513a6a6f7d4242529bf587d9e799b21 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e2sg_fractional_pll_clk200.vhd"                            
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
index 0b37db4eda5bce7af1ce781ec6eb0cc37e493585..18add70cdae83bd4d7fb44c79042098f3f38eb22 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
index b970b966a7b11109d8711b625c7c39639803c899..f26e8d39ef573090f106c9515157833d5a81bc25 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
@@ -29,18 +29,18 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
   vcom         "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_200MHz.vhd"
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
   vcom         "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz.vhd"
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
   vcom         "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_reset_seq.vhd"
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/sim"
   vcom         "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.vhd"
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
   vcom         "$IP_DIR/ip_arria10_e2sg_jesd204b_tx.vhd"
 
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
index fd070965ac2464d8af95a087df022b13643318f0..0872ac39324cc51a15a130e7018926655cc0124d 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
@@ -11,17 +11,17 @@ synth_files =
 test_bench_files =
 
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
 
 [modelsim_project_file]
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/ip_arria10_e2sg_jesd204b_rx_200MHz.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/ip_arria10_e2sg_jesd204b_rx_reset_seq.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_tx/ip_arria10_e2sg_jesd204b_tx.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/ip_arria10_e2sg_jesd204b_rx_200MHz.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/ip_arria10_e2sg_jesd204b_rx_reset_seq.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_tx/ip_arria10_e2sg_jesd204b_tx.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
index c775402d02b409cbc5f046ee91549577ddf8c52a..0f920fa60eb1bb158995b720f14582422039bcec 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
index f7f37290b061064ae6303e4ce53f382935df23d6..aa5ec7b591ed22177c0b79fdf4cac2911944a6cc 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
 
      
   vcom     "$IP_DIR/ip_arria10_e2sg_mac_10g.vhd"                                                                                        
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
index ed87d3019f951a4e75fb41402d143faa0ae59021..ccb711c22644ea64bd15b54ee46c08fed0737f55 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
@@ -9,17 +9,17 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_mac_10g/ip_arria10_e2sg_mac_10g.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_mac_10g/ip_arria10_e2sg_mac_10g.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
index ea16fe38cfcca46235d81bd21154e52c9d7fd9e0..8c7deabdda4181c5fbddccac6d82472f7938a002 100644
--- a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mult_add4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mult_add4/sim"
 
 vmap  ip_arria10_e2sg_mult_add4 ./work/
 vmap  altera_mult_add_1910       ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
index 77ae9c3528d82b79d00f43e19726275fedb5a807..ea79c19262bd494116caa6147a8dcf23ff09ebe9 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r.vhd"                                                                                                  
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
index b6e2620a30c5a519a44ee21dd8704865d7e23551..59e6354d2e0e7f7034a8e59c1941dabfeb4a5e2b 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
index e3603311ebdf462074c795637f193835cc925a10..6171b4bbce0bfb01e9941131b0c018f7d95952bd 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
 
     
   vcom         "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_12.vhd"   
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
index b211cea285350937189b4a4af8e6fc3c2c189861..71711ff204b35ed08c0f093a4b351f052728a49e 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
index c1b9278620d266e5a3926578eec8685e5521ae37..944729d21148141a6cde3f5b05060ebcc6fa038b 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
 
 
   vcom         "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_24.vhd"         
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
index d3d9782e0228bda57a7ac4da933066335e74b1bd..728607161987d96b4bf068a25ed838c5bc4fb7ed 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
index 5e81bb41af29029a71012512b1c3c2fe2d1a61a5..73e98d5057b5812060d26ef7417fc57b69bb1567 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_3.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
index 4f381244ec1aeabddda0ff07ae8e9054a12755e6..c58d0c6956562dc0fedfeb17a92a0631dfc24e90 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
index a969be29f8e1d8f990c37f3356ee44cb0c3a3b0a..66f765f185bb90026a33f0e651e5ff1027776b47 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
 
    
   vcom         "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_4.vhd"                                                                                               
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
index 2f337692b2f861cf3a8f7a8493d3fc853e8bee20..0f1f0700d449bdf9bca472a11a86f3be68388159 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
index 0cd5157ee40b2b4afba70f273e3ce4a86eddd40d..955fb6426eb6d8c9c730afad58690bf0387f07e8 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
 
     
   vcom      "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_48.vhd"                                                                    
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
index 0f7ce6dd7d7042d51c02935f231695f6fbcd1f0c..861239db7d312bc19426ef8ac413b14581e7185e 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
index d3104e52cfcc79d3cbdc527a1c4f3258379ff5b5..1a3ce1dc14579efdab4123be3544c6bf7fbafaf6 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
    
   vcom     "$IP_DIR/ip_arria10_e2sg_pll_clk125.vhd"                                              
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
index 44ddc0d42fdfda3fad56703f64ff8d0d3dedf063..7d067c8f00883371112bba2ec7e6f1cf3e786af9 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk125/ip_arria10_e2sg_pll_clk125.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk125/ip_arria10_e2sg_pll_clk125.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
index ef4a13259c720ebf73155d8d51d62c5a4d99469b..935e742e0787ef233aeff75ce5a44b2f8303084e 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
   vcom  "$IP_DIR/ip_arria10_e2sg_pll_clk200.vhd"                                           
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
index b51d69c36e06699efdf26f150fbf011aa4f58bc5..f94c62b25f1107c5ed7da862633bfc920048b57a 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk200/ip_arria10_e2sg_pll_clk200.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk200/ip_arria10_e2sg_pll_clk200.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
index 284b7227b32d1e3a3ec10d0c42c9a45ee8d1d0e3..bfa6416fdc661da6ae56d6014e1d9e5454dabc04 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
 
      
   vcom  "$IP_DIR/ip_arria10_e2sg_pll_clk25.vhd"                                        
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
index b4643a3f390ada1c13954f1d7f22192bd34bc10b..46fb9069c1ea69fbd4135f47c0c74d2376d3cd65 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk25/ip_arria10_e2sg_pll_clk25.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk25/ip_arria10_e2sg_pll_clk25.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 2b7ee9fed6f9909fb0117460b1ad72520b7c0eae..99a216a6d72cad941109e609b67df27a9a4f4fe2 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
 
        
   vcom         "$IP_DIR/ip_arria10_e2sg_pll_xgmii_mac_clocks.vhd"                              
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
index 4c9dbb43ed32379ff3585cc939ffff5cf648a1d7..dfe53436952f37c50697717f911a930126c8059d 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/ram/README.txt b/libraries/technology/ip_arria10_e2sg/ram/README.txt
index 24ad4ab94e542bd2d642eaa079f4e18624d8c163..bb10b060478b5b615634aedfea779ac31cbf3845 100755
--- a/libraries/technology/ip_arria10_e2sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
index f7bf08e5ecea0e8639431ab5b19f90f338216121..8734d79939cdab8d774b0b1c88397ce07a6c8fa4 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_temp_sense/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_temp_sense/sim"
 
 vmap  altera_temp_sense_1910      ./work/
 
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
index 346ed99c7996f5cb0454f3e402ec5179479003de..d60dcd8cb37cdaf0e81fbd4a84be4d00b1d979fa 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files = 
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_temp_sense/ip_arria10_e2sg_temp_sense.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_temp_sense/ip_arria10_e2sg_temp_sense.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
index fb04e579cf4beec06569ffc587aa25476ef515ab..cff9d462ddb421b73eb4007baee13e8b35508ebd 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
 
   vcom       "$IP_DIR/ip_arria10_e2sg_transceiver_pll_10g.vhd"                                                                                                    
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
index 3883ef2edc2c2a299c0a030db27bee57ee98e3bc..da176b5e2d41d724904d4ea24013f015fbb2a92c 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qip
 
 
 [generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
index acd0d01beafdf9a36f59f649285fa21e7a6e2bb6..f7b9790eb849c79d32eb6b809cf3ec0b2c97e153 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
 
                
   vcom         "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_1.vhd"                    
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
index 6d04b9ceda1aa964f20c87583563c94e033ff047..afd333910fa674bb2babb136748e36bf8b9dedd9 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
index e5371e0872f8623555348a631ced65524bab8743..07b0a76b7ac066f43402ad1e9e707fa8002d964a 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/sim"
 
   vcom         "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_12.vhd"                      
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
index de8a07ce6b8762eeecec9ef4d5be305d4a92f822..729d6026b9c623f4e558a1beb5f2e6c5ad4f0501 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
index 5bbfb9dc8a990657cf60f8c99de0bc4118021b41..a09ecb238ff122de0c9465b76840eb7ddabea200 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/sim"
 
                 
   vcom         "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_24.vhd"                    
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
index 1769ca01f58a4454eb1767de68a6845e3237eec4..a51aa93ac3e2587f4ab9d01b52336a646be46206 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
index aebd7ffc4380dabb3247066427752b3d60f9958d..dc4fd31164efcfdf4079f0c0750f058ce5d26999 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_3.vhd"                     
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
index a2612ca5c3ac497f37b8e1608a4529914601c0af..9bb94ac6ebf40de158cac6adba05d8b27a3fc687 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
index a0dddbff50147a52eddeb782e4516af07abf9fce..0091266d7722b7e2b5472f2e229d31b7858af57c 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/sim"
                 
   vcom         "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_4.vhd"                     
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
index 2854213ec43d0ef71038079ff5acbbc8b9230127..a54de5d847b33f8d93a0b0b0039910290dc0a158 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
index bb2f21d04ed3c93a447951c8676a4ff3010b772e..c3771cd87b9a6220501d80fbe0b06fe1b6fe1396 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/sim"
 
                  
   vcom      "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_48.vhd"                     
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
index 4a07513526282f07d11538976177ff41af201aba..0e53b9ead40fac90fb1e8fc8e57dba5126b2cad5 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
index fa105db173e0dc963f59b1e10b143cf5cc782167..8b2022353701472bac9f6210d3711db0e1f06574 100755
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
 
 The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
 
 The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
 
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
 
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
index 72131625fde500fcb42c32616d5f52925542f538..5d270f7373d191e4ac9d174db4dff9811f3d60fe 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
 
   vcom         "$IP_DIR/ip_arria10_e2sg_tse_sgmii_gx.vhd"        
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
index e507db9acba22696372f25597bfd600f8414e59d..cd126f4a8e9195218228223f6ea269c47cf45c9d 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
     
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
index efe749e3a03ff7e95c29fd5bfc6bb62ae55040a2..2272417d950803e9bf009b24dc20bc41ba38a416 100755
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
 
-See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
   
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
index ec4f247a9caba7327656d1b02ae2247645e05a57..0da01d1c74d53ea60692cec6846de8ad131fed43 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
         
   vcom         "$IP_DIR/ip_arria10_e2sg_tse_sgmii_lvds.vhd"                                                                 
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
index 25bd4f45551365f4d2e0dbe15db1dda870b95945..22fcc1b2b1da196f51a8ea7c1120db54a0a0f752 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qip
 
 
 [generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
index 1b8ecbf3fa6859557dfbd0a0e73c959b20f04e70..138997c714f52aedebe229e2927a80a0f5a6e432 100644
--- a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_voltage_sense/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_voltage_sense/sim"
 
 vmap  ip_arria10_e2sg_voltage_sense          ./work/
 vmap  altera_voltage_sensor_1910              ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
index 6414fcd8bca7fb0a1203e4361ae33f1e1bac417b..c8da4f7b011d1d759fb0eb5114f48c71c07ab2e9 100644
--- a/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
 [modelsim_project_file]
 # There is no simulation model for the FPGA voltage sensor IP
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
 
 
 [quartus_project_file]
 quartus_qip_files = 
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_voltage_sense/ip_arria10_e2sg_voltage_sense.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_voltage_sense/ip_arria10_e2sg_voltage_sense.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index bf8cd80c93a7860a1697ac526a57157b151b6842..7ae5ccdb0110507c116a5516c53b54a7644de291 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index 109d6d33f6e69eeb5ff6ea97c62d103cbe51ed8a..79113b1143ec7895efe714928977031df7e2563c 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
index c9a33bbdfc0710640b0f4e967376ce8a5627e40e..2e863c2d4bc14d7e9cd91d360150bfc69e948cda 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 9d3d77809588700d590519cd1596b2ab44add79d..57832897c9e03dacb771638be58eac6e5f950b5e 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index a9a34dbda047cd800f4a536b461a62de82b713b2..338c4d6556de3b8f3cd2b4d1fe6696b87adc1094 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
index 1823e822ffac72fd6dfccb16917ab9972bed2a75..7ea3cfffa4c932d75e3ec2d52c01d41e8b1fc5ad 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index bf52569332beb12035486d9477909efde4f0d22e..eaf469f3cdb80fe86e34fabfa3ecfcb5910f8555 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} {
 
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
+    set IP_DIR "$env(HDL_BUILD_DIR)/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151  ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
 } else {
 
     # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
-    set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
+    set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
     
     vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_in_1.vhd"
     vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index 5c041edb861d2ce9b4b87e35ee81629134c6fa2b..b454aeb4e33f5aa4b11c7a7115f3bb186bf5d3cf 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index e62b5e5b0ec2ca57c94a7ab5b9d13a8a9f993b0c..f9daedf909c3374e88c54a2db2a5788038997cdf 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index ffac688997df0844310121f869edb099a0f7b893..960d695d93ac14ac14d9fca19cb02da3dde50874 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index dd9a5269ec2975720a5adb4402f5d17b2a6292d4..5578d5083b733523b2ed9b1fa62a75ca07e75233 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index 5af54448735656b71c72ba70c8ea9abda0030c03..4958df3351a1a1f8f3802460d8e7f0321d2f2917 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index c7dc9753f6703576382161215eaf38894884de9b..9ee3836145e3eeae78859b7d60f8325a0d8d0848 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index e973cfc298313ed0bb5e3163f94eacd4b9b0a4f0..58da6ad396a67c0f706778f7b7445feb4125f49d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index 9235dd757d1c734c7100d95ab966a22837ab6b6d..f1b453f200164d5d78459ead9a893ce00b1db24e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index 50bcddb253056ba6151939404cb7a8087772998d..04c2a8b4be31e4d5f5ef249a650466322d8b90f7 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index f8c58abd7306b4b20930834c6dd1037463b66c29..a2707c8733f0f7dc9839ea08b92ab77f7e7368d2 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index 6ab71a395bb7b1e3e7d06d446983253e205c110e..ce6a73617cf8953e1e92e06aed99720360d50beb 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index 7017bd16807f790d696cdf8165fb677c09c390bc..aae9b7d9c164ae06e67a2c7f461da36003ebce98 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index 61b0187261993f78a56afb9aa4432fcb871c4724..3cab8b771d430df159d6d700d618b09762602e34 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
index 6db25b6412e89ebde6decb09c13f7e14890315b0..bcf8b55de24242e455a4481c6c64b948f0d04797 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index bdfa521c2e6ecc238bbde399fb49198e91421278..dca4f15724202af79962351ed84c4c74b7e698ff 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
 
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 8158007cdb873e2d4e2ab3ce592fe8f529c1cdba..47aa7b1f73b239e5615975ad96359c5dbf87dd8a 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 3ce459025cc583a84317805d0d834f9a99f92364..74015b629d77fa5bb93635d791d424e2c431c3e4 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151  ./work/
 vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151       ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index d86f360f5343b5477c35ed1eaffd53207cdf13b7..81a791fca234ac29fb491f4502fc352d4ca02574 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index 644fcc2174cfdc4be4fb1a61a7a39c99ff51f2bd..7e094e9376d12c2d669bd1f866df2cc8e050d012 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index 3206621e21ad428d93007250e5f8b547abf67029..a943ad1b82041a5c9cacd4f06bfc6a37a51b0226 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index c74c2287408f1056c710ee8f3f4919c6b978c3ae..c0daa81c16aead7d28d9c9c4a02a89d671be52e7 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index 8d98ad13a49efc499b251b8f19b0f90a616acf2d..16bc3c0bb0eb8949833b9ebafd6619aa71c289fa 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
index c775402d02b409cbc5f046ee91549577ddf8c52a..0f920fa60eb1bb158995b720f14582422039bcec 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
 
 1) Porting
 2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 652e8572667600fc7ffe8d9af75e567441a6835e..5567b55fb3ecb22e5b70bf65468cff275cf57dd2 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
-set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 2395b80019ba2a23b3ad696cc19a94fe3f2e5310..73453ccd6f6e9c6ad2d20a6cfea4097b92902953 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+    #$HDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
 
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index f4812de719ae2432daf1b2136321bbf4c5c830af..9f2c5442d710666ca8ab4049d336979fdafc104c 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index bac46a302542d23df2b48e95b334e174592073bb..e27cf86d7f2e8c9c5aff9ebccdeb94f396559222 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index 8e7bc5b458b44fcbf572c6c0fbc7369b885366d6..1666045e3fcc6f073e67625df1b658b3651e78b5 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 845c5bc4dc96a15673a1beae9442e550c2ce0461..4d2d833dae507da920d09319c4b44fda9d976d05 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index 1f8b843ee0e885c212a83cedd2b062461c58a7ef..af90b2ceabe48deae56788ca0a6ba0931f71680b 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 52b235c6fcc56d01e23f600b679f612c623e2a13..26ba984cb5036540586ece8045005736f2841a36 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index 189f75540261952924676637fab2d899555a4eef..eca36fd33d3f65ea9b21f16737a18632305b9586 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index a1a50b1517e457f5de611dfafda1d454f0098099..76743709b4c09aebff7c4cdf62d95de2aa1f831b 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index 16bfd7165f750dcb58664297ccde118874795f76..83a8521a6e58b813106f3c4bbf03f7ee1af2da96 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index 55c73ea9afa9b28c71305785104bf7c394b6fbfc..f80ddb5a8f5ef750d79362407a6fa7c6a1f50805 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index 7c697c657220366c271679dfa03484443286dce6..110de8fc611b9ec521ae3846bbd3e4cedc440e31 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index 0f450fb1fb2068e521e2419cf34ac571b826bce8..cdad30ae363b2c7919319f57edf6f9ae3c05282e 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index ed9baef7c276d80213e9ee9f83b734acdc1ef283..125973f6df336ee91508438ad4037ae6a53cc1f0 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 4596b44c787b38044a3ce96587702fc3ea42c746..1e38e5900f4698bdf951883342899bdf381249e4 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index ca6a0c6d8bcaf01250aad3e0b1c575c7a0fb98f6..0ef6b5812bf01123b0a43559260a71d441df28a8 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index 6b08a6749e9ad8aec693df93ea7fd05f06ae8475..fed8a5ff9a11c0fb8a76aa9943bfdec3ab112af2 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index 77d805a510d55269397e2a21e0f5fcf7d54b6e2e..935fac281b5074d93f64b3e6a2ccb5cbd1b14b1f 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index b165f8ec1162f64706d063d64920cf8eb4111265..10417d22caf3d49fad2250b27a92af6e1c837bd4 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index bb1bcd9a4f1102d16b6c3fd34a8a43f342f89bc7..dcdf033830c817684c6bd5c3947a58fb729b243a 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/README.txt b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
index 24ad4ab94e542bd2d642eaa079f4e18624d8c163..bb10b060478b5b615634aedfea779ac31cbf3845 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
 
 Contents:
 
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index 5453478c58970fb5e877ab1e2b8a7c492aa9725d..350a3674c84ac54768168ceb712b6ff2a8ddb292 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 8f96a5f7bb69eea60f9d3a9f6ded0dede3641550..d843b8899a6bb2b05070d91160966b9517e9bb94 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index fb2a92dad8ae293a93969f9f5aed73cdcbe2d9b9..e16ab1bb84c6316da9dfc49018ba573bc2b95a77 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index afd34643a6205c784885b1f99810fa3d2ae787ed..c989e42aca3f12cc28793e4ba3d6d1f987f3fba6 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index 54b0b19176acc00bc244f13a55b8f1df88066d77..824d03bc0cb687920db589d5f8ea78d4f8560d98 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index f6fbacfad75630fa73b904381d4b085fed7f106e..8f024422861ab5ba1ed4393e2f24e9798b4086cb 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index ad26deea9322f9d42db7aa499771b957a181fabe..b674c73aa85fa7158f0b197728d48ec5b4e03671 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index a0f8d7cfba9c5fe142cfc0b4feb676dae5a5ca14..88b05a011d566cedd36f089afb2f691c08516d09 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index a1afcf294250b25a461c3a81bb59f97dd6d38eb3..d9cbccb13916af9d956f2cfd4599dffd5adb1e36 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index a1b6720a8007e8c8a9ac5be26ee23faafcdf33bd..b6a376782fd776015c6bc8acce2becbf96d640df 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index fb291b27e4d4d9f54eb8a0c5e6e3635510b451f8..f2d0fa88e704a22ac8413b19035bcbfa706dfabd 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index 79a61988aa6ba09e885b18851cf9c110f50ea3f7..9ce9710164a5aa0c5fb8343809b387cd92e3011e 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index 41414481897ae78573b47195fa70475fdca94790..84ad7eb84803cc22e84de6f2107d5db4a3761297 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index fddd592bd0bd0443933331ebe8b8a628abeeb125..9ac085cabd0cfe70149354fdb5e7d26f6a9f26fd 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
index fa105db173e0dc963f59b1e10b143cf5cc782167..8b2022353701472bac9f6210d3711db0e1f06574 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
 
 The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
 
 The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
 
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index 124ced04c46847a261fd34787276c34cc47f597a..216ad6395efaab77b402e3772713ca874f202a96 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index 9745670627b54edab6625fe19f05163fbd0e885b..b914d37c026500597b2ccb340887cd8534600b4a 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
     
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
index efe749e3a03ff7e95c29fd5bfc6bb62ae55040a2..2272417d950803e9bf009b24dc20bc41ba38a416 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
 
-See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
   
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index f6ae1988b3bb03f0f934553df7c61505a06a108e..add9457301889430396ec523be3c6a3948e1ff19 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
 # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 1f2692dc301256fb90cdc53bab628aa3944f33ed..48b8e5d73dd54c4c9ebb8c9db85a70aaf0d9ffb9 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index 2e88d7082a8dee592125afd2206cf5ae9f94e951..090df9c5c970cda1729a1d4f14a1ad3d2b96691d 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR   "$env(HDL_BUILD_DIR)/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index 77801114c9b0760f52b341b03fcebe2ed4d91545..96e7557c6baf655bddac9f66fd9e421ce333905b 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
 [modelsim_project_file]
 # There is no simulation model for the FPGA voltage sensor IP
 #modelsim_compile_ip_files =
-#    $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+#    $HDL_WORK/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index a2129d9a99fbc73df2def0410fec51f4e143e4af..f3d535487c60fe99c746e654c6e09ccf7a27557c 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -23,7 +23,7 @@
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
 # Get the memory model for the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
index 4b428db9638ab2d3c81cdeb69b9c53ebe7ac92f2..d8233db8ea4e592010773731bb16edb96bc2c291 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index 0cd94954d84f08aaaa3e6f3d4fa7413a56eb60cc..0cba85661da782f1018dac1256b37ce01128a5e7 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index d73de176a4e4528412132468a9617fd9acf0ba43..c62e33e6542d97c0afd5710ed102b21c46b996fb 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index 56142bcee051639f84ee9d08c8ce694570dcbb04..098694698b25449f0c89e93c6ebb5a552e635ced 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index 182467d01b17a56aeea08094f341d59925e91b01..0130afea23dfba3cd3857bdb6b6ce45204bc2f89 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index f3f0232211be40a411b8f9051d31dcbc5a580d31..aae001963a1666ede237e7d4a4f3879f8747cab9 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index adec7b0329c573111c3f04d2598b44c6ded23d79..7a6d61ba17878ba80982869501428a400106e309 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index b248f5b52c5effb708991a84367db7047b3c3a13..100507af6ac9d66860d3515cce14de9b0d6d6018 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index 16afa271530c6722b7ded9fa3a890288ece0e45e..96244d1526a14cce781676867953c8e7a7a4b5e3 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index 8391e40fd9e4df2ec9f076a6f635ac7b4476d8f4..84368ca1a7e9513dbe799d5e7cec07ecb2c4b8c8 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 3941d3de8cca0ca760403391bd31e6056403d596..84678948ceb14c7d67f200944ea17387669da202 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index 0e72fc7b5348808fb86070e500f3b80681c38022..6a06571581b76225f3950e55aad925a7bb8b8a8c 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index e59e8b5ca01e5156790364cc7011cda38e5a909c..b1ea4716a92286994dc5058016815a7a03840596 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index 59118cab74016c69aff32a1edb2d96647ed21cce..ca5ef73e8666aba7af7ecc6b4bb7a8088ae62929 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
 
 # Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index 3f69d05466561abe71d506c79a3d6952a6be20b0..755278c8493e3aee82e075c5c9c660581ef38ef7 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
 
 # This file is based on Megawizard-generated file msim_setup.tcl.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index 806cd417be752174015339438584299d42cf0af1..c2bc27298a00c4af38c91fd090d7ac7cb76cb49f 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/flash/hdllib.cfg b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
index 31d0dceb881b16597685cfac93c06272e8fe172e..a6abdf612ba523d7dcafd3a3ccce8cabf7fddc23 100644
--- a/libraries/technology/ip_stratixiv/flash/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    $RADIOHDL_WORK/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
+    $HDL_WORK/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 1a23512475600b3c92c9993885b2f546701c009a..8133ccc7f4a321a55c1e08d79c23843be17a72b9 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
 # file msim_setup.tcl.
 # tr_xaui is the first module I did this for.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
 
 #vlib ./work/         ;# Assume library work already exists
 #vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index 47e15241a44bca39c627542497dae602dfb123dc..6ac6b58969391bb4d329889ca4d88eaf87d5588c 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
 modelsim_copy_files =
     
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index 72ba6432812883235936295c64978558c0268fe9..3318814203f8331a9e088a57d8fec68ae9cc9284 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
 # correct compile order).
 # EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
 
 #vlib ./work/       ;# EK: Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index fb8eca101ffc7543a7edc6b661298de98dd06531..7e223040ac5a77da850fcf76c456371f295e9dbd 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
 # correct compile order). Bonus of this is also that there will be no errors
 # when making all_mod without having run the XAUI megawizard first.
 
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
 
 #vlib ./work/       ;# EK: Assume library work already exists
 
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index ac4ee7014d1b5e7aa4680c1b529972eed67c1f09..f8e68802122e63eb2c0eefb5327f771d64001224 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -21,8 +21,8 @@ modelsim_copy_files =
     wave_tb_ip_stratixiv_phy_xaui_ppm.do .
     
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
-    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+    $HDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
 
 
 [quartus_project_file]
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index 2455289038abd04dbe8db97cc146fd94713f397e..3ecd647ba5be5f4b0781b748fa63fe7af432a58d 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Copied from entity $RADIOHDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+  -- Copied from entity $HDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
   COMPONENT ip_stratixiv_mac_10g IS
   PORT (
     csr_clk_clk                     : in  std_logic                     := '0';             --                    csr_clk.clk
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index ec3f497a8e67769cbc0c51efbf08f6a2cabc4ae7..6d568f45691b5a9864189ba50ae4d01ea284a7bb 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
+  -- Copied from $HDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
   COMPONENT ip_stratixiv_tse_sgmii_lvds IS 
   PORT ( 
      address  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -78,7 +78,7 @@ PACKAGE tech_tse_component_pkg IS
   ); 
   END COMPONENT;
 
-  -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
+  -- Copied from $HDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
   COMPONENT ip_stratixiv_tse_sgmii_gx IS 
   PORT ( 
     address  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
+  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_tse_sgmii_lvds IS
   PORT (
     clk            : in  std_logic                     := '0';             -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
+  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_tse_sgmii_gx IS
   PORT (
     clk                : in  std_logic                     := '0';             -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10_e3sge3
   ------------------------------------------------------------------------------
 
-  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
   PORT (
     reg_data_out   : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
   PORT (
     reg_data_out       : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
   -- ip_arria10_e1sg
   ------------------------------------------------------------------------------
 
-  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
   COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
   PORT (
     reg_data_out   : out std_logic_vector(31 downto 0);                    --                  control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
   END COMPONENT;
 
 
-  -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+  -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
   COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
   PORT (
     reg_data_out       : out std_logic_vector(31 downto 0);                    --                  control_port.readdata