From a7483ef47d39e045d533cdbfd2838c6f63e54415 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 3 Dec 2020 15:20:38 +0100
Subject: [PATCH] L2SDP-184, add tb_tb_dp_block_from_mm and now working with
full blocks
---
libraries/base/dp/hdllib.cfg | 10 +-
.../base/dp/src/vhdl/dp_block_from_mm.vhd | 32 ++--
libraries/base/dp/src/vhdl/dp_block_to_mm.vhd | 27 ++-
.../base/dp/tb/vhdl/tb_dp_block_from_mm.vhd | 156 ++++++++----------
4 files changed, 107 insertions(+), 118 deletions(-)
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 4ef6330876..08537b9386 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -73,6 +73,8 @@ synth_files =
src/vhdl/dp_bsn_restore_global.vhd
src/vhdl/dp_block_gen.vhd
src/vhdl/dp_block_gen_valid_arr.vhd
+ src/vhdl/dp_block_from_mm.vhd
+ src/vhdl/dp_block_to_mm.vhd
src/vhdl/dp_bsn_source.vhd
src/vhdl/dp_bsn_source_v2.vhd
src/vhdl/dp_bsn_source_reg.vhd
@@ -167,8 +169,7 @@ synth_files =
src/vhdl/dp_selector.vhd
src/vhdl/mms_dp_scale.vhd
- src/vhdl/dp_block_from_mm.vhd
- src/vhdl/dp_block_to_mm.vhd
+
tb/vhdl/dp_stream_player.vhd
tb/vhdl/dp_sosi_recorder.vhd
@@ -188,6 +189,7 @@ test_bench_files =
tb/vhdl/tb_dp_block_reshape_sync.vhd
tb/vhdl/tb_dp_block_gen.vhd
tb/vhdl/tb_dp_block_gen_valid_arr.vhd
+ tb/vhdl/tb_dp_block_from_mm.vhd
tb/vhdl/tb_dp_bsn_align.vhd
tb/vhdl/tb_mms_dp_bsn_align.vhd
tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -255,13 +257,14 @@ test_bench_files =
tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
tb/vhdl/tb_mms_dp_gain_arr.vhd
tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
- tb/vhdl/tb_dp_block_from_mm.vhd
+
tb/vhdl/tb_tb_dp_block_select.vhd
tb/vhdl/tb_tb_dp_block_reshape.vhd
tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
tb/vhdl/tb_tb_dp_block_gen.vhd
tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
+ tb/vhdl/tb_tb_dp_block_from_mm.vhd
tb/vhdl/tb_tb_dp_bsn_align.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_concat.vhd
@@ -323,6 +326,7 @@ regression_test_vhdl =
tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
tb/vhdl/tb_tb_dp_block_gen.vhd
tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
+ tb/vhdl/tb_tb_dp_block_from_mm.vhd
tb/vhdl/tb_tb_dp_bsn_align.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_concat.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 56b129b4e6..553d7370c4 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- . Read a block of data from memory mapped (MM) location and stream it as a block of data.
-- Description:
--- . " "
+-- . https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+filterbank
-- --------------------------------------------------------------------------
LIBRARY IEEE,common_lib;
@@ -60,18 +60,22 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
busy : STD_LOGIC;
sop : STD_LOGIC;
eop : STD_LOGIC;
- word_index : NATURAL RANGE 0 TO g_data_size-1;
- step_index : NATURAL RANGE 0 TO c_mem_size;
+ word_index : NATURAL;
+ step_index : NATURAL;
END RECORD;
CONSTANT c_reg_rst : t_reg := ('0', '0', '0', 0, 0);
SIGNAL r : t_reg;
SIGNAL d : t_reg;
-
+ SIGNAL mm_address : NATURAL := 0;
+ SIGNAL last_mm_address : NATURAL := 0;
BEGIN
- mm_mosi.address <= TO_MEM_ADDRESS(start_address + r.word_index + r.step_index);
+ last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address;
+ mm_address <= start_address + r.word_index + r.step_index;
+
+ mm_mosi.address <= TO_MEM_ADDRESS(mm_address);
out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
@@ -89,7 +93,7 @@ BEGIN
END IF;
END PROCESS;
- p_comb : PROCESS(r, start_pulse, out_siso, d)
+ p_comb : PROCESS(r, start_pulse, out_siso, mm_address, last_mm_address)
BEGIN
d <= r;
d.sop <= '0';
@@ -101,14 +105,12 @@ BEGIN
ELSIF r.busy = '1' THEN
IF out_siso.ready = '1' THEN
-- continue with block
- IF r.step_index < c_mem_size THEN
- mm_mosi.rd <= '1';
- IF r.word_index < g_data_size - 1 THEN
- d.word_index <= r.word_index + 1;
- ELSE
- d.word_index <= 0;
- d.step_index <= r.step_index + g_step_size;
- END IF;
+ mm_mosi.rd <= '1';
+ IF r.word_index < g_data_size - 1 THEN
+ d.word_index <= r.word_index + 1;
+ ELSE
+ d.word_index <= 0;
+ d.step_index <= r.step_index + g_step_size;
END IF;
-- check start of block
@@ -117,7 +119,7 @@ BEGIN
END IF;
-- check end of block
- IF r.step_index >= c_mem_size THEN
+ IF mm_address >= last_mm_address THEN
d.eop <= '1';
-- prepare for next block
d.busy <= '0';
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 29929f9e43..7f2fd8aed8 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- . get a block of data from a stream and write it to a memory mapped (MM) location.
-- Description:
--- . " "
+-- . https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+filterbank
-- --------------------------------------------------------------------------
LIBRARY IEEE,common_lib;
@@ -54,18 +54,19 @@ ARCHITECTURE rtl OF dp_block_to_mm IS
TYPE t_reg IS RECORD
wr : STD_LOGIC;
- word_index : NATURAL RANGE 0 TO g_data_size-1;
- step_index : NATURAL RANGE 0 TO c_mem_size;
+ word_index : NATURAL;
+ step_index : NATURAL;
END RECORD;
CONSTANT c_reg_rst : t_reg := ('0', 0, 0);
SIGNAL r : t_reg;
SIGNAL d : t_reg;
+ SIGNAL address : NATURAL := 0;
BEGIN
-
- mm_mosi.address <= TO_MEM_ADDRESS(start_address + r.word_index + r.step_index);
+ address <= start_address + r.word_index + r.step_index;
+ mm_mosi.address <= TO_MEM_ADDRESS(address);
mm_mosi.wrdata <= RESIZE_MEM_DATA(in_sosi.data);
mm_mosi.wr <= r.wr;
@@ -82,18 +83,10 @@ BEGIN
BEGIN
d <= r;
d.wr <= '0';
-
- -- if end of block
- IF in_sosi.eop = '1' THEN
- -- prepare for next block
- d.word_index <= 0;
- d.step_index <= 0;
- END IF;
-
-- while receiving block
IF in_sosi.valid = '1' THEN
-- continue with block
- IF r.step_index < c_mem_size THEN
+ IF r.step_index <= c_mem_size THEN
d.wr <= '1';
IF r.word_index < g_data_size - 1 THEN
d.word_index <= r.word_index + 1;
@@ -103,6 +96,12 @@ BEGIN
END IF;
END IF;
END IF;
+ -- if end of block
+ IF in_sosi.eop = '1' THEN
+ -- prepare for next block
+ d.word_index <= 0;
+ d.step_index <= 0;
+ END IF;
END PROCESS;
END rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index 2f07c14c5c..d1b64a7811 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -28,9 +28,9 @@
-- . process flow:
-- p_init_ram --> p_transfer --> p_verify_read / p_verify_check.
-- . p_init_ram, initializes u_ram_rd with ascending values.
--- . p_transfer, u_dp_block_from_mm reads data (using data and step size)
+-- . p_transfer, u_dp_block_from_mm reads data (using g_data_size and g_step size)
-- from u_ram_rd and stream it to u_dp_block_to_mm which write it to u_ram_wr.
--- . p_verify_read, set ram address (using data and step size) to check and
+-- . p_verify_read, set ram address (using g_data_size and g_step_size) to check and
-- read value from ram, also set expected ram value.
-- . p_verify_check, check if ram_value is equal to expected value.
-- --------------------------------------------------------------------------
@@ -52,47 +52,46 @@ ENTITY tb_dp_block_from_mm IS
GENERIC (
g_data_size : NATURAL := 2;
g_step_size : NATURAL := 4;
- g_nof_data : NATURAL := 512 -- 512
+ g_nof_data : NATURAL := 512
);
END tb_dp_block_from_mm;
-
ARCHITECTURE tb OF tb_dp_block_from_mm IS
- CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_step_size;
+ CONSTANT c_nof_blocks : NATURAL := g_step_size / g_data_size;
+ CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks;
CONSTANT c_ram_adr_w : NATURAL := ceil_log2(c_ram_data_size);
CONSTANT c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
- SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL clk : STD_LOGIC := '1';
- SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC := '1';
- SIGNAL start_pulse : STD_LOGIC := '0';
- SIGNAL start_address : NATURAL := 0;
- SIGNAL block_done : STD_LOGIC;
+ SIGNAL start_pulse : STD_LOGIC := '0';
+ SIGNAL start_address : NATURAL := 0;
+ SIGNAL start_address_dly : NATURAL := 0;
+ SIGNAL block_done : STD_LOGIC;
SIGNAL rd_mosi : t_mem_mosi;
SIGNAL rd_miso : t_mem_miso;
- SIGNAL blk_sosi : t_dp_sosi;
- SIGNAL blk_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL blk_sosi : t_dp_sosi;
+ SIGNAL blk_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL wr_mosi : t_mem_mosi;
SIGNAL wr_miso : t_mem_miso;
-- needed for init and verify
- SIGNAL ram_wr_en : STD_LOGIC := '0';
- SIGNAL ram_wr_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL ram_wr_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL ram_rd_en : STD_LOGIC := '0';
- SIGNAL ram_rd_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0);
- SIGNAL ram_rd_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0);
- SIGNAL ram_rd_val : STD_LOGIC;
-
- SIGNAL exp_data : NATURAL;
-
- SIGNAL init_done : STD_LOGIC := '0';
+ SIGNAL ram_wr_en : STD_LOGIC := '0';
+ SIGNAL ram_wr_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL ram_wr_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL ram_rd_en : STD_LOGIC := '0';
+ SIGNAL ram_rd_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0);
+ SIGNAL ram_rd_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0);
+ SIGNAL ram_rd_val : STD_LOGIC;
+
+ SIGNAL init_done : STD_LOGIC := '0';
SIGNAL transfer_done : STD_LOGIC := '0';
BEGIN
@@ -100,7 +99,6 @@ BEGIN
clk <= (NOT clk) OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*7;
-
------------------------------------------------------------------------------
-- STIMULI
------------------------------------------------------------------------------
@@ -110,10 +108,10 @@ BEGIN
ram_wr_en <= '0';
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
- FOR i IN 0 TO c_ram.nof_dat-1 LOOP
+ FOR i IN 0 TO c_ram_data_size-1 LOOP
ram_wr_adr <= TO_UVEC(i, c_ram.adr_w);
ram_wr_dat <= TO_UVEC(i, c_ram.dat_w);
- ram_wr_en <= '1';
+ ram_wr_en <= '1';
proc_common_wait_some_cycles(clk, 1);
END LOOP;
ram_wr_en <= '0';
@@ -124,41 +122,32 @@ BEGIN
p_transfer : PROCESS
BEGIN
- start_pulse <= '0';
+ start_pulse <= '0';
start_address <= 0;
+ start_address_dly <= 0;
proc_common_wait_until_high(clk, init_done);
- start_pulse <= '1';
- proc_common_wait_some_cycles(clk, 1);
- start_pulse <= '0';
- proc_common_wait_until_high(clk, block_done);
-
+ FOR i IN 0 TO c_nof_blocks-1 LOOP
+ start_address <= i * g_data_size;
+ start_pulse <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ start_address_dly <= i * g_data_size; -- dp_block_to_mm is 1 clock behind so set address also 1 clock later.
+ start_pulse <= '0';
+ proc_common_wait_until_high(clk, block_done);
+ END LOOP;
+ proc_common_wait_some_cycles(clk, 1); -- needed for dp_block_to_mm to proccess last word.
transfer_done <= '1';
WAIT;
END PROCESS;
-
p_verify_read : PROCESS
- VARIABLE v_word_index: NATURAL := 0;
- VARIABLE v_step_index: NATURAL := 0;
- VARIABLE v_ram_adr : NATURAL := 0;
BEGIN
- ram_rd_en <= '0';
+ ram_rd_en <= '0';
ram_rd_adr <= TO_UVEC(0 , c_ram.adr_w);
- exp_data <= 0;
proc_common_wait_until_high(clk, transfer_done);
- WHILE v_ram_adr < c_ram.nof_dat LOOP
- ram_rd_adr <= TO_UVEC(v_ram_adr , c_ram.adr_w);
- ram_rd_en <= '1';
+ ram_rd_en <= '1';
+ FOR i IN 0 TO c_ram_data_size-1 LOOP
+ ram_rd_adr <= TO_UVEC(i, c_ram.adr_w);
proc_common_wait_some_cycles(clk, 1);
- exp_data <= v_ram_adr;
-
- IF v_word_index < g_data_size-1 THEN
- v_word_index := v_word_index + 1;
- ELSE
- v_word_index := 0;
- v_step_index := v_step_index + g_step_size;
- END IF;
- v_ram_adr := start_address + v_step_index + v_word_index;
END LOOP;
ram_rd_en <= '0';
@@ -167,39 +156,41 @@ BEGIN
WAIT;
END PROCESS;
-
p_verify_check: PROCESS
+ VARIABLE v_cnt: NATURAL := 0;
BEGIN
proc_common_wait_until_high(clk, transfer_done);
WHILE tb_end = '0' LOOP
WAIT UNTIL rising_edge(clk);
IF ram_rd_val = '1' THEN
- ASSERT exp_data = TO_UINT(ram_rd_dat) REPORT "RAM values not equal" SEVERITY ERROR;
+ ASSERT v_cnt = TO_UINT(ram_rd_dat) REPORT "RAM values not equal" SEVERITY ERROR;
+ v_cnt := v_cnt + 1;
END IF;
END LOOP;
WAIT;
END PROCESS;
-
-
+
+ ------------------------------------------------------------------------------
+ -- DUT, dp_block_from_mm and dp_block_to_mm
+ ------------------------------------------------------------------------------
-- RAM with test data
u_ram_rd: ENTITY common_lib.common_ram_r_w
GENERIC MAP (
g_ram => c_ram
)
PORT MAP (
- rst => rst,
- clk => clk,
- wr_en => ram_wr_en,
- wr_adr => ram_wr_adr,
- wr_dat => ram_wr_dat,
- rd_en => rd_mosi.rd,
- rd_adr => rd_mosi.address(c_ram.adr_w-1 DOWNTO 0),
- rd_dat => rd_miso.rddata(c_ram.dat_w-1 DOWNTO 0),
- rd_val => rd_miso.rdval
+ rst => rst,
+ clk => clk,
+ wr_en => ram_wr_en,
+ wr_adr => ram_wr_adr,
+ wr_dat => ram_wr_dat,
+ rd_en => rd_mosi.rd,
+ rd_adr => rd_mosi.address(c_ram.adr_w-1 DOWNTO 0),
+ rd_dat => rd_miso.rddata(c_ram.dat_w-1 DOWNTO 0),
+ rd_val => rd_miso.rdval
);
-
- -- DUT : dp_block_from_mm
+ -- DUT, dp_block_from_mm
u_dp_block_from_mm: ENTITY work.dp_block_from_mm
GENERIC MAP (
g_data_size => g_data_size,
@@ -209,19 +200,16 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
-
start_pulse => start_pulse,
start_address => start_address,
mm_done => block_done,
-
mm_mosi => rd_mosi,
mm_miso => rd_miso,
-
out_sosi => blk_sosi,
out_siso => blk_siso
);
- -- convert mm back to block
+ -- DUT, dp_block_to_mm
u_dp_block_to_mm: ENTITY work.dp_block_to_mm
GENERIC MAP (
g_data_size => g_data_size,
@@ -231,30 +219,26 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
-
- start_address => start_address,
-
+ start_address => start_address_dly,
mm_mosi => wr_mosi,
- --mm_miso => wr_miso,
-
- in_sosi => blk_sosi
+ in_sosi => blk_sosi
);
- -- RAM with converted result
+ -- RAM with transferred data
u_ram_wr: ENTITY common_lib.common_ram_r_w
GENERIC MAP (
g_ram => c_ram
)
PORT MAP (
- rst => rst,
- clk => clk,
- wr_en => wr_mosi.wr,
- wr_adr => wr_mosi.address(c_ram.adr_w-1 DOWNTO 0),
- wr_dat => wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0),
- rd_en => ram_rd_en,
- rd_adr => ram_rd_adr,
- rd_dat => ram_rd_dat,
- rd_val => ram_rd_val
+ rst => rst,
+ clk => clk,
+ wr_en => wr_mosi.wr,
+ wr_adr => wr_mosi.address(c_ram.adr_w-1 DOWNTO 0),
+ wr_dat => wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0),
+ rd_en => ram_rd_en,
+ rd_adr => ram_rd_adr,
+ rd_dat => ram_rd_dat,
+ rd_val => ram_rd_val
);
END tb;
--
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