diff --git a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd index a7d5d3e301106a454cc41d4b02a880766f8c7518..538f815e7a4972931599bb4a84e2dbcae8169cef 100644 --- a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd +++ b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd @@ -56,9 +56,15 @@ END mms_st_histogram; ARCHITECTURE str OF mms_st_histogram IS + CONSTANT c_reg_adr_w : NATURAL := 1; + CONSTANT c_ram_adr_w : NATURAL := ceil_log2(g_nof_bins); + SIGNAL reg_mosi_arr : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0); SIGNAL reg_miso_arr : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0); + SIGNAL dp_ram_mosi : t_mem_mosi; + SIGNAL dp_ram_miso : t_mem_miso; + SIGNAL ram_mosi_arr : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0); SIGNAL ram_miso_arr : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0); @@ -111,11 +117,36 @@ BEGIN ------------------------------------------------------------------------------- -- reg_mosi/miso multiplexer from g_nof_instances to 1 ------------------------------------------------------------------------------- + u_common_mem_mux_reg : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => g_nof_instances, + g_mult_addr_w => c_reg_adr_w + ) + PORT MAP ( + mosi => reg_mosi, + miso => reg_miso, + mosi_arr => reg_mosi_arr, + miso_arr => reg_miso_arr + ); ------------------------------------------------------------------------------- -- ram_mosi/miso multiplexer from g_nof_instances to 1 ------------------------------------------------------------------------------- + u_common_mem_mux_ram : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => g_nof_instances, + g_mult_addr_w => c_ram_adr_w + ) + PORT MAP ( + mosi => dp_ram_mosi, + miso => dp_ram_miso, + mosi_arr => ram_mosi_arr, + miso_arr => ram_miso_arr + ); - + -- Cross clock domain from DP clock to MM clock NOTE - work in progress + ram_miso <= dp_ram_miso; + dp_ram_mosi <= ram_mosi; + END str;