From a632f092cd947dee5e7cfee4e2326fd5aed490f1 Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Thu, 2 Nov 2023 10:47:13 +0100
Subject: [PATCH] Added the library to hdl_lib_uses_synth for the
ip_agi027_xxxx. Added ip_agi027_xxxx_ram ip_agi027_xxxx_ram_lib to
hdl_lib_disclose_library_clause_names. Added tech_memory_ram_rw_rw.vhd to
synth_files.
---
libraries/technology/memory/hdllib.cfg | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 03824a363b..86c40cbc4d 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram ip_agi027_xxxx_ram
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -10,6 +10,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_ram ip_arria10_e1sg_ram_lib
ip_arria10_e2sg_ram ip_arria10_e2sg_ram_lib
ip_ultrascale_ram ip_ultrascale_ram_lib
+ ip_agi027_xxxx_ram ip_agi027_xxxx_ram_lib
synth_files =
tech_memory_component_pkg.vhd
@@ -17,6 +18,7 @@ synth_files =
tech_memory_ram_crw_crw.vhd
tech_memory_ram_crwk_crw.vhd
tech_memory_ram_r_w.vhd
+ tech_memory_ram_rw_rw.vhd
tech_memory_rom_r.vhd
test_bench_files =
--
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