diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index 20a040c3f60a0c937c3b99e0ae3d4b2a3f2d18a5..0c5cfb57f97114126f356222a32abd9d9f34f2ba 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -40,6 +40,7 @@ test_bench_files =
tb/vhdl/tb_mms_reorder_rewire.vhd
regression_test_vhdl =
+ tb/vhdl/tb_reorder_col_wide_row_select.vhd
# tb/vhdl/tb_tb_reorder_col.vhd -- fails in unb2c
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
index 3345a5b623f67f66f47a0d3c4af4fd45e1202e1c..0c473d217b9614df7d6588373c4445fc363e6387 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
@@ -1,24 +1,25 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2011
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
-- Purpose: Reorder packet
-- Description:
-- Select g_nof_ch_sel complex samples from an input block of g_nof_ch_in
@@ -32,23 +33,7 @@
-- Note that if g_nof_ch_in is less than the period size, then g_nof_ch_sel
-- can be larger than g_nof_ch_in to select channels multiple times.
-- . The g_nof_ch_in defines the number of complex input data words in a data
--- period. In LOFAR a subband sample was defined as a dual pol subband, so a
--- pair of complex samples, but here instead the subband is defined as a
--- single signal path sample, so 1 complex sample via sosi.im and sosi.re.
--- . In LOFAR the channel select buffer was dual page, to ensure that the page
--- switch happens aligned with the sync. However typically the select buffer
--- only needs to be set once and remains fixed during a measurement.
--- Therefore the channel select buffer can be a single page memory.
--- . In LOFAR the selected channels were also output time multiplexed. This
--- was possible because g_nof_ch_sel <= g_nof_ch_in/2. Here the output is not
--- time multiplexed. If time multiplexing is needed then a separate component
--- needs to be used for this. For this purpose the reorder_retrieve streaming
--- source supports the ready signal. Typically output_siso.ready='1', but
--- when g_nof_ch_sel < g_nof_ch_in/2, then a toggling output_siso.ready can
--- be used to multiplex this reorder_col_select output with another reorder_col_select output stream.
--- . The reorder_col_select streaming sink does not support the input_siso signal, because it
--- is assumed that the reorder_col_select source is always fast enough. The reorder_col_select sink could
--- support the input_siso signal, e.g. based on store_done and retrieve_done.
+-- period, so 1 complex sample via sosi.im and sosi.re.
LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
index ed940ac1137eb2f2d2ad76cf6a092a85b642a6a8..53accf74f748070b8bffbe24cf61f596432a92ac 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
@@ -1,31 +1,30 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2011
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
-- Purpose: Select and/or reorder data on multiple streams.
--
-- Description:
--- Reorder-row unit that handles a stream that consists of
+-- Reorder-col unit that handles a stream that consists of
-- multiple (g_nof_inputs) input streams.
--- It assumes that the g_nof_ch_in input channels are equally
--- distributed over the g_nof_inputs input streams.
--
--
-- Remarks:
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index d248dca6631cc8404433839360af7fc4070c2d37..478eb96db607a8eeaa5627264d6886ad1c83dee2 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -1,35 +1,35 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2011
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
-- Purpose: Subband Select Reordering.
--
-- Description: For every clock cycle within a frame a different output
-- configuration can be created, based on the available inputs.
--
--- The selection buffer stores a set of selection words. Each
--- selection word defines the mapping of the inputs to the outputs
+-- The in_select input defines the mapping of the inputs to the outputs
-- for a single clock cylce.
--
-- Remarks:
---
+-- in_select has to be defined 1 clock cycle after the in_sosi data.
LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -62,7 +62,7 @@ END reorder_row_select;
ARCHITECTURE str OF reorder_row_select IS
- CONSTANT c_tot_pipeline : NATURAL := g_pipeline_in + g_pipeline_in_m + g_pipeline_out;
+ CONSTANT c_tot_pipeline : NATURAL := g_pipeline_in + g_pipeline_in_m + g_pipeline_out + 1; --+1 for regs process
CONSTANT c_data_w : NATURAL := g_dsp_data_w*c_nof_complex;
TYPE t_dp_sosi_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
index ad3c4d0cf9ddcb8ee50e9c7f091076c8cee5b509..847aea42e6d1ad4d7d992abf2d0acf18c35b9bb9 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
@@ -1,24 +1,31 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2010
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Usage:
+-- > as 10
+-- > run -all
+-- . Observe in_sosi_arr and out_sosi_arr in the Wave window
+--
+-- Description:
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
@@ -29,14 +36,6 @@ USE common_lib.common_lfsr_sequences_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
-
--- Usage:
--- > as 10
--- > run -all
--- . Observe in_sosi_arr and out_sosi_arr in the Wave window
---
--- Description:
-
ENTITY tb_reorder_col_wide_row_select IS
END tb_reorder_col_wide_row_select;
@@ -50,10 +49,19 @@ ARCHITECTURE tb OF tb_reorder_col_wide_row_select IS
CONSTANT c_nof_sync : NATURAL := 5;
- CONSTANT c_nof_inputs : NATURAL := 4;
- CONSTANT c_nof_ch_in : NATURAL := 256;
- CONSTANT c_nof_ch_sel : NATURAL := 192;
+ CONSTANT c_nof_inputs : NATURAL := 6;
+ CONSTANT c_nof_outputs : NATURAL := 2;
+ CONSTANT c_nof_ch_in : NATURAL := 1024;
+ CONSTANT c_nof_ch_sel_row : NATURAL := c_nof_inputs;
+ CONSTANT c_nof_ch_sel_col : NATURAL := 2;
+ CONSTANT c_nof_ch_sel_offset : NATURAL := 2;
+ CONSTANT c_ch_sel_offsets : t_natural_arr(0 TO c_nof_ch_sel_offset-1) := (0, 16);
+ CONSTANT c_ch_sel_step : NATURAL := 3;
+ CONSTANT c_nof_ch_sel : NATURAL := c_nof_ch_sel_offset*c_nof_ch_sel_col*c_nof_ch_sel_row;
CONSTANT c_nof_block_per_sync : NATURAL := 4;
+ CONSTANT c_nof_inputs_w : NATURAL := ceil_log2(c_nof_inputs);
+ CONSTANT c_in_select_w : NATURAL := c_nof_outputs*c_nof_inputs_w;
+ CONSTANT c_in_select_dly : NATURAL := 2;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
@@ -65,6 +73,8 @@ ARCHITECTURE tb OF tb_reorder_col_wide_row_select IS
SIGNAL st_en : STD_LOGIC := '1';
SIGNAL st_siso_arr : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL st_sosi_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL exp_sosi_arr : t_dp_sosi_arr(c_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL exp_siso_arr : t_dp_siso_arr(c_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL bsn : NATURAL := 10;
@@ -72,7 +82,11 @@ ARCHITECTURE tb OF tb_reorder_col_wide_row_select IS
SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL col_wide_select_sosi_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
- SIGNAL out_sosi_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_outputs-1 DOWNTO 0);
+ SIGNAL dly_out_sosi_arr : t_dp_sosi_arr(c_nof_outputs-1 DOWNTO 0);
+
+ SIGNAL reorder_row_in_select : STD_LOGIC_VECTOR(c_in_select_w-1 DOWNTO 0);
+ SIGNAL in_select : STD_LOGIC_VECTOR(c_in_select_w-1 DOWNTO 0);
BEGIN
@@ -81,24 +95,45 @@ BEGIN
-- MM domain
p_mm_stimuli : PROCESS
+ VARIABLE k : NATURAL;
BEGIN
FOR rep IN 0 TO c_nof_sync*c_nof_block_per_sync-1 LOOP
+ k := c_nof_ch_sel_col * (rep/c_nof_block_per_sync) * c_ch_sel_step;
mm_mosi <= c_mem_mosi_rst;
- proc_common_wait_until_low(clk, mm_miso.waitrequest);
- FOR I IN 0 TO c_nof_ch_sel-1 LOOP
- proc_mem_mm_bus_rd(I, clk, mm_mosi); -- Write the default SS map: (0, 1, 2, ... c_nof_ch_sel-1) ==> (0, 1, 2, ... c_nof_ch_sel-1)
+ proc_common_wait_until_low(clk, mm_miso.waitrequest);
+ FOR I IN 0 TO c_nof_ch_sel_offset-1 LOOP
+ FOR row IN 0 TO c_nof_ch_sel_row-1 LOOP
+ FOR col IN 0 TO c_nof_ch_sel_col-1 LOOP
+ FOR i_out IN 0 TO c_nof_outputs-1 LOOP
+ reorder_row_in_select((i_out+1)* c_nof_inputs_w -1 DOWNTO i_out * c_nof_inputs_w) <= TO_UVEC(row, c_nof_inputs_w);
+ END LOOP;
+ proc_mem_mm_bus_rd(c_ch_sel_offsets(I)+col+k, clk, mm_mosi);
+ END LOOP;
+ END LOOP;
END LOOP;
END LOOP;
WAIT;
END PROCESS;
-
+
+ u_pipe_in_select : ENTITY common_lib.common_pipeline
+ GENERIC MAP(
+ g_pipeline => c_in_select_dly,
+ g_in_dat_w => c_in_select_w,
+ g_out_dat_w => c_in_select_w
+ )
+ PORT MAP(
+ rst => rst,
+ clk => clk,
+ in_dat => reorder_row_in_select,
+ out_dat => in_select
+ );
------------------------------------------------------------------------------
-- Data blocks
------------------------------------------------------------------------------
gen_stimuli : FOR K IN 0 TO c_nof_inputs-1 GENERATE
p_st_stimuli : PROCESS
- VARIABLE v_re : NATURAL := 0;
- VARIABLE v_im : NATURAL := 1;
+ VARIABLE v_re : NATURAL := 0+k*2**5;
+ VARIABLE v_im : NATURAL := 1+k*2**5;
BEGIN
tb_end <= '0';
st_sosi_arr(K) <= c_dp_sosi_rst;
@@ -117,19 +152,6 @@ BEGIN
END LOOP;
END LOOP;
st_sosi_arr(K) <= c_dp_sosi_rst;
- proc_common_wait_some_cycles(clk, 100);
- -- Run some sync intervals more
- WAIT UNTIL rising_edge(clk);
- FOR I IN 0 TO c_nof_sync-1 LOOP
- proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
- v_re := v_re + c_nof_ch_in;
- v_im := v_im + c_nof_ch_in;
- FOR J IN 0 TO c_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
- v_re := v_re + c_nof_ch_in;
- v_im := v_im + c_nof_ch_in;
- END LOOP;
- END LOOP;
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
WAIT;
@@ -138,7 +160,7 @@ BEGIN
-- Time stimuli
bsn <= bsn + 1 WHEN rising_edge(clk) AND (st_sosi_arr(0).eop='1'); -- OR st_sosi.sync='1');
-
+
-- Add BSN to the ST data
p_in_sosi : PROCESS(st_sosi_arr, bsn)
BEGIN
@@ -147,6 +169,75 @@ BEGIN
in_sosi_arr(I).bsn <= TO_DP_BSN(bsn);
END LOOP;
END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Verification
+ ------------------------------------------------------------------------------
+
+ u_pipeline_arr : ENTITY dp_lib.dp_pipeline_arr
+ GENERIC MAP (
+ g_nof_streams => c_nof_outputs
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+
+ snk_in_arr => out_sosi_arr,
+ src_out_arr => dly_out_sosi_arr
+ );
+
+ gen_verify : FOR O IN 0 TO c_nof_outputs-1 GENERATE
+ p_generate_exp_data : PROCESS
+ VARIABLE v_col : NATURAL := 0;
+ VARIABLE v_row : NATURAL := 0;
+ VARIABLE v_offset : NATURAL := 0;
+ VARIABLE v_sync_ix : NATURAL := 0;
+ VARIABLE v_k : NATURAL := 0;
+ BEGIN
+ FOR I IN 0 TO c_nof_sync*c_nof_block_per_sync-1 LOOP
+ exp_sosi_arr(O) <= c_dp_sosi_rst;
+ proc_common_wait_until_high(clk, out_sosi_arr(0).sop);
+ FOR J IN 0 TO c_nof_ch_sel-1 LOOP
+ v_sync_ix := I / c_nof_block_per_sync;
+ v_offset := J / (c_nof_ch_sel_col*c_nof_ch_sel_row);
+ v_col := J MOD c_nof_ch_sel_col;
+ v_row := (J/c_nof_ch_sel_col) MOD c_nof_ch_sel_row;
+ v_k := c_nof_ch_sel_col * v_sync_ix * c_ch_sel_step;
+
+ exp_sosi_arr(O) <= c_dp_sosi_rst;
+ exp_sosi_arr(O).valid <= '1';
+ IF J = 0 THEN
+ exp_sosi_arr(O).sop <= '1';
+ IF I MOD c_nof_block_per_sync = 0 THEN
+ exp_sosi_arr(O).sync <= '1';
+ END IF;
+ ELSIF j = c_nof_ch_sel-1 THEN
+ exp_sosi_arr(O).eop <= '1';
+ END IF;
+
+ exp_sosi_arr(O).re <= TO_DP_DSP_DATA( I * c_nof_ch_in + v_k + c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ exp_sosi_arr(O).im <= TO_DP_DSP_DATA(1+ I * c_nof_ch_in + v_k + c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ proc_common_wait_some_cycles(clk, 1);
+ END LOOP;
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+ p_verify_out_sosi : PROCESS(clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ ASSERT dly_out_sosi_arr(O).valid = exp_sosi_arr(O).valid REPORT "Wrong out_sosi.valid" SEVERITY ERROR;
+ ASSERT dly_out_sosi_arr(O).sop = exp_sosi_arr(O).sop REPORT "Wrong out_sosi.sop" SEVERITY ERROR;
+ ASSERT dly_out_sosi_arr(O).eop = exp_sosi_arr(O).eop REPORT "Wrong out_sosi.eop" SEVERITY ERROR;
+ ASSERT dly_out_sosi_arr(O).sync = exp_sosi_arr(O).sync REPORT "Wrong out_sosi.sync" SEVERITY ERROR;
+ IF exp_sosi_arr(O).valid = '1' THEN
+ ASSERT dly_out_sosi_arr(O).re = exp_sosi_arr(O).re REPORT "Wrong out_sosi.re" SEVERITY ERROR;
+ ASSERT dly_out_sosi_arr(O).im = exp_sosi_arr(O).im REPORT "Wrong out_sosi.im" SEVERITY ERROR;
+ END IF;
+ END IF;
+ END PROCESS;
+ END GENERATE;
+
u_dut_col : ENTITY work.reorder_col_wide_select
GENERIC MAP (
@@ -173,17 +264,20 @@ BEGIN
GENERIC MAP (
g_dsp_data_w => c_dsp_data_w,
g_nof_inputs => c_nof_inputs,
- g_nof_outputs => 1
+ g_nof_outputs => c_nof_outputs
)
PORT MAP (
dp_rst => rst,
dp_clk => clk,
- in_select => (OTHERS => '0'),
+ in_select => in_select,
-- Streaming
input_sosi_arr => col_wide_select_sosi_arr,
output_sosi_arr => out_sosi_arr
- );
+ );
+
+
+
END tb;