diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/hdllib.cfg b/applications/compaan/designs/compaan_unb1_10g_param_stream/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..aa9d3751a69d42702935ddb51ac24b3172ff14ca
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/hdllib.cfg
@@ -0,0 +1,36 @@
+hdl_lib_name = compaan_unb1_10g_param_stream
+hdl_library_clause_name = compaan_unb1_10g_param_stream_lib
+hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE param_stream
+hdl_lib_technology = ip_stratixiv
+
+synth_files =
+ src/vhdl/compaan_design.vhd
+ src/vhdl/mmm_compaan_unb1_10g_param_stream.vhd
+ src/vhdl/compaan_unb1_10g_param_stream.vhd
+
+ $RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/mmm_compaan_unb1_10g_bg_db.vhd
+ $RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/compaan_unb1_10g_bg_db.vhd
+
+test_bench_files =
+ tb/vhdl/tb_compaan_unb1_10g_param_stream.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files = quartus/qsys_compaan_unb1_10g_param_stream.qsys .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ quartus/compaan_unb1_10g_param_stream_pins.tcl
+
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_unb1_10g_param_stream/qsys_compaan_unb1_10g_param_stream/synthesis/qsys_compaan_unb1_10g_param_stream.qip
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/mmm.cfg b/applications/compaan/designs/compaan_unb1_10g_param_stream/mmm.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8417b7e4515fa04ad3ad5cb1b86db33d41ed7ed1
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/mmm.cfg
@@ -0,0 +1,29 @@
+mmm_name = compaan_unb1_10g_param_stream
+
+board_select = unb1
+
+custom_peripherals =
+ reg_bsn_monitor 4 4
+ reg_dp_offload_tx 1 1
+ reg_dp_offload_tx_hdr_dat 1 6
+ reg_dp_offload_tx_hdr_ovr 1 5
+ reg_dp_offload_rx_hdr_dat 1 7
+ reg_dp_offload_rx_filter_hdr_fields 1 7
+ reg_diag_data_buffer 1 5
+ ram_diag_data_buffer 1 14
+ reg_diag_bg 1 3
+ ram_diag_bg 1 9
+ reg_mdio_0 1 3
+ reg_mdio_1 1 3
+ reg_mdio_2 1 3
+ reg_tr_10gbe 1 15
+ reg_tr_xaui 1 11
+ reg_compaan 1 19
+
+input_clks = mm_clk
+
+synth_master = qsys
+
+vhdl_output_path = src/vhdl/
+
+
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/quartus/compaan_unb1_10g_param_stream_pins.tcl b/applications/compaan/designs/compaan_unb1_10g_param_stream/quartus/compaan_unb1_10g_param_stream_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..111bf0bafb3056d9c045c22a3ef0a0a7dbf09805
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/quartus/compaan_unb1_10g_param_stream_pins.tcl
@@ -0,0 +1,29 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_clk.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_0.tcl
+
+
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/quartus/qsys_compaan_unb1_10g_param_stream.qsys b/applications/compaan/designs/compaan_unb1_10g_param_stream/quartus/qsys_compaan_unb1_10g_param_stream.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..0cf56e79cc37b2d9b65f6f87d8b0e6bdc478f739
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/quartus/qsys_compaan_unb1_10g_param_stream.qsys
@@ -0,0 +1,2582 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "12296";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element clk_input
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "28672";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element ram_diag_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_rx_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "long";
+ }
+ }
+ element reg_mdio_2.mem
+ {
+ datum baseAddress
+ {
+ value = "12320";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_tx_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "1536";
+ type = "long";
+ }
+ }
+ element reg_mdio_1.mem
+ {
+ datum baseAddress
+ {
+ value = "2016";
+ type = "long";
+ }
+ }
+ element reg_compaan.mem
+ {
+ datum baseAddress
+ {
+ value = "2097152";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_rx_filter_hdr_fields.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "long";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "12464";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element reg_diag_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "long";
+ }
+ }
+ element reg_mdio_0.mem
+ {
+ datum baseAddress
+ {
+ value = "12352";
+ type = "long";
+ }
+ }
+ element ram_diag_data_buffer.mem
+ {
+ datum baseAddress
+ {
+ value = "65536";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_tx_hdr_ovr.mem
+ {
+ datum baseAddress
+ {
+ value = "1792";
+ type = "long";
+ }
+ }
+ element reg_tr_xaui.mem
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "long";
+ }
+ }
+ element reg_bsn_monitor.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "12384";
+ type = "long";
+ }
+ }
+ element reg_diag_data_buffer.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "long";
+ }
+ }
+ element reg_tr_10GbE.mem
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ datum baseAddress
+ {
+ value = "262144";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_tx.mem
+ {
+ datum baseAddress
+ {
+ value = "12472";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "24576";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "1920";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\unb_unb1_minimal\\build\\synth\\quartus}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element ram_diag_bg
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element ram_diag_data_buffer
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element avs_eth_0.ram_write
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element reg_diag_data_buffer.read
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor.read
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_compaan
+ {
+ datum _sortIndex
+ {
+ value = "27";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element reg_diag_bg
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_diag_data_buffer
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_rx_filter_hdr_fields
+ {
+ datum _sortIndex
+ {
+ value = "28";
+ type = "int";
+ }
+ }
+ element reg_dp_offload_rx_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_tx
+ {
+ datum _sortIndex
+ {
+ value = "25";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_tx_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_tx_hdr_ovr
+ {
+ datum _sortIndex
+ {
+ value = "26";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element reg_mdio_0
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mdio_1
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mdio_2
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_xaui
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "12304";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "12448";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "1984";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element reg_wdi.system_reset
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_diag_data_buffer.write
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element reg_wdi.writedata
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="1" />
+ <parameter name="timeStamp" value="1461842596935" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="pio_debug_wave_external_connection"
+ internal="pio_debug_wave.external_connection"
+ type="conduit"
+ dir="end">
+ <port name="out_port_from_the_pio_debug_wave" internal="out_port" />
+ </interface>
+ <interface
+ name="pio_wdi_external_connection"
+ internal="pio_wdi.external_connection"
+ type="conduit"
+ dir="end">
+ <port name="out_port_from_the_pio_wdi" internal="out_port" />
+ </interface>
+ <interface
+ name="ram_diag_data_buffer_readdata"
+ internal="ram_diag_data_buffer.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_read"
+ internal="ram_diag_data_buffer.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_writedata"
+ internal="ram_diag_data_buffer.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_write"
+ internal="ram_diag_data_buffer.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_address"
+ internal="ram_diag_data_buffer.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_clk"
+ internal="ram_diag_data_buffer.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_reset"
+ internal="ram_diag_data_buffer.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_readdata"
+ internal="reg_diag_data_buffer.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_read"
+ internal="reg_diag_data_buffer.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_writedata"
+ internal="reg_diag_data_buffer.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_write"
+ internal="reg_diag_data_buffer.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_address"
+ internal="reg_diag_data_buffer.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_clk"
+ internal="reg_diag_data_buffer.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_reset"
+ internal="reg_diag_data_buffer.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_reset"
+ internal="reg_mdio_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_clk"
+ internal="reg_mdio_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_address"
+ internal="reg_mdio_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_write"
+ internal="reg_mdio_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_read"
+ internal="reg_mdio_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_writedata"
+ internal="reg_mdio_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_readdata"
+ internal="reg_mdio_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_reset"
+ internal="reg_mdio_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_readdata"
+ internal="reg_mdio_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_clk"
+ internal="reg_mdio_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_address"
+ internal="reg_mdio_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_write"
+ internal="reg_mdio_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_writedata"
+ internal="reg_mdio_1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_read"
+ internal="reg_mdio_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_reset"
+ internal="reg_mdio_2.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_clk"
+ internal="reg_mdio_2.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_address"
+ internal="reg_mdio_2.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_write"
+ internal="reg_mdio_2.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_writedata"
+ internal="reg_mdio_2.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_read"
+ internal="reg_mdio_2.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_readdata"
+ internal="reg_mdio_2.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_reset"
+ internal="reg_dp_offload_rx_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_clk"
+ internal="reg_dp_offload_rx_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_address"
+ internal="reg_dp_offload_rx_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_write"
+ internal="reg_dp_offload_rx_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_writedata"
+ internal="reg_dp_offload_rx_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_read"
+ internal="reg_dp_offload_rx_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_readdata"
+ internal="reg_dp_offload_rx_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_mm_rst"
+ internal="avs_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface name="eth1g_mm_clk" internal="avs_eth_0.clk" type="conduit" dir="end" />
+ <interface
+ name="eth1g_tse_address"
+ internal="avs_eth_0.tse_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_write"
+ internal="avs_eth_0.tse_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_read"
+ internal="avs_eth_0.tse_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_address"
+ internal="avs_eth_0.reg_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_write"
+ internal="avs_eth_0.reg_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_read"
+ internal="avs_eth_0.reg_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_readdata"
+ internal="avs_eth_0.reg_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_address"
+ internal="avs_eth_0.ram_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_write"
+ internal="avs_eth_0.ram_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_read"
+ internal="avs_eth_0.ram_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
+ type="conduit"
+ dir="end" />
+ <interface name="eth1g_irq" internal="avs_eth_0.irq" type="conduit" dir="end" />
+ <interface
+ name="reg_unb_sens_reset"
+ internal="reg_unb_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_clk"
+ internal="reg_unb_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_address"
+ internal="reg_unb_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_write"
+ internal="reg_unb_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_writedata"
+ internal="reg_unb_sens.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_read"
+ internal="reg_unb_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_readdata"
+ internal="reg_unb_sens.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_reset"
+ internal="pio_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_clk"
+ internal="pio_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_address"
+ internal="pio_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_write"
+ internal="pio_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_writedata"
+ internal="pio_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_read"
+ internal="pio_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_readdata"
+ internal="pio_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_reset"
+ internal="pio_pps.reset"
+ type="conduit"
+ dir="end" />
+ <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
+ <interface
+ name="pio_pps_address"
+ internal="pio_pps.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_write"
+ internal="pio_pps.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_writedata"
+ internal="pio_pps.writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
+ <interface
+ name="pio_pps_readdata"
+ internal="pio_pps.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_reset"
+ internal="reg_wdi.reset"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_wdi_address"
+ internal="reg_wdi.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_write"
+ internal="reg_wdi.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_writedata"
+ internal="reg_wdi.writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
+ <interface
+ name="reg_wdi_readdata"
+ internal="reg_wdi.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_reset"
+ internal="rom_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_clk"
+ internal="rom_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_address"
+ internal="rom_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_write"
+ internal="rom_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_writedata"
+ internal="rom_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_read"
+ internal="rom_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_readdata"
+ internal="rom_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_reset"
+ internal="reg_tr_10GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_clk"
+ internal="reg_tr_10GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_address"
+ internal="reg_tr_10GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_write"
+ internal="reg_tr_10GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_writedata"
+ internal="reg_tr_10GbE.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_read"
+ internal="reg_tr_10GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_readdata"
+ internal="reg_tr_10GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_waitrequest"
+ internal="reg_tr_10GbE.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_reset"
+ internal="reg_tr_xaui.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_clk"
+ internal="reg_tr_xaui.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_address"
+ internal="reg_tr_xaui.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_write"
+ internal="reg_tr_xaui.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_read"
+ internal="reg_tr_xaui.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_writedata"
+ internal="reg_tr_xaui.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_readdata"
+ internal="reg_tr_xaui.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_waitrequest"
+ internal="reg_tr_xaui.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_reset"
+ internal="reg_bsn_monitor.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_clk"
+ internal="reg_bsn_monitor.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_address"
+ internal="reg_bsn_monitor.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_write"
+ internal="reg_bsn_monitor.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_writedata"
+ internal="reg_bsn_monitor.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_read"
+ internal="reg_bsn_monitor.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_readdata"
+ internal="reg_bsn_monitor.readdata"
+ type="conduit"
+ dir="end" />
+ <interface name="clk_in" internal="clk_input.clk_in" type="clock" dir="end" />
+ <interface
+ name="reset_in"
+ internal="clk_input.clk_in_reset"
+ type="reset"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_reset"
+ internal="reg_dp_offload_tx_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_clk"
+ internal="reg_dp_offload_tx_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_address"
+ internal="reg_dp_offload_tx_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_write"
+ internal="reg_dp_offload_tx_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_writedata"
+ internal="reg_dp_offload_tx_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_read"
+ internal="reg_dp_offload_tx_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_readdata"
+ internal="reg_dp_offload_tx_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_reset"
+ internal="reg_diag_bg.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_clk"
+ internal="reg_diag_bg.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_address"
+ internal="reg_diag_bg.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_write"
+ internal="reg_diag_bg.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_writedata"
+ internal="reg_diag_bg.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_read"
+ internal="reg_diag_bg.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_readdata"
+ internal="reg_diag_bg.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_reset"
+ internal="ram_diag_bg.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_clk"
+ internal="ram_diag_bg.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_address"
+ internal="ram_diag_bg.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_write"
+ internal="ram_diag_bg.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_writedata"
+ internal="ram_diag_bg.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_read"
+ internal="ram_diag_bg.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_readdata"
+ internal="ram_diag_bg.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_reset"
+ internal="reg_dp_offload_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_clk"
+ internal="reg_dp_offload_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_address"
+ internal="reg_dp_offload_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_write"
+ internal="reg_dp_offload_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_writedata"
+ internal="reg_dp_offload_tx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_read"
+ internal="reg_dp_offload_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_readdata"
+ internal="reg_dp_offload_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_reset"
+ internal="reg_dp_offload_tx_hdr_ovr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_clk"
+ internal="reg_dp_offload_tx_hdr_ovr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_address"
+ internal="reg_dp_offload_tx_hdr_ovr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_write"
+ internal="reg_dp_offload_tx_hdr_ovr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_writedata"
+ internal="reg_dp_offload_tx_hdr_ovr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_read"
+ internal="reg_dp_offload_tx_hdr_ovr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_readdata"
+ internal="reg_dp_offload_tx_hdr_ovr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_reset"
+ internal="reg_compaan.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_clk"
+ internal="reg_compaan.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_address"
+ internal="reg_compaan.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_write"
+ internal="reg_compaan.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_writedata"
+ internal="reg_compaan.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_read"
+ internal="reg_compaan.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_filter_hdr_fields_readdata"
+ internal="reg_dp_offload_rx_filter_hdr_fields.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_filter_hdr_fields_read"
+ internal="reg_dp_offload_rx_filter_hdr_fields.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_filter_hdr_fields_writedata"
+ internal="reg_dp_offload_rx_filter_hdr_fields.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_filter_hdr_fields_write"
+ internal="reg_dp_offload_rx_filter_hdr_fields.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_filter_hdr_fields_address"
+ internal="reg_dp_offload_rx_filter_hdr_fields.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_filter_hdr_fields_clk"
+ internal="reg_dp_offload_rx_filter_hdr_fields.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_filter_hdr_fields_reset"
+ internal="reg_dp_offload_rx_filter_hdr_fields.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_readdata"
+ internal="reg_compaan.readdata"
+ type="conduit"
+ dir="end" />
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">qsys_compaan_unb1_10g_app_onchip_memory2_0</parameter>
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="true" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="25000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="25000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="25000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="is_hardcopy_compatible" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuID_stored" value="0" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="setting_perfCounterWidth" value="32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="muldiv_multiplierType" value="DSPBlock" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_lineSize" value="32" />
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="dataAddrWidth" value="22" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x7000' end='0x7800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_filter_hdr_fields.mem' start='0x400' end='0x600' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x600' end='0x700' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x700' end='0x780' /><slave name='avs_eth_0.mms_reg' start='0x780' end='0x7C0' /><slave name='timer_0.s1' start='0x7C0' end='0x7E0' /><slave name='reg_mdio_1.mem' start='0x7E0' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_debug_wave.s1' start='0x3010' end='0x3020' /><slave name='reg_mdio_2.mem' start='0x3020' end='0x3040' /><slave name='reg_mdio_0.mem' start='0x3040' end='0x3060' /><slave name='reg_unb_sens.mem' start='0x3060' end='0x3080' /><slave name='reg_diag_bg.mem' start='0x3080' end='0x30A0' /><slave name='pio_wdi.s1' start='0x30A0' end='0x30B0' /><slave name='pio_pps.mem' start='0x30B0' end='0x30B8' /><slave name='reg_dp_offload_tx.mem' start='0x30B8' end='0x30C0' /><slave name='ram_diag_bg.mem' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='cpu_0.jtag_debug_module' start='0x7000' end='0x7800' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='reg_compaan.mem' start='0x200000' end='0x400000' /></address-map>]]></parameter>
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_data_buffer">
+ <parameter name="g_adr_w" value="14" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_data_buffer">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_0">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_1">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_2">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_rx_hdr_dat">
+ <parameter name="g_adr_w" value="7" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_10GbE">
+ <parameter name="g_adr_w" value="15" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_xaui">
+ <parameter name="g_adr_w" value="11" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_input">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_tx_hdr_dat">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diag_bg">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
+ <parameter name="g_adr_w" value="9" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_tx">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_tx_hdr_ovr">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_compaan">
+ <parameter name="g_adr_w" value="19" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_rx_filter_hdr_fields">
+ <parameter name="g_adr_w" value="7" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x7000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x7000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3008" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3010" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x30a0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x07c0" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="cpu_0.reset_n" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="ram_diag_data_buffer.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_data_buffer.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_data_buffer.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00010000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mdio_0.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mdio_1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x07e0" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mdio_1.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mdio_2.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mdio_2.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3020" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_rx_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mdio_0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3040" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0780" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3060" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x30b0" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_tr_10GbE.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00040000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_tr_xaui.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_xaui.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_bsn_monitor.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_diag_data_buffer.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_mdio_0.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_mdio_1.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_mdio_2.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_tr_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_tr_xaui.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_bsn_monitor.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="ram_diag_data_buffer.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="cpu_0.reset_n" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0600" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_diag_bg.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3080" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="ram_diag_bg.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="ram_diag_bg.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diag_bg.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_tx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diag_data_buffer.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_bsn_monitor.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_2.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_10GbE.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="rom_system_info.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_wdi.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_pps.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_rx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_1.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_0.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="ram_diag_data_buffer.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="timer_0.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="pio_wdi.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_debug_wave.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_system_info.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="avs_eth_0.mm" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_tx.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_tx_hdr_ovr.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_tx_hdr_ovr.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_hdr_ovr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0700" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x30b8" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="ram_diag_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx_hdr_ovr.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_compaan.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_compaan.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_compaan.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00200000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_rx_filter_hdr_fields.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_rx_filter_hdr_fields.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_rx_filter_hdr_fields.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_rx_filter_hdr_fields.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0400" />
+ </connection>
+</system>
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/compaan_design.vhd b/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/compaan_design.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..379c14fb9e4ae50a82a7b0fa8620611a12344a0e
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/compaan_design.vhd
@@ -0,0 +1,132 @@
+------------------------------------------------------------------
+-- TOP LEVEL
+------------------------------------------------------------------
+library IEEE, dp_lib, param_stream_lib;
+use IEEE.STD_LOGIC_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+entity compaan_design is
+ generic (
+ BLOCKS_PER_SYNC : natural := 10
+ );
+ port (
+
+ -- ST sink
+ snk_out : OUT t_dp_siso := c_dp_siso_rdy;
+ snk_in : IN t_dp_sosi;
+
+ -- ST source
+ src_in : IN t_dp_siso;
+ src_out : OUT t_dp_sosi;
+
+ TEST_STOP : out std_logic_vector(2 downto 0 );
+ TEST_ERROR : out std_logic_vector(2 downto 0 );
+ TEST_FIFO_FULL : out std_logic_vector(1 downto 0 );
+ TEST_BLOCK_RD : out std_logic_vector(2 downto 0 );
+ address : in std_logic_vector(18 downto 0 );
+ read_data : out std_logic_vector(31 downto 0 );
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0 );
+
+ MM_CLK : in std_logic;
+
+ KPN_CLK : in std_logic;
+ KPN_RST : in std_logic
+ );
+end compaan_design;
+
+architecture STRUCTURE of compaan_design is
+
+
+ signal data_in_Data : std_logic_vector(63 downto 0);
+ signal data_in_control : std_logic;
+ signal data_in_Read : std_logic;
+ signal data_in_Exists : std_logic;
+ signal data_in_SOP : std_logic;
+ signal data_in_EOP : std_logic;
+
+ signal data_out_Data_c : std_logic_vector(63 downto 0);
+ signal data_out_Control_c : std_logic;
+ signal data_out_Write_c : std_logic;
+
+ signal data_out_Data : std_logic_vector(63 downto 0);
+ signal data_out_Control : std_logic;
+ signal data_out_Write : std_logic;
+ signal data_out_Full : std_logic;
+ signal data_out_SOP : std_logic;
+ signal data_out_EOP : std_logic;
+
+ signal snk_in_nop : t_dp_sosi := c_dp_sosi_rst;
+
+begin
+
+ snk_out.ready <= data_in_Read; --'1';
+
+ -- wrapper -> ipcore
+ data_in_Data <= snk_in.data(63 downto 0);
+ data_in_Exists <= snk_in.valid;
+ data_in_SOP <= snk_in.sop;
+ data_in_EOP <= snk_in.eop;
+
+ -- ipcore --> wrapper
+ --src_out.valid <= data_out_Write;
+ --src_out.data <= RESIZE_DP_DATA(data_out_Data);
+ --src_out.sop <= data_out_SOP;
+ --src_out.eop <= data_out_EOP;
+
+
+
+ snk_in_nop.valid <= data_out_Write_c;
+ snk_in_nop.data <= RESIZE_DP_DATA(data_out_Data_c);
+ data_out_Full <= not src_in.ready;
+
+ -- Compaan ipcore
+ u_compaan_design : ENTITY param_stream_lib.param_stream
+ PORT MAP (
+
+ data_in_Data => data_in_Data,
+ data_in_Control => data_in_Control,
+ data_in_Read => data_in_Read,
+ data_in_Exists => data_in_Exists,
+
+ data_out_Data => data_out_Data_c,
+ data_out_Control => data_out_Control_c,
+ data_out_Write => data_out_Write_c,
+ data_out_Full => data_out_Full,
+
+ TEST_STOP => open,
+ TEST_ERROR => open,
+ TEST_FIFO_FULL => open,
+ TEST_BLOCK_RD => open,
+ address => address,
+ read_data => read_data,
+ read_en => read_en,
+ write_en => write_en,
+ write_data => write_data,
+
+ pci_clk => MM_CLK,
+-- MM_RST => MM_RST,
+ KPN_CLK => KPN_CLK,
+ KPN_RST => KPN_RST
+ );
+
+ u_pkg_signals_gen : ENTITY dp_lib.dp_block_gen
+ GENERIC MAP (
+ g_use_src_in => FALSE, -- when true use src_in.ready else use snk_in.valid for flow control
+ g_nof_data => BLOCKS_PER_SYNC -- nof data per block
+ )
+ port map (
+ rst => KPN_RST,
+ clk => KPN_CLK,
+ -- Streaming sink
+ snk_in => snk_in_nop,
+ -- Streaming source
+ src_in => src_in,
+ src_out => src_out,
+ -- MM control
+ en => '1'
+ );
+
+end architecture STRUCTURE;
+
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/compaan_unb1_10g_param_stream.vhd b/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/compaan_unb1_10g_param_stream.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..04dc36e580020ee64ad6108061e3f0d7c1382ced
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/compaan_unb1_10g_param_stream.vhd
@@ -0,0 +1,944 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . Test dp_offload_tx and dp_offload_rx components
+-- Description:
+-- . Block generators generate data blocks that flow from dp_offload_tx to dp_offload_rx
+-- instances via 10GbE (64b user interface)
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, diag_lib, tr_10GbE_lib, technology_lib;
+use IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+ENTITY compaan_unb1_10g_param_stream IS
+ GENERIC (
+ g_design_name : STRING := "compaan_unb1_10g_param_stream";
+ g_design_note : STRING := "revision info";
+ g_technology : NATURAL := c_tech_stratixiv;
+ g_sim : BOOLEAN := FALSE; -- set by ModelSim
+ g_sim_unb_nr : NATURAL := 0; -- set by ModelSim
+ g_sim_node_nr : NATURAL := 0; -- set by ModelSim
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
+ PPS : IN STD_LOGIC;
+ WDI : OUT STD_LOGIC;
+ INTA : INOUT STD_LOGIC;
+ INTB : INOUT STD_LOGIC;
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- SerDes Clock BN-BI / SI_FN
+
+ -- Serial I/O: 10GbE receivers
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- So we need to assign a '1' to it.
+ );
+END compaan_unb1_10g_param_stream;
+
+
+ARCHITECTURE str OF compaan_unb1_10g_param_stream IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 1); --
+
+ CONSTANT c_use_compaan : BOOLEAN := TRUE;
+
+ -- Revision controlled constants
+ CONSTANT c_use_1GbE : BOOLEAN := TRUE;
+ CONSTANT c_nof_streams : NATURAL := 1;
+ CONSTANT c_nof_10GbE_streams : NATURAL := c_nof_streams;
+ CONSTANT c_nof_bsn_mon_streams : NATURAL := 4;
+
+ CONSTANT c_data_w : NATURAL := 64; -- c_tech_tse_data_w;
+
+ -- Block generator
+ CONSTANT c_bg_addr_w : NATURAL := 9;
+ CONSTANT c_bg_block_size : NATURAL := 1117;
+ CONSTANT c_bg_gapsize : NATURAL := c_bg_block_size/2; -- Full (no gaps in data) BG output rate = 200MHz * 64b = 12.8Gbps. Including gap size: (365/(365+182))*12.8Gbps=8.54Gbps.
+ CONSTANT c_bg_calc_blocks_per_sync : NATURAL := 200000000/(c_bg_block_size+c_bg_gapsize);
+ CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, c_bg_calc_blocks_per_sync); -- 200000*(900+100) = 200000000 cycles = 1 second
+ CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+ -- dp_offload_tx
+ -- . IP total length : 2948 (UDP total lenth) + 20 (Ip header length) = 2968
+ -- . UDP total length: 8 (UDP header) + 20 (usr header) + 2920 (payload bytes) = 2948 -- 1488
+ CONSTANT c_ip_length : NATURAL := c_bg_block_size*8 + 50; --2970;
+ CONSTANT c_udp_length : NATURAL := c_bg_block_size*8 + 30; --2950;
+ CONSTANT c_nof_hdr_fields : NATURAL := 3+12+4+9+1; -- Total header bits = 512
+ CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(c_ip_length) ), --1508) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(c_udp_length) ), --1488) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ),
+ ( field_name_pad("usr_hdr_word_align" ), " ", 16, field_default(0) ) );
+
+
+
+
+ CONSTANT c_bypass_rx_filter : BOOLEAN := FALSE;
+
+ CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "111"&"111111111111"&"0011"&"101111111"&"0";
+
+ CONSTANT c_fifo_size : NATURAL := 2*c_bg_block_size;
+ CONSTANT c_nof_header_words : NATURAL := field_slv_len(c_hdr_field_arr) / c_data_w;
+ CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
+ CONSTANT c_nof_crc_words : NATURAL := 0;
+ CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
+
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
+
+ -- System
+ SIGNAL sa_rst : STD_LOGIC := '0';
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL dp_pps : STD_LOGIC;
+ SIGNAL epcs_clk : STD_LOGIC;
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi;
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC;
+ SIGNAL eth1g_ram_mosi : t_mem_mosi;
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ SIGNAL reg_diag_bg_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_miso : t_mem_miso;
+
+ SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+
+ --. 10G Receiver
+ SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+ SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+
+ SIGNAL reg_mdio_0_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_0_miso : t_mem_miso;
+ SIGNAL reg_mdio_1_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_1_miso : t_mem_miso;
+ SIGNAL reg_mdio_2_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_2_miso : t_mem_miso;
+
+ SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_miso : t_mem_miso;
+ SIGNAL ram_diag_data_buffer_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buffer_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buffer_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buffer_miso : t_mem_miso;
+
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ SIGNAL reg_compaan_mosi : t_mem_mosi;
+ SIGNAL reg_compaan_miso : t_mem_miso;
+
+ SIGNAL reg_dp_offload_rx_filter_hdr_fields_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_filter_hdr_fields_miso : t_mem_miso;
+
+ SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL block_gen_src_in_arr_temp : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL dp_offload_tx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_filter_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_filter_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL dp_fifo_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL dp_fifo_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL bsn_monitor_snk_in_arr : t_dp_sosi_arr(c_nof_bsn_mon_streams-1 DOWNTO 0);
+ SIGNAL bsn_monitor_snk_out_arr : t_dp_siso_arr(c_nof_bsn_mon_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ -- Interface: 10GbE
+ SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+
+ SIGNAL TEST_STOP : STD_LOGIC_VECTOR(2 downto 0 );
+ SIGNAL TEST_ERROR : STD_LOGIC_VECTOR(2 downto 0 );
+ SIGNAL TEST_FIFO_FULL : STD_LOGIC_VECTOR(1 downto 0 );
+ SIGNAL TEST_BLOCK_RD : STD_LOGIC_VECTOR(2 downto 0 );
+ SIGNAL address : STD_LOGIC_VECTOR(18 downto 0 );
+ SIGNAL read_data : STD_LOGIC_VECTOR(31 downto 0 );
+ SIGNAL read_en : STD_LOGIC;
+ SIGNAL write_en : STD_LOGIC;
+ SIGNAL write_data : STD_LOGIC_VECTOR(31 downto 0 );
+
+ SIGNAL fi_snk_out : t_dp_siso;
+ SIGNAL fi_snk_in : t_dp_sosi;
+ SIGNAL fi_src_in : t_dp_siso;
+ SIGNAL fi_src_out : t_dp_sosi;
+ SIGNAL fo_snk_out : t_dp_siso;
+ SIGNAL fo_snk_in : t_dp_sosi;
+ SIGNAL fo_src_in : t_dp_siso;
+ SIGNAL fo_src_out : t_dp_sosi;
+ SIGNAL compaan_snk_out : t_dp_siso;
+ SIGNAL compaan_snk_in : t_dp_sosi;
+ SIGNAL compaan_src_in : t_dp_siso;
+ SIGNAL compaan_src_out : t_dp_sosi;
+ SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- Interface : 10GbE
+ -----------------------------------------------------------------------------
+ -- Wire together different types
+ gen_wires: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ unb_xaui_tx_arr(i) <= xaui_tx_arr(i);
+ xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
+ END GENERATE;
+
+ u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
+ GENERIC MAP (
+ g_nof_xaui => c_nof_10GbE_streams
+ )
+ PORT MAP (
+ xaui_tx_arr => unb_xaui_tx_arr,
+ xaui_rx_arr => unb_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
+
+ u_areset_sa_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ PORT MAP(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_streams,
+ g_use_mdio => TRUE
+ )
+
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Data received by 10G
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ -- Data to be send by 10G
+ snk_out_arr => dp_offload_tx_src_in_arr,--dp_fifo_fill_src_in_arr,
+ snk_in_arr => dp_offload_tx_src_out_arr,--dp_fifo_fill_src_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
+
+
+
+ gen_dp_fifo_sc : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_fifo_size => 3*c_bg_block_size
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (BG)
+ snk_out => dp_fifo_snk_out_arr(i),
+ snk_in => dp_fifo_snk_in_arr(i),
+ -- ST source (tx_offload)
+ src_in => dp_offload_tx_snk_out_arr(i),
+ src_out => dp_offload_tx_snk_in_arr(i)
+ );
+
+
+
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- TX: dp_offload_tx
+ -----------------------------------------------------------------------------
+ u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_use_complex => FALSE,
+-- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => c_bg_block_size,
+-- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init,
+ g_use_post_split_fifo => TRUE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+-- reg_mosi => reg_dp_offload_tx_mosi,
+-- reg_miso => reg_dp_offload_tx_miso,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => dp_offload_tx_src_out_arr,
+ src_in_arr => dp_offload_tx_src_in_arr,
+
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
+
+ gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ -- dst = src
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac" )) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr" )) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+
+ -- dst port goes through 4000,4001,4002
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i).sync);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_hdr_word_align") DOWNTO field_lo(c_hdr_field_arr, "usr_hdr_word_align" )) <= TO_UVEC(0, 16);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_total_length" ) DOWNTO field_lo(c_hdr_field_arr, "ip_total_length" )) <= TO_UVEC(c_ip_length, 16);
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- DP loopback dp_offload_rx to dp_offload_tx
+ -----------------------------------------------------------------------------
+ gen_compaan : IF c_use_compaan = TRUE GENERATE
+
+
+ -- RX --> FIFO in
+ fi_snk_in <= dp_offload_rx_filter_src_out_arr(0);--dp_offload_rx_src_out_arr(0);
+ dp_offload_rx_filter_src_in_arr(0) <= fi_snk_out; --dp_offload_rx_src_in_arr(0);
+
+ -- FIFO out --> Tx
+ dp_fifo_snk_in_arr(0) <= fo_src_out;
+ fo_src_in <= dp_fifo_snk_out_arr(0);
+
+
+ -- Loop FIFO in
+ g_fifo_in_header : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => c_data_w, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_bsn_w => 1,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => FALSE,
+ g_use_empty => FALSE,
+ g_use_channel => FALSE,
+ g_use_error => FALSE,
+ g_use_sync => FALSE,
+ g_use_ctrl => TRUE, -- sop & eop
+ g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size*2, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin => 4, -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl => 0
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Monitor FIFO filling
+ wr_ful => open,
+ usedw => open,
+ rd_emp => open,
+ -- ST sink
+ snk_out => fi_snk_out,
+ snk_in => fi_snk_in,
+ -- ST source
+ src_in => compaan_snk_out,
+ src_out => compaan_snk_in
+ );
+
+
+ -- Loop FIFO out
+ g_fifo_out : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => c_data_w, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_bsn_w => 1,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => FALSE,
+ g_use_empty => FALSE,
+ g_use_channel => FALSE,
+ g_use_error => FALSE,
+ g_use_sync => FALSE,
+ g_use_ctrl => TRUE, -- sop & eop
+ g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin => 4, -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl => 1
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Monitor FIFO filling
+ wr_ful => open,
+ usedw => open,
+ rd_emp => open,
+ -- ST sink
+ snk_out => compaan_src_in,
+ snk_in => compaan_src_out,
+ -- ST source
+ src_in => fo_src_in,
+ src_out => fo_src_out
+ );
+
+
+ -- Compaan design
+
+
+ g_compaan_design : ENTITY work.compaan_design
+ GENERIC MAP (
+ BLOCKS_PER_SYNC => c_bg_block_size
+ )
+ PORT MAP (
+
+ -- ST sink
+ snk_out => compaan_snk_out,
+ snk_in => compaan_snk_in,
+
+ -- ST source
+ src_in => compaan_src_in,
+ src_out => compaan_src_out,
+
+ TEST_STOP => TEST_STOP,
+ TEST_ERROR => TEST_ERROR,
+ TEST_FIFO_FULL => TEST_FIFO_FULL,
+ TEST_BLOCK_RD => TEST_BLOCK_RD,
+ address => reg_compaan_mosi.address(18 DOWNTO 0),
+ read_data => reg_compaan_miso.rddata(c_word_w -1 DOWNTO 0),
+ read_en => reg_compaan_mosi.rd,
+ write_en => reg_compaan_mosi.wr,
+ write_data => reg_compaan_mosi.wrdata(c_word_w -1 DOWNTO 0),
+
+ MM_CLK => mm_clk,
+
+ KPN_CLK => dp_clk,
+ KPN_RST => dp_rst
+ );
+
+ gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
+ diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- RX: Data buffers and BSN monitors
+ -----------------------------------------------------------------------------
+ gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ diag_data_buf_snk_in_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ diag_data_buf_snk_in_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ diag_data_buf_snk_in_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ END GENERATE;
+ END GENERATE;
+
+ gen_clean_loopback : IF c_use_compaan = FALSE GENERATE
+ -- Rx --> Tx
+ -- Create loopback without compaan.
+ dp_fifo_snk_in_arr <= dp_offload_rx_filter_src_out_arr;
+ dp_offload_rx_filter_src_in_arr <= dp_fifo_snk_out_arr;
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- RX: dp_offload_rx
+ -----------------------------------------------------------------------------
+ u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => c_use_1GbE,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- RX: dp_offload_rx_filter
+ -----------------------------------------------------------------------------
+ u_header_check : ENTITY dp_lib.dp_offload_rx_filter_mm
+ GENERIC MAP(
+ g_bypass => c_bypass_rx_filter,
+ g_nof_streams => c_nof_streams, --: POSITIVE;
+ g_data_w => c_data_w, --: NATURAL;
+ g_hdr_field_arr => c_hdr_field_arr --: t_common_field_arr
+ )
+ PORT MAP(
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_dp_offload_rx_filter_hdr_fields_mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
+ reg_dp_offload_rx_filter_hdr_fields_miso => reg_dp_offload_rx_filter_hdr_fields_miso,
+
+ snk_in_arr => dp_offload_rx_src_out_arr,
+ snk_out_arr => dp_offload_rx_src_in_arr,
+
+ src_out_arr => dp_offload_rx_filter_src_out_arr,
+ src_in_arr => dp_offload_rx_filter_src_in_arr,
+
+ hdr_fields_to_check_arr => hdr_fields_out_arr,
+
+ hdr_fields_val => '1'
+ );
+
+
+
+
+
+
+ u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+ GENERIC MAP (
+ g_nof_streams => c_nof_bsn_mon_streams,
+ g_cross_clock_domain => TRUE,
+ g_sync_timeout => 210000000,--c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync+1),
+ g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync*c_bg_block_size+1),
+ g_log_first_bsn => TRUE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => bsn_monitor_snk_out_arr,
+ in_sosi_arr => bsn_monitor_snk_in_arr
+ );
+
+ bsn_monitor_snk_in_arr(0) <= dp_offload_tx_snk_in_arr(0);
+ bsn_monitor_snk_out_arr(0) <= dp_offload_tx_snk_out_arr(0);
+
+ bsn_monitor_snk_in_arr(1) <= dp_offload_tx_src_out_arr(0);
+ bsn_monitor_snk_out_arr(1) <= dp_offload_tx_src_in_arr(0);
+
+ bsn_monitor_snk_in_arr(2) <= dp_offload_rx_snk_in_arr(0);
+ bsn_monitor_snk_out_arr(2) <= dp_offload_rx_snk_out_arr(0);
+
+ bsn_monitor_snk_in_arr(3) <= diag_data_buf_snk_in_arr(0);
+ bsn_monitor_snk_out_arr(3) <= diag_data_buf_snk_out_arr(0);
+
+ diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
+
+ u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => FALSE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buffer_mosi,
+ ram_data_buf_miso => ram_diag_data_buffer_miso,
+ reg_data_buf_mosi => reg_diag_data_buffer_mosi,
+ reg_data_buf_miso => reg_diag_data_buffer_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl_unb1_board : ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_flash_model => FALSE,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_fw_version => c_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_udp_offload => FALSE,
+ g_udp_offload_nof_streams => c_nof_streams,
+ g_dp_clk_use_pll => TRUE,
+ g_xo_clk_use_pll => TRUE
+ )
+ PORT MAP (
+ -- Clock and reset signals
+
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- UniBoard FPGA pins
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_inst_mmm_compaan_unb1_10g_param_stream : ENTITY work.mmm_compaan_unb1_10g_param_stream
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+ reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
+ reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ reg_diag_data_buffer_mosi => reg_diag_data_buffer_mosi,
+ reg_diag_data_buffer_miso => reg_diag_data_buffer_miso,
+ ram_diag_data_buffer_mosi => ram_diag_data_buffer_mosi,
+ ram_diag_data_buffer_miso => ram_diag_data_buffer_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_mdio_0_mosi => reg_mdio_0_mosi,
+ reg_mdio_0_miso => reg_mdio_0_miso,
+ reg_mdio_1_mosi => reg_mdio_1_mosi,
+ reg_mdio_1_miso => reg_mdio_1_miso,
+ reg_mdio_2_mosi => reg_mdio_2_mosi,
+ reg_mdio_2_miso => reg_mdio_2_miso,
+ reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
+ reg_tr_10gbe_miso => reg_tr_10gbe_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+ reg_compaan_mosi => reg_compaan_mosi,
+ reg_compaan_miso => reg_compaan_miso,
+ reg_dp_offload_rx_filter_hdr_fields_mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
+ reg_dp_offload_rx_filter_hdr_fields_miso => reg_dp_offload_rx_filter_hdr_fields_miso
+
+ );
+
+ reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
+ reg_mdio_mosi_arr(1) <= reg_mdio_1_mosi;
+ reg_mdio_mosi_arr(2) <= reg_mdio_2_mosi;
+
+ reg_mdio_0_miso <= reg_mdio_miso_arr(0);
+ reg_mdio_1_miso <= reg_mdio_miso_arr(1);
+ reg_mdio_2_miso <= reg_mdio_miso_arr(2);
+
+END str;
+
+
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/mmm_compaan_unb1_10g_param_stream.vhd b/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/mmm_compaan_unb1_10g_param_stream.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f783890f450501c52a66ff0725905b2d25d5a365
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/src/vhdl/mmm_compaan_unb1_10g_param_stream.vhd
@@ -0,0 +1,693 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- u_inst_mmm_compaan_unb1_10g_param_stream : ENTITY work.mmm_compaan_unb1_10g_param_stream
+-- GENERIC MAP(
+-- g_sim => g_sim,
+-- g_sim_unb_nr => g_sim_unb_nr,
+-- g_sim_node_nr => g_sim_node_nr
+-- )
+-- PORT MAP(
+-- mm_clk => mm_clk,
+-- mm_rst => mm_rst,
+-- pout_wdi => pout_wdi,
+-- reg_wdi_mosi => reg_wdi_mosi,
+-- reg_wdi_miso => reg_wdi_miso,
+-- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+-- reg_unb_system_info_miso => reg_unb_system_info_miso,
+-- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+-- rom_unb_system_info_miso => rom_unb_system_info_miso,
+-- reg_unb_sens_mosi => reg_unb_sens_mosi,
+-- reg_unb_sens_miso => reg_unb_sens_miso,
+-- reg_ppsh_mosi => reg_ppsh_mosi,
+-- reg_ppsh_miso => reg_ppsh_miso,
+-- eth1g_mm_rst => eth1g_mm_rst,
+-- eth1g_reg_interrupt => eth1g_reg_interrupt,
+-- eth1g_ram_mosi => eth1g_ram_mosi,
+-- eth1g_ram_miso => eth1g_ram_miso,
+-- eth1g_reg_mosi => eth1g_reg_mosi,
+-- eth1g_reg_miso => eth1g_reg_miso,
+-- eth1g_tse_mosi => eth1g_tse_mosi,
+-- eth1g_tse_miso => eth1g_tse_miso,
+-- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+-- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+-- reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
+-- reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
+-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+-- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+-- reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
+-- reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
+-- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+-- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+-- reg_dp_offload_rx_filter_hdr_fields_mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
+-- reg_dp_offload_rx_filter_hdr_fields_miso => reg_dp_offload_rx_filter_hdr_fields_miso,
+-- reg_diag_data_buffer_mosi => reg_diag_data_buffer_mosi,
+-- reg_diag_data_buffer_miso => reg_diag_data_buffer_miso,
+-- ram_diag_data_buffer_mosi => ram_diag_data_buffer_mosi,
+-- ram_diag_data_buffer_miso => ram_diag_data_buffer_miso,
+-- reg_diag_bg_mosi => reg_diag_bg_mosi,
+-- reg_diag_bg_miso => reg_diag_bg_miso,
+-- ram_diag_bg_mosi => ram_diag_bg_mosi,
+-- ram_diag_bg_miso => ram_diag_bg_miso,
+-- reg_mdio_0_mosi => reg_mdio_0_mosi,
+-- reg_mdio_0_miso => reg_mdio_0_miso,
+-- reg_mdio_1_mosi => reg_mdio_1_mosi,
+-- reg_mdio_1_miso => reg_mdio_1_miso,
+-- reg_mdio_2_mosi => reg_mdio_2_mosi,
+-- reg_mdio_2_miso => reg_mdio_2_miso,
+-- reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
+-- reg_tr_10gbe_miso => reg_tr_10gbe_miso,
+-- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+-- reg_tr_xaui_miso => reg_tr_xaui_miso,
+-- reg_compaan_mosi => reg_compaan_mosi,
+-- reg_compaan_miso => reg_compaan_miso
+-- );
+--
+-- SIGNAL reg_wdi_mosi : t_mem_mosi;
+-- SIGNAL reg_wdi_miso : t_mem_miso;
+-- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+-- SIGNAL reg_unb_system_info_miso : t_mem_miso;
+-- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+-- SIGNAL rom_unb_system_info_miso : t_mem_miso;
+-- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+-- SIGNAL reg_unb_sens_miso : t_mem_miso;
+-- SIGNAL reg_ppsh_mosi : t_mem_mosi;
+-- SIGNAL reg_ppsh_miso : t_mem_miso;
+-- SIGNAL eth1g_ram_mosi : t_mem_mosi;
+-- SIGNAL eth1g_ram_miso : t_mem_miso;
+-- SIGNAL eth1g_reg_mosi : t_mem_mosi;
+-- SIGNAL eth1g_reg_miso : t_mem_miso;
+-- SIGNAL eth1g_tse_mosi : t_mem_mosi;
+-- SIGNAL eth1g_tse_miso : t_mem_miso;
+-- SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
+-- SIGNAL reg_bsn_monitor_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_rx_filter_hdr_fields_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_rx_filter_hdr_fields_miso : t_mem_miso;
+-- SIGNAL reg_diag_data_buffer_mosi : t_mem_mosi;
+-- SIGNAL reg_diag_data_buffer_miso : t_mem_miso;
+-- SIGNAL ram_diag_data_buffer_mosi : t_mem_mosi;
+-- SIGNAL ram_diag_data_buffer_miso : t_mem_miso;
+-- SIGNAL reg_diag_bg_mosi : t_mem_mosi;
+-- SIGNAL reg_diag_bg_miso : t_mem_miso;
+-- SIGNAL ram_diag_bg_mosi : t_mem_mosi;
+-- SIGNAL ram_diag_bg_miso : t_mem_miso;
+-- SIGNAL reg_mdio_0_mosi : t_mem_mosi;
+-- SIGNAL reg_mdio_0_miso : t_mem_miso;
+-- SIGNAL reg_mdio_1_mosi : t_mem_mosi;
+-- SIGNAL reg_mdio_1_miso : t_mem_miso;
+-- SIGNAL reg_mdio_2_mosi : t_mem_mosi;
+-- SIGNAL reg_mdio_2_miso : t_mem_miso;
+-- SIGNAL reg_tr_10gbe_mosi : t_mem_mosi;
+-- SIGNAL reg_tr_10gbe_miso : t_mem_miso;
+-- SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+-- SIGNAL reg_tr_xaui_miso : t_mem_miso;
+-- SIGNAL reg_compaan_mosi : t_mem_mosi;
+-- SIGNAL reg_compaan_miso : t_mem_miso;
+--
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+
+ENTITY mmm_compaan_unb1_10g_param_stream IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0
+ );
+ PORT (
+ mm_clk : IN STD_LOGIC := '1';
+ mm_rst : IN STD_LOGIC := '1';
+ pout_wdi : OUT STD_LOGIC := '1';
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_bsn_monitor_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_tx_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_rx_filter_hdr_fields_mosi : OUT t_mem_mosi;
+ reg_dp_offload_rx_filter_hdr_fields_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_diag_data_buffer_mosi : OUT t_mem_mosi;
+ reg_diag_data_buffer_miso : IN t_mem_miso := c_mem_miso_rst;
+ ram_diag_data_buffer_mosi : OUT t_mem_mosi;
+ ram_diag_data_buffer_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_diag_bg_mosi : OUT t_mem_mosi;
+ reg_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst;
+ ram_diag_bg_mosi : OUT t_mem_mosi;
+ ram_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mdio_0_mosi : OUT t_mem_mosi;
+ reg_mdio_0_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mdio_1_mosi : OUT t_mem_mosi;
+ reg_mdio_1_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mdio_2_mosi : OUT t_mem_mosi;
+ reg_mdio_2_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_tr_10gbe_mosi : OUT t_mem_mosi;
+ reg_tr_10gbe_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_tr_xaui_mosi : OUT t_mem_mosi;
+ reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_compaan_mosi : OUT t_mem_mosi;
+ reg_compaan_miso : IN t_mem_miso := c_mem_miso_rst
+ );
+END ENTITY mmm_compaan_unb1_10g_param_stream;
+
+ARCHITECTURE str OF mmm_compaan_unb1_10g_param_stream IS
+
+ CONSTANT c_sim_node_type : STRING(1 TO 2) := sel_a_b(g_sim_node_nr<4, "FN", "BN");
+ CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+ CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+ CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+
+ SIGNAL sim_eth_mm_bus_switch : STD_LOGIC ;
+ SIGNAL sim_eth_psc_access : STD_LOGIC ;
+ SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth1g_reg_miso : t_mem_miso;
+ SIGNAL mm_rst_n : STD_LOGIC ;
+ SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
+
+ COMPONENT mm_file IS
+ GENERIC (
+ g_file_prefix : STRING ;
+ g_mm_clk_period : TIME := 8 ns;
+ g_update_on_change : BOOLEAN := FALSE;
+ g_mm_rd_latency : NATURAL := 1
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst;
+ mm_master_in : IN t_mem_miso := c_mem_miso_rst
+ );
+ END COMPONENT mm_file;
+
+ COMPONENT qsys_compaan_unb1_10g_param_stream IS
+ PORT (
+ reg_diag_bg_reset_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_write_export : out std_logic;
+ reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic;
+ ram_diag_bg_read_export : out std_logic;
+ eth1g_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_reset_export : out std_logic;
+ reset_in_reset_n : in std_logic := '0';
+ pio_pps_address_export : out std_logic;
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ reg_dp_offload_rx_filter_hdr_fields_clk_export : out std_logic;
+ pio_pps_reset_export : out std_logic;
+ eth1g_tse_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_1_clk_export : out std_logic;
+ reg_tr_10gbe_write_export : out std_logic;
+ reg_dp_offload_rx_filter_hdr_fields_address_export : out std_logic_vector(6 downto 0);
+ eth1g_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ ram_diag_data_buffer_reset_export : out std_logic;
+ reg_mdio_0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ eth1g_ram_address_export : out std_logic_vector(9 downto 0);
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_rx_hdr_dat_clk_export : out std_logic;
+ reg_diag_data_buffer_read_export : out std_logic;
+ reg_dp_offload_rx_filter_hdr_fields_writedata_export : out std_logic_vector(31 downto 0);
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0);
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ eth1g_reg_writedata_export : out std_logic_vector(31 downto 0);
+ reg_unb_sens_reset_export : out std_logic;
+ reg_tr_xaui_write_export : out std_logic;
+ eth1g_tse_address_export : out std_logic_vector(9 downto 0);
+ reg_wdi_reset_export : out std_logic;
+ reg_tr_xaui_writedata_export : out std_logic_vector(31 downto 0);
+ clk_in_clk : in std_logic := '0';
+ reg_dp_offload_rx_filter_hdr_fields_read_export : out std_logic;
+ ram_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_read_export : out std_logic;
+ rom_system_info_clk_export : out std_logic;
+ reg_unb_sens_read_export : out std_logic;
+ reg_compaan_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_unb_sens_write_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_mdio_0_clk_export : out std_logic;
+ ram_diag_bg_reset_export : out std_logic;
+ eth1g_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ eth1g_ram_write_export : out std_logic;
+ reg_dp_offload_tx_write_export : out std_logic;
+ reg_dp_offload_tx_hdr_ovr_read_export : out std_logic;
+ ram_diag_data_buffer_clk_export : out std_logic;
+ reg_tr_xaui_address_export : out std_logic_vector(10 downto 0);
+ reg_unb_sens_clk_export : out std_logic;
+ reg_dp_offload_rx_filter_hdr_fields_write_export : out std_logic;
+ reg_compaan_writedata_export : out std_logic_vector(31 downto 0);
+ ram_diag_bg_write_export : out std_logic;
+ ram_diag_bg_address_export : out std_logic_vector(8 downto 0);
+ reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ reg_diag_data_buffer_reset_export : out std_logic;
+ reg_mdio_0_write_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_write_export : out std_logic;
+ eth1g_ram_read_export : out std_logic;
+ reg_wdi_read_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_read_export : out std_logic;
+ eth1g_reg_read_export : out std_logic;
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0);
+ reg_tr_10gbe_read_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_reset_export : out std_logic;
+ reg_bsn_monitor_reset_export : out std_logic;
+ eth1g_tse_write_export : out std_logic;
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0);
+ reg_bsn_monitor_write_export : out std_logic;
+ reg_mdio_2_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_tr_xaui_waitrequest_export : in std_logic := '0';
+ pio_pps_clk_export : out std_logic;
+ eth1g_reg_address_export : out std_logic_vector(3 downto 0);
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0);
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(4 downto 0);
+ reg_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_tr_xaui_reset_export : out std_logic;
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ reg_compaan_clk_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_reset_export : out std_logic;
+ reg_dp_offload_rx_filter_hdr_fields_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(5 downto 0);
+ reg_diag_data_buffer_address_export : out std_logic_vector(4 downto 0);
+ reg_mdio_2_read_export : out std_logic;
+ reg_mdio_1_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_bsn_monitor_read_export : out std_logic;
+ reg_mdio_2_reset_export : out std_logic;
+ reg_tr_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ reg_diag_bg_clk_export : out std_logic;
+ reg_wdi_address_export : out std_logic;
+ pio_system_info_write_export : out std_logic;
+ reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ pio_pps_write_export : out std_logic;
+ rom_system_info_write_export : out std_logic;
+ rom_system_info_read_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_clk_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(6 downto 0);
+ reg_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_2_clk_export : out std_logic;
+ ram_diag_data_buffer_read_export : out std_logic;
+ reg_diag_bg_read_export : out std_logic;
+ reg_mdio_1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_mdio_2_address_export : out std_logic_vector(2 downto 0);
+ eth1g_tse_read_export : out std_logic;
+ ram_diag_bg_clk_export : out std_logic;
+ reg_tr_xaui_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_1_read_export : out std_logic;
+ eth1g_ram_writedata_export : out std_logic_vector(31 downto 0);
+ reg_compaan_address_export : out std_logic_vector(18 downto 0);
+ reg_mdio_2_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_address_export : out std_logic;
+ out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0);
+ reg_mdio_1_address_export : out std_logic_vector(2 downto 0);
+ reg_tr_xaui_read_export : out std_logic;
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ pio_system_info_reset_export : out std_logic;
+ reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ pio_system_info_read_export : out std_logic;
+ reg_bsn_monitor_address_export : out std_logic_vector(5 downto 0);
+ reg_mdio_1_reset_export : out std_logic;
+ reg_wdi_clk_export : out std_logic;
+ reg_diag_bg_write_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ eth1g_mm_rst_export : out std_logic;
+ reg_dp_offload_rx_filter_hdr_fields_reset_export : out std_logic;
+ reg_tr_10gbe_reset_export : out std_logic;
+ reg_compaan_read_export : out std_logic;
+ reg_tr_10gbe_clk_export : out std_logic;
+ reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic;
+ out_port_from_the_pio_wdi : out std_logic;
+ reg_bsn_monitor_clk_export : out std_logic;
+ eth1g_reg_write_export : out std_logic;
+ reg_mdio_1_write_export : out std_logic;
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ ram_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_compaan_reset_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_read_export : out std_logic;
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_wdi_write_export : out std_logic;
+ reg_tr_xaui_clk_export : out std_logic;
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_compaan_write_export : out std_logic;
+ pio_pps_read_export : out std_logic;
+ reg_mdio_2_write_export : out std_logic;
+ reg_dp_offload_tx_clk_export : out std_logic;
+ pio_system_info_clk_export : out std_logic;
+ reg_tr_10gbe_address_export : out std_logic_vector(14 downto 0);
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ eth1g_tse_waitrequest_export : in std_logic := '0';
+ reg_mdio_0_writedata_export : out std_logic_vector(31 downto 0);
+ reg_tr_10gbe_waitrequest_export : in std_logic := '0';
+ reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_diag_data_buffer_write_export : out std_logic;
+ eth1g_mm_clk_export : out std_logic;
+ rom_system_info_reset_export : out std_logic;
+ ram_diag_data_buffer_write_export : out std_logic;
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0);
+ reg_mdio_0_reset_export : out std_logic;
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ eth1g_irq_export : in std_logic := '0';
+ reg_mdio_0_address_export : out std_logic_vector(2 downto 0);
+ reg_diag_data_buffer_clk_export : out std_logic;
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_hdr_ovr_write_export : out std_logic;
+ reg_mdio_0_read_export : out std_logic;
+ ram_diag_data_buffer_address_export : out std_logic_vector(13 downto 0)
+ );
+ END COMPONENT qsys_compaan_unb1_10g_param_stream;
+
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ ----------------------------------------------------------------------------
+ gen_mm_file_io : IF g_sim = TRUE GENERATE
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_eth1g_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
+ PORT MAP(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ u_mm_file_eth1g_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
+ PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
+ u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
+ u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_rx_filter_hdr_fields : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_FILTER_HDR_FIELDS")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_filter_hdr_fields_mosi, reg_dp_offload_rx_filter_hdr_fields_miso );
+ u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buffer_mosi, reg_diag_data_buffer_miso );
+ u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buffer_mosi, ram_diag_data_buffer_miso );
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
+ u_mm_file_reg_mdio_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_0")
+ PORT MAP(mm_rst, mm_clk, reg_mdio_0_mosi, reg_mdio_0_miso );
+ u_mm_file_reg_mdio_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_1")
+ PORT MAP(mm_rst, mm_clk, reg_mdio_1_mosi, reg_mdio_1_miso );
+ u_mm_file_reg_mdio_2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_2")
+ PORT MAP(mm_rst, mm_clk, reg_mdio_2_mosi, reg_mdio_2_miso );
+ u_mm_file_reg_tr_10gbe : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10gbe_mosi, reg_tr_10gbe_miso );
+ u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")
+ PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso );
+ u_mm_file_reg_compaan : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_COMPAAN")
+ PORT MAP(mm_rst, mm_clk, reg_compaan_mosi, reg_compaan_miso );
+ ----------------------------------------------------------------------------
+ -- 1GbE setup sequence normally performed by unb_os@NIOS
+ ----------------------------------------------------------------------------
+ eth1g_mm_rst <= '1', '0' AFTER 40 ns;
+ p_eth_setup : PROCESS
+ BEGIN
+ sim_eth_mm_bus_switch <= '1';
+ eth1g_tse_mosi.wr <= '0';
+ eth1g_tse_mosi.rd <= '0';
+ WAIT FOR 400 ns;
+ WAIT UNTIL rising_edge(mm_clk);
+ proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+ -- Enable RX
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ sim_eth_mm_bus_switch <= '0';
+ WAIT;
+ END PROCESS;
+
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+ BEGIN
+ IF sim_eth_mm_bus_switch = '1' THEN
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ ELSE
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ END IF;
+ END PROCESS;
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ END GENERATE;
+ ----------------------------------------------------------------------------
+ -- SOPC or QSYS for synthesis
+ ----------------------------------------------------------------------------
+ gen_qsys_compaan_unb1_10g_param_stream : IF g_sim = FALSE GENERATE
+
+ mm_rst_n <= NOT(mm_rst);
+
+ u_qsys_compaan_unb1_10g_param_stream : qsys_compaan_unb1_10g_param_stream
+ PORT MAP(
+ clk_in_clk => mm_clk,
+ eth1g_irq_export => eth1g_reg_interrupt,
+ eth1g_mm_clk_export => OPEN,
+ eth1g_mm_rst_export => eth1g_mm_rst,
+ eth1g_ram_address_export => eth1g_ram_mosi.address(9 DOWNTO 0),
+ eth1g_ram_read_export => eth1g_ram_mosi.rd,
+ eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_ram_write_export => eth1g_ram_mosi.wr,
+ eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ eth1g_reg_address_export => eth1g_reg_mosi.address(3 DOWNTO 0),
+ eth1g_reg_read_export => eth1g_reg_mosi.rd,
+ eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_reg_write_export => eth1g_reg_mosi.wr,
+ eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ eth1g_tse_address_export => eth1g_tse_mosi.address(9 DOWNTO 0),
+ eth1g_tse_read_export => eth1g_tse_mosi.rd,
+ eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ eth1g_tse_write_export => eth1g_tse_mosi.wr,
+ eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ out_port_from_the_pio_debug_wave => OPEN,
+ out_port_from_the_pio_wdi => pout_wdi,
+ pio_pps_address_export => reg_ppsh_mosi.address(0),
+ pio_pps_clk_export => OPEN,
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_pps_reset_export => OPEN,
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(4 DOWNTO 0),
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_address_export => ram_diag_bg_mosi.address(8 DOWNTO 0),
+ ram_diag_bg_clk_export => OPEN,
+ ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
+ ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_reset_export => OPEN,
+ ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
+ ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_address_export => ram_diag_data_buffer_mosi.address(13 DOWNTO 0),
+ ram_diag_data_buffer_clk_export => OPEN,
+ ram_diag_data_buffer_read_export => ram_diag_data_buffer_mosi.rd,
+ ram_diag_data_buffer_readdata_export => ram_diag_data_buffer_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_reset_export => OPEN,
+ ram_diag_data_buffer_write_export => ram_diag_data_buffer_mosi.wr,
+ ram_diag_data_buffer_writedata_export => ram_diag_data_buffer_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(5 DOWNTO 0),
+ reg_bsn_monitor_clk_export => OPEN,
+ reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
+ reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_reset_export => OPEN,
+ reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
+ reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_compaan_address_export => reg_compaan_mosi.address(18 DOWNTO 0),
+ reg_compaan_clk_export => OPEN,
+ reg_compaan_read_export => reg_compaan_mosi.rd,
+ reg_compaan_readdata_export => reg_compaan_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_compaan_reset_export => OPEN,
+ reg_compaan_write_export => reg_compaan_mosi.wr,
+ reg_compaan_writedata_export => reg_compaan_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_address_export => reg_diag_bg_mosi.address(2 DOWNTO 0),
+ reg_diag_bg_clk_export => OPEN,
+ reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
+ reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_reset_export => OPEN,
+ reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
+ reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_address_export => reg_diag_data_buffer_mosi.address(4 DOWNTO 0),
+ reg_diag_data_buffer_clk_export => OPEN,
+ reg_diag_data_buffer_read_export => reg_diag_data_buffer_mosi.rd,
+ reg_diag_data_buffer_readdata_export => reg_diag_data_buffer_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_reset_export => OPEN,
+ reg_diag_data_buffer_write_export => reg_diag_data_buffer_mosi.wr,
+ reg_diag_data_buffer_writedata_export => reg_diag_data_buffer_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_filter_hdr_fields_address_export => reg_dp_offload_rx_filter_hdr_fields_mosi.address(6 DOWNTO 0),
+ reg_dp_offload_rx_filter_hdr_fields_clk_export => OPEN,
+ reg_dp_offload_rx_filter_hdr_fields_read_export => reg_dp_offload_rx_filter_hdr_fields_mosi.rd,
+ reg_dp_offload_rx_filter_hdr_fields_readdata_export => reg_dp_offload_rx_filter_hdr_fields_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_filter_hdr_fields_reset_export => OPEN,
+ reg_dp_offload_rx_filter_hdr_fields_write_export => reg_dp_offload_rx_filter_hdr_fields_mosi.wr,
+ reg_dp_offload_rx_filter_hdr_fields_writedata_export => reg_dp_offload_rx_filter_hdr_fields_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(6 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_address_export => reg_dp_offload_tx_mosi.address(0),
+ reg_dp_offload_tx_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(5 DOWNTO 0),
+ reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_address_export => reg_dp_offload_tx_hdr_ovr_mosi.address(4 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_ovr_read_export => reg_dp_offload_tx_hdr_ovr_mosi.rd,
+ reg_dp_offload_tx_hdr_ovr_readdata_export => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_reset_export => OPEN,
+ reg_dp_offload_tx_hdr_ovr_write_export => reg_dp_offload_tx_hdr_ovr_mosi.wr,
+ reg_dp_offload_tx_hdr_ovr_writedata_export => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_read_export => reg_dp_offload_tx_mosi.rd,
+ reg_dp_offload_tx_readdata_export => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_reset_export => OPEN,
+ reg_dp_offload_tx_write_export => reg_dp_offload_tx_mosi.wr,
+ reg_dp_offload_tx_writedata_export => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mdio_0_address_export => reg_mdio_0_mosi.address(2 DOWNTO 0),
+ reg_mdio_0_clk_export => OPEN,
+ reg_mdio_0_read_export => reg_mdio_0_mosi.rd,
+ reg_mdio_0_readdata_export => reg_mdio_0_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mdio_0_reset_export => OPEN,
+ reg_mdio_0_write_export => reg_mdio_0_mosi.wr,
+ reg_mdio_0_writedata_export => reg_mdio_0_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mdio_1_address_export => reg_mdio_1_mosi.address(2 DOWNTO 0),
+ reg_mdio_1_clk_export => OPEN,
+ reg_mdio_1_read_export => reg_mdio_1_mosi.rd,
+ reg_mdio_1_readdata_export => reg_mdio_1_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mdio_1_reset_export => OPEN,
+ reg_mdio_1_write_export => reg_mdio_1_mosi.wr,
+ reg_mdio_1_writedata_export => reg_mdio_1_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mdio_2_address_export => reg_mdio_2_mosi.address(2 DOWNTO 0),
+ reg_mdio_2_clk_export => OPEN,
+ reg_mdio_2_read_export => reg_mdio_2_mosi.rd,
+ reg_mdio_2_readdata_export => reg_mdio_2_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mdio_2_reset_export => OPEN,
+ reg_mdio_2_write_export => reg_mdio_2_mosi.wr,
+ reg_mdio_2_writedata_export => reg_mdio_2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_address_export => reg_tr_10gbe_mosi.address(14 DOWNTO 0),
+ reg_tr_10gbe_clk_export => OPEN,
+ reg_tr_10gbe_read_export => reg_tr_10gbe_mosi.rd,
+ reg_tr_10gbe_readdata_export => reg_tr_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_reset_export => OPEN,
+ reg_tr_10gbe_waitrequest_export => reg_tr_10gbe_miso.waitrequest,
+ reg_tr_10gbe_write_export => reg_tr_10gbe_mosi.wr,
+ reg_tr_10gbe_writedata_export => reg_tr_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_xaui_address_export => reg_tr_xaui_mosi.address(10 DOWNTO 0),
+ reg_tr_xaui_clk_export => OPEN,
+ reg_tr_xaui_read_export => reg_tr_xaui_mosi.rd,
+ reg_tr_xaui_readdata_export => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_xaui_reset_export => OPEN,
+ reg_tr_xaui_waitrequest_export => reg_tr_xaui_miso.waitrequest,
+ reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr,
+ reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 DOWNTO 0),
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_address_export => reg_wdi_mosi.address(0),
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reset_in_reset_n => mm_rst_n,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+END str;
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/tb/python/tc_compaan_unb1_10g_param_stream.py b/applications/compaan/designs/compaan_unb1_10g_param_stream/tb/python/tc_compaan_unb1_10g_param_stream.py
new file mode 100644
index 0000000000000000000000000000000000000000..179f22247e2802b439e1b7f85fe72931ba96da3a
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/tb/python/tc_compaan_unb1_10g_param_stream.py
@@ -0,0 +1,247 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (dC) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# Purpose:
+# . Scripts make 10G settings for FN0 and FN1:
+#
+# Where FN0 and FN1 contain both the compaan_unb1_10g_bg_db design.
+#
+# Description:
+# . BG outputs blocks of 365 64b words = 2920 bytes;
+# . BG uses inter-block gap size of c_gap_size = 3000 words to limit BG output rate to
+
+# Usage:
+# . Load the following images on the following nodes:
+# . FN0 - compaan_unb1_10g_loopback or compaan_unb1_10g_compaan
+# . FN1 - compaan_unb1_10g_blockgen
+# . python tc_compaan_unb1_10g_bg_lb.py --unb # --fn 0,1
+# . Use tcpdump to view the received packets.
+
+
+# FN2 = lcu(bg and db), FN3 = dut(app)
+
+from common import *
+import test_case
+import node_io
+import pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_bg_db
+import pi_dp_offload_rx_hdr_fields_compaan_unb1_10g_bg_db
+import pi_diag_block_gen
+import pi_diag_data_buffer
+import pi_eth
+import pi_compaan
+from eth import *
+
+# Some definitions
+c_10g_data_w = 64 # 64 bit internal data
+c_blocksize = 16 # 365 samples * 8 bytes(= 64bit) = 2920 bytes
+c_bg_nof_streams = 1
+c_bg_ram_size = 512
+c_gap_size = 100
+c_nof_blocks_per_sync = 10
+c_write_block_gen = True
+
+# Instantiate testcase and IO
+tc = test_case.Testcase('TB - ', '')
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+ca = pi_compaan.PiCompaan(tc, io, nof_inst=1)
+
+# rx fields reg
+rx_filter_hdr = pi_dp_offload_rx_hdr_fields_compaan_unb1_10g_bg_db.PiDpOffloadRxFilterHdrFieldsCompaanUnb110gBgDb(tc, io, nof_inst=1)
+
+# Instantiate 10G offload objects: FN0=[0], FN1=[1]
+dpotx_hdr_dat = pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_bg_db.PiDpOffloadTxHdrDatCompaanUnb110GBgDb(tc, io, nof_inst=1)
+
+# Create block generator/data buffer instance (only FN2)
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, c_bg_nof_streams, c_bg_ram_size, tc.nodeFn2Nrs )
+db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = '', nofStreams=c_bg_nof_streams, ramSizePerStream=2048, nodeNr = tc.nodeFn2Nrs )
+
+# MAC Addresses
+eth_src_mac = 0x2286080008 # 10G MAC base address for UniBoard
+eth_dst_mac = 0x074306C700 #+ 1 # 10G MAC address jop63
+
+# Fixed header constants
+IP_HEADER_LENGTH = 20
+UDP_HEADER_LENGTH = 8
+USR_HEADER_LENGTH = 20
+USR_HDR_WORD_ALIGN = 2
+NOF_PAYLOAD_BYTES = c_blocksize * 8 #2920
+
+###############################################################################
+# The IP header field values. All fixed except ip_src_addr
+# (and concequently the ip_header_checksum).
+###############################################################################
+ip_version = 4
+ip_header_length = 5 # 5 32b words
+ip_services = 0
+ip_total_length = IP_HEADER_LENGTH+UDP_HEADER_LENGTH+USR_HEADER_LENGTH+USR_HDR_WORD_ALIGN+NOF_PAYLOAD_BYTES - 7 # 6196B
+ip_identification = 0
+ip_flags = 2
+ip_fragment_offset = 0
+ip_time_to_live = 127
+ip_protocol = 17
+ip_header_checksum = 0 # to be calculated
+#ip_src_addr_fn0 = 0xc0a80164 # 0xc0a80164 = 192.168.1.100
+#ip_src_addr_fn1 = 0xc0a80165 # 0xc0a80165 = 192.168.1.101
+ip_src_addr_fn2 = 0xc0a80166 # 0xc0a80164 = 192.168.1.102
+ip_src_addr_fn3 = 0xc0a80167 # 0xc0a80165 = 192.168.1.103
+ip_dst_addr = 0xc0a80102 # 0xc0a80102 = 192.168.1.2 = IP-address 10G in jop63
+
+###############################################################################
+# Calculate and print the IP header checksum for FN0
+###############################################################################
+hdr_bits_common = CommonBits(ip_version ,4) & \
+ CommonBits(ip_header_length ,4) & \
+ CommonBits(ip_services ,8) & \
+ CommonBits(ip_total_length ,16) & \
+ CommonBits(ip_identification ,16) & \
+ CommonBits(ip_flags ,3) & \
+ CommonBits(ip_fragment_offset ,13) & \
+ CommonBits(ip_time_to_live ,8) & \
+ CommonBits(ip_protocol ,8) & \
+ CommonBits(ip_header_checksum ,16)
+
+#hdr_bits_fn0 = hdr_bits_common & \
+# CommonBits(ip_src_addr_fn0 ,32) & \
+# CommonBits(ip_dst_addr ,32)
+
+#hdr_bits_fn1 = hdr_bits_common & \
+# CommonBits(ip_src_addr_fn1 ,32) & \
+# CommonBits(ip_dst_addr ,32)
+
+hdr_bits_fn2 = hdr_bits_common & \
+ CommonBits(ip_src_addr_fn2 ,32) & \
+ CommonBits(ip_dst_addr ,32)
+
+hdr_bits_fn3 = hdr_bits_common & \
+ CommonBits(ip_src_addr_fn3 ,32) & \
+ CommonBits(ip_dst_addr ,32)
+
+#hdr_bytes_fn0 = CommonBytes(hdr_bits_fn0.data, 20)
+#hdr_bytes_fn1 = CommonBytes(hdr_bits_fn1.data, 20)
+hdr_bytes_fn2 = CommonBytes(hdr_bits_fn2.data, 20)
+hdr_bytes_fn3 = CommonBytes(hdr_bits_fn3.data, 20)
+
+#tc.append_log(3, 'IP header checksum FN0: %d' % ip_hdr_checksum(hdr_bytes_fn0))
+#tc.append_log(3, 'IP header checksum FN1: %d' % ip_hdr_checksum(hdr_bytes_fn1))
+tc.append_log(3, 'IP header checksum FN2: %d' % ip_hdr_checksum(hdr_bytes_fn2))
+tc.append_log(3, 'IP header checksum FN3: %d' % ip_hdr_checksum(hdr_bytes_fn3))
+
+#hdr_bits = CommonBits(ip_version ,4) & \
+# CommonBits(ip_header_length ,4) & \
+# CommonBits(ip_services ,8) & \
+# CommonBits(ip_total_length ,16) & \
+# CommonBits(ip_identification ,16) & \
+# CommonBits(ip_flags ,3) & \
+# CommonBits(ip_fragment_offset ,13) & \
+# CommonBits(ip_time_to_live ,8) & \
+# CommonBits(ip_protocol ,8) & \
+# CommonBits(ip_header_checksum ,16) & \
+# CommonBits(ip_src_addr_fn0 ,32) & \
+# CommonBits(ip_dst_addr ,32)
+#
+#hdr_bytes = CommonBytes(hdr_bits.data, 20)
+#
+#print ip_hdr_checksum(hdr_bytes)
+
+# Write setting for the block generator:
+
+#ca.write(node_nrs=tc.nodeNrs[1],registers=[('register_name_0', 15)])
+#ca.write(node_nrs=tc.nodeNrs[1],registers=[('register_name_4', 20)])
+
+bg.write_block_gen_settings(samplesPerPacket=c_blocksize, blocksPerSync=c_nof_blocks_per_sync, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+
+
+# Configure 10G of FN2
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('eth_src_mac', eth_src_mac + 2)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_dst_mac)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_src_addr', ip_src_addr_fn2)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_dst_addr)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_header_checksum', ip_hdr_checksum(hdr_bytes_fn2))], regmap=dpotx_hdr_dat.regmap)
+
+# Configure 10G of FN3
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_src_mac', eth_src_mac + 3)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_dst_mac)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_src_addr', ip_src_addr_fn3)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_dst_addr)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_header_checksum', ip_hdr_checksum(hdr_bytes_fn3))], regmap=dpotx_hdr_dat.regmap)
+
+# Configure rx filter
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_src_mac + 3)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_src_addr_fn3)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('udp_dst_port', 4000)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_total_length', ip_total_length)],regmap=rx_filter_hdr.regmap)
+
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac_ena', 0)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr_ena', 0)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('ip_total_length_ena', 0)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[1], inst_nrs=tc.gpNumbers, registers=[('udp_dst_port_ena', 0)], regmap=rx_filter_hdr.regmap)
+
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac_ena', 0)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr_ena', 0)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('ip_total_length_ena', 0)], regmap=rx_filter_hdr.regmap)
+rx_filter_hdr.write(node_nrs=tc.nodeNrs[0], inst_nrs=tc.gpNumbers, registers=[('udp_dst_port_ena', 0)], regmap=rx_filter_hdr.regmap)
+
+
+
+################################################################################
+##
+## Write data and settings to block generator
+##
+################################################################################
+# Write setting for the block generator:
+bg.write_block_gen_settings(samplesPerPacket=c_blocksize+1, blocksPerSync=c_nof_blocks_per_sync, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+
+bg_data = []
+#bg_data.append(0xC7000022)
+for i in range(c_bg_ram_size):
+ bg_data.append(i)
+
+
+# Write the stimuli to the block generator and enable the block generator
+if c_write_block_gen == True:
+ for i in range(c_bg_nof_streams):
+ bg.write_waveform_ram(data=bg_data, channelNr= i)
+
+# BG: Enable the blockgenerator
+bg.write_enable()
+
+################################################################################
+##
+## Read data from the databuffer
+##
+################################################################################
+#time.sleep(10)
+db_out = []
+#ca.read(node_nrs=tc.nodeNrs[1],registers='register_name_0')
+
+
+do_until_ge(db.read_nof_words, ms_retry=1000, val=1024, s_timeout=3600)
+
+for i in range(1):
+ db_out.append(flatten(db.read_data_buffer(streamNr=i, n=2048, radix='uns', width=64, nofColumns=1))) #n=2048 (32 bit word) = 1024 (64 bit word)
+
+
+
+
+print db_out
+
diff --git a/applications/compaan/designs/compaan_unb1_10g_param_stream/tb/vhdl/tb_compaan_unb1_10g_param_stream.vhd b/applications/compaan/designs/compaan_unb1_10g_param_stream/tb/vhdl/tb_compaan_unb1_10g_param_stream.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3410ce740a4c5680d2032ef035f395fefba5da95
--- /dev/null
+++ b/applications/compaan/designs/compaan_unb1_10g_param_stream/tb/vhdl/tb_compaan_unb1_10g_param_stream.vhd
@@ -0,0 +1,163 @@
+
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . Test bench compaan_unb1_dp_offload.
+-- Description:
+-- . The block generator in the design is enabled by default.
+-- . Design 'compaan_unb1_dp_offload' requires the 1GbE demux to be set up so
+-- received streams are forwarded based on the received destination UDP port.
+-- This is done by /tb/python/tc_unb1_board1_dp_offload.py.
+-- Usage (manual mode, run compaan_unb1_dp_offload.py for auto mode):
+-- . Start ModelSim
+-- . lp compaan_unb1_dp_offload
+-- . mk compile
+-- . double click simulation configuration
+-- . as 8
+-- . run 2us (wait until MM master did the initial ETH settings before Python ETH access)
+-- . in separate console: python tc_unb1_board1_dp_offload.py --unb 0 --fn 0 -r 0:2 --sim
+-- . run -a
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_compaan_unb1_10g_param_stream IS
+END tb_compaan_unb1_10g_param_stream;
+
+ARCHITECTURE tb OF tb_compaan_unb1_10g_param_stream IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_unb1_board_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr_bg_db : NATURAL := 2; -- FN2
+ CONSTANT c_node_nr_app : NATURAL := 3; -- FN3
+ CONSTANT c_id_bg_db : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr_bg_db, c_unb1_board_nof_chip_w);
+ CONSTANT c_id_app : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr_app, c_unb1_board_nof_chip_w);
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+
+ CONSTANT c_eth_clk_period : TIME := 40 ns;
+ CONSTANT c_sa_clk_period : TIME := 6.4 ns;
+ CONSTANT c_clk_period : TIME := 5 ns;
+
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL sa_clk : STD_LOGIC := '1';
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ SIGNAL si_fn_0_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_1_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_2_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_3_lcu_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SIGNAL si_fn_0_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_1_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_2_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_3_lcu_rx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID_bg_db : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_bg_db;
+ SIGNAL ID_app : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_app;
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- Externally generated clocks
+ ----------------------------------------------------------------------------
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+ sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
+
+ ------------------------------------------------------------------------------
+ -- u_lcu
+ ------------------------------------------------------------------------------
+ u_lcu : ENTITY work.compaan_unb1_10g_bg_db
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb1_board_nr,
+ g_sim_node_nr => c_node_nr_bg_db
+ )
+ PORT MAP (
+ CLK => clk,
+ PPS => '0',
+ VERSION => VERSION,
+ ID => ID_bg_db,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+
+ -- Serial I/O
+ SI_FN_0_RX => si_fn_0_lcu_rx,
+ SI_FN_1_RX => si_fn_1_lcu_rx,
+ SI_FN_2_RX => si_fn_2_lcu_rx,
+ SI_FN_3_RX => si_fn_3_lcu_rx,
+ SI_FN_0_TX => si_fn_0_lcu_tx,
+ SI_FN_1_TX => si_fn_1_lcu_tx,
+ SI_FN_2_TX => si_fn_2_lcu_tx,
+ SI_FN_3_TX => si_fn_3_lcu_tx
+ );
+
+ ------------------------------------------------------------------------------
+ -- u_dut
+ ------------------------------------------------------------------------------
+ u_dut : ENTITY work.compaan_unb1_10g_param_stream
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb1_board_nr,
+ g_sim_node_nr => c_node_nr_app
+ )
+ PORT MAP (
+ CLK => clk,
+ PPS => '0',
+ VERSION => VERSION,
+ ID => ID_app,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+
+ -- Serial I/O
+ SI_FN_0_RX => si_fn_0_lcu_tx,
+ SI_FN_1_RX => si_fn_1_lcu_tx,
+ SI_FN_2_RX => si_fn_2_lcu_tx,
+ SI_FN_3_RX => si_fn_3_lcu_tx,
+ SI_FN_0_TX => si_fn_0_lcu_rx,
+ SI_FN_1_TX => si_fn_1_lcu_rx,
+ SI_FN_2_TX => si_fn_2_lcu_rx,
+ SI_FN_3_TX => si_fn_3_lcu_rx
+ );
+
+END tb;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/hdllib.cfg b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0a2495d2a345d9b065c33d27176dde4e8bf0b824
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/hdllib.cfg
@@ -0,0 +1,20 @@
+hdl_lib_name = compaandesign_com_param_stream2rtl_functions_1
+hdl_library_clause_name = compaandesign_com_param_stream2rtl_functions_1_lib
+hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/compaan_outlinedproc0.vhd
+ src/vhdl/compaan_outlinedproc0_pipeline.vhd
+ src/vhdl/transformer.vhd
+ src/vhdl/transformer_pipeline.vhd
+ src/vhdl/compaan_outlinedproc1.vhd
+ src/vhdl/compaan_outlinedproc1_pipeline.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3752cc86cd534864749694a354d069548f36ac7c
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd
@@ -0,0 +1,161 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc0 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc0;
+
+architecture RTL of compaan_outlinedproc0 is
+
+ component compaan_outlinedproc0_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+ end component;
+
+ component CONTROLLER is
+ generic (
+ N_STAGES : natural := 1;
+ BLOCKING : natural := 0
+ );
+ port (
+ READ : out std_logic;
+ EXIST : in std_logic;
+ WRITE : out std_logic;
+ FULL : in std_logic;
+ --
+ ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
+ STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
+ STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
+ --
+ CLK : in std_logic;
+ RST : in std_logic
+ );
+ end component;
+
+ constant c_BLOCKING : natural := 1;
+
+ signal sl_EXIST : std_logic;
+ signal sl_READ : std_logic;
+ signal sl_FULL : std_logic;
+ signal sl_WRITE : std_logic;
+ signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
+ --
+
+ --
+
+ --
+
+begin
+
+ -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+ sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+ -- Functional Evaluation. Only when all signals are high, we can set READF high.
+ READF <= (READF'range =>sl_READ);
+ sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+ WRITEF <= (WRITEF'range=>sl_WRITE);
+
+ PIPELINE : compaan_outlinedproc0_pipeline
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ -- Inputs
+ ip_tmp1 => ip_tmp1,
+ -- Iterators
+ it_i => it_i,
+ -- Outputs
+ op_tmp0 => op_tmp0,
+ --
+ ENi => sl_READ,
+ EN => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ ERROR => ERROR
+ );
+
+ CTRL : CONTROLLER
+ generic map (
+ N_STAGES => c_STAGES,
+ BLOCKING => c_BLOCKING
+ )
+ port map (
+ RST => RST,
+ CLK => CLK,
+ READ => sl_READ,
+ EXIST => sl_EXIST,
+ --
+ ENABLE_EX => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ --
+ WRITE => sl_WRITE,
+ FULL => sl_FULL
+ );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e4e2bbc7d4af14a9edb9b55baf91fce518bf2d5e
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd
@@ -0,0 +1,91 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc0_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+ --
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc0_pipeline;
+
+architecture RTL of compaan_outlinedproc0_pipeline is
+--
+ constant error_int : integer := -1;
+ constant reset_int : std_logic_vector(0 downto 0) := b"0";
+ -- Input registers
+ signal ipr_tmp1 : std_logic_vector(63 downto 0);
+
+ -- Iterator registers
+ signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Output signals
+
+ --
+ -- Your pipeline signals
+ --
+ -- STAGE_0
+ signal s0_tmp1 : std_logic_vector(63 downto 0);
+ signal r0_tmp1 : std_logic_vector(63 downto 0);
+
+begin
+
+ PIPE_REGS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RST='1') then
+ -- Something to reset?
+ else
+ if( ENi = '1' ) then
+ -- Input Registers
+ ipr_tmp1 <= ip_tmp1;
+ -- Iterator Registers
+ itr_i <= it_i;
+ end if;
+ -- Pipeline Depth: 1 stages
+ -- STAGE_0
+ if( EN(0) = '1' ) then
+ r0_tmp1 <= s0_tmp1;
+ end if;
+ end if;
+ end if;
+ end process; -- PIPE_REGS
+ --
+ -- Output
+ op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+ --
+ -- PIPE_COMB:
+ s0_tmp1 <= ipr_tmp1;
+ --
+ STALL_FRONT <= (others=>'0');
+ STALL_BACK <= (others=>'0');
+ ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c784274692f3f9816f36d31fc18accc19b0ca8cf
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd
@@ -0,0 +1,161 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc1 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc1;
+
+architecture RTL of compaan_outlinedproc1 is
+
+ component compaan_outlinedproc1_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+ end component;
+
+ component CONTROLLER is
+ generic (
+ N_STAGES : natural := 1;
+ BLOCKING : natural := 0
+ );
+ port (
+ READ : out std_logic;
+ EXIST : in std_logic;
+ WRITE : out std_logic;
+ FULL : in std_logic;
+ --
+ ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
+ STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
+ STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
+ --
+ CLK : in std_logic;
+ RST : in std_logic
+ );
+ end component;
+
+ constant c_BLOCKING : natural := 1;
+
+ signal sl_EXIST : std_logic;
+ signal sl_READ : std_logic;
+ signal sl_FULL : std_logic;
+ signal sl_WRITE : std_logic;
+ signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
+ --
+
+ --
+
+ --
+
+begin
+
+ -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+ sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+ -- Functional Evaluation. Only when all signals are high, we can set READF high.
+ READF <= (READF'range =>sl_READ);
+ sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+ WRITEF <= (WRITEF'range=>sl_WRITE);
+
+ PIPELINE : compaan_outlinedproc1_pipeline
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ -- Inputs
+ ip_tmp1 => ip_tmp1,
+ -- Iterators
+ it_x => it_x,
+ -- Outputs
+ op_tmp0 => op_tmp0,
+ --
+ ENi => sl_READ,
+ EN => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ ERROR => ERROR
+ );
+
+ CTRL : CONTROLLER
+ generic map (
+ N_STAGES => c_STAGES,
+ BLOCKING => c_BLOCKING
+ )
+ port map (
+ RST => RST,
+ CLK => CLK,
+ READ => sl_READ,
+ EXIST => sl_EXIST,
+ --
+ ENABLE_EX => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ --
+ WRITE => sl_WRITE,
+ FULL => sl_FULL
+ );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7bea02bb535fb088452dba24c862af6d9930fae3
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd
@@ -0,0 +1,91 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc1_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+ --
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc1_pipeline;
+
+architecture RTL of compaan_outlinedproc1_pipeline is
+--
+ constant error_int : integer := -1;
+ constant reset_int : std_logic_vector(0 downto 0) := b"0";
+ -- Input registers
+ signal ipr_tmp1 : std_logic_vector(63 downto 0);
+
+ -- Iterator registers
+ signal itr_x : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Output signals
+
+ --
+ -- Your pipeline signals
+ --
+ -- STAGE_0
+ signal s0_tmp1 : std_logic_vector(63 downto 0);
+ signal r0_tmp1 : std_logic_vector(63 downto 0);
+
+begin
+
+ PIPE_REGS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RST='1') then
+ -- Something to reset?
+ else
+ if( ENi = '1' ) then
+ -- Input Registers
+ ipr_tmp1 <= ip_tmp1;
+ -- Iterator Registers
+ itr_x <= it_x;
+ end if;
+ -- Pipeline Depth: 1 stages
+ -- STAGE_0
+ if( EN(0) = '1' ) then
+ r0_tmp1 <= s0_tmp1;
+ end if;
+ end if;
+ end if;
+ end process; -- PIPE_REGS
+ --
+ -- Output
+ op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+ --
+ -- PIPE_COMB:
+ s0_tmp1 <= ipr_tmp1;
+ --
+ STALL_FRONT <= (others=>'0');
+ STALL_BACK <= (others=>'0');
+ ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0db3f33ee3360057e82306426e20e3ba5ca55885
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer.vhd
@@ -0,0 +1,167 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity transformer is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Non Syncronized Parameters
+ rf_brightness : in std_logic_vector( 32-1 downto 0); -- input
+ -- Inputs
+ ip_a : in std_logic_vector(63 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(63 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end transformer;
+
+architecture RTL of transformer is
+
+ component transformer_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Non Syncronized Parameters
+ rf_brightness : in std_logic_vector( 32-1 downto 0); --input
+ -- Inputs
+ ip_a : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(63 downto 0);
+
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+ end component;
+
+ component CONTROLLER is
+ generic (
+ N_STAGES : natural := 1;
+ BLOCKING : natural := 0
+ );
+ port (
+ READ : out std_logic;
+ EXIST : in std_logic;
+ WRITE : out std_logic;
+ FULL : in std_logic;
+ --
+ ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
+ STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
+ STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
+ --
+ CLK : in std_logic;
+ RST : in std_logic
+ );
+ end component;
+
+ constant c_BLOCKING : natural := 1;
+
+ signal sl_EXIST : std_logic;
+ signal sl_READ : std_logic;
+ signal sl_FULL : std_logic;
+ signal sl_WRITE : std_logic;
+ signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
+ --
+
+ --
+
+ --
+
+begin
+
+ -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+ sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+ -- Functional Evaluation. Only when all signals are high, we can set READF high.
+ READF <= (READF'range =>sl_READ);
+ sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+ WRITEF <= (WRITEF'range=>sl_WRITE);
+
+ PIPELINE : transformer_pipeline
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ -- Non Syncronized Parameters
+ rf_brightness => rf_brightness,
+ -- Inputs
+ ip_a => ip_a,
+ -- Iterators
+ it_j => it_j,
+ -- Outputs
+ op_b => op_b,
+ --
+ ENi => sl_READ,
+ EN => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ ERROR => ERROR
+ );
+
+ CTRL : CONTROLLER
+ generic map (
+ N_STAGES => c_STAGES,
+ BLOCKING => c_BLOCKING
+ )
+ port map (
+ RST => RST,
+ CLK => CLK,
+ READ => sl_READ,
+ EXIST => sl_EXIST,
+ --
+ ENABLE_EX => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ --
+ WRITE => sl_WRITE,
+ FULL => sl_FULL
+ );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer_pipeline.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ae11626e463320233cf7f2569af7a4c3b575bc95
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer_pipeline.vhd
@@ -0,0 +1,101 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity transformer_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Non Syncronized Parameters
+ rf_brightness : in std_logic_vector( 32-1 downto 0); -- input
+ -- Inputs
+ ip_a : in std_logic_vector(63 downto 0);
+ ip_brightness : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(63 downto 0);
+ --
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+end transformer_pipeline;
+
+architecture RTL of transformer_pipeline is
+--
+ constant error_int : integer := -1;
+ constant reset_int : std_logic_vector(0 downto 0) := b"0";
+ -- Input registers
+ signal ipr_a : std_logic_vector(63 downto 0);
+
+ signal ipr_brightness : std_logic_vector(31 downto 0);
+
+ -- Iterator registers
+ signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Output signals
+
+ --
+ -- Your pipeline signals
+ --
+ -- STAGE_0
+ signal s0_a : std_logic_vector(63 downto 0);
+ signal r0_a : std_logic_vector(63 downto 0);
+ signal s0_brightness : std_logic_vector(31 downto 0);
+ signal r0_brightness : std_logic_vector(31 downto 0);
+
+begin
+
+ PIPE_REGS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RST='1') then
+ -- Something to reset?
+ else
+ if( ENi = '1' ) then
+ -- Input Registers
+ ipr_a <= ip_a;
+ ipr_brightness <= ip_brightness;
+ -- Iterator Registers
+ itr_j <= it_j;
+ end if;
+ -- Pipeline Depth: 1 stages
+ -- STAGE_0
+ if( EN(0) = '1' ) then
+ r0_a <= s0_a;
+ r0_brightness <= s0_brightness;
+ end if;
+ end if;
+ end if;
+ end process; -- PIPE_REGS
+ --
+ -- Output
+ op_b <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(rf_brightness), op_b'Length));
+ --
+ -- PIPE_COMB:
+ s0_a <= ipr_a;
+ s0_brightness <= ipr_brightness;
+ --
+ STALL_FRONT <= (others=>'0');
+ STALL_BACK <= (others=>'0');
+ ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/hdllib.cfg b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..672baaeb5d784abf32f542fcc07b52ad62763970
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_param_stream2rtl_hwn_nd_2_1
+hdl_library_clause_name = compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib
+hdl_lib_uses_synth = compaandesign_com_param_stream2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/param_stream2rtl_hwn_nd_2_execution_unit.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_rd.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_wr.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_2.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..60f440383faa9dff3c1c3cf78dbe70532a35986f
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2.vhd
@@ -0,0 +1,462 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity param_stream2rtl_hwn_nd_2 is
+ generic (
+ STIM_DIR : string := "bla";
+ RESET_HIGH : natural := 1;
+ PAR_WIDTH : natural := 16;
+ QUANT : natural := 32;
+ WRAP : boolean := true
+ );
+ port (
+
+ -- Dataflow input interfaces
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(63 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+
+ -- Dataflow Control Input interfaces
+ -- Dataflow output interfaces
+ -- ED_1 : out_0
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic
+ );
+end param_stream2rtl_hwn_nd_2;
+
+architecture RTL of param_stream2rtl_hwn_nd_2 is
+ --
+ -- ====================================
+ -- = Constants declaration =
+ -- ====================================
+ -- Setting the parameters of the HW Node
+ constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
+ constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
+ constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
+ constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+ constant c_COUNTERS : natural := 1; -- number of iterators
+ -- ===========================================
+ -- = Iterators run from Inner to Outer loop =
+ -- ===========================================
+ constant c_CNTR_QUANT : natural := 5;
+ constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
+ constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
+ constant c_STAGES : natural := 1; -- number of pipeline stages or delay
+ constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
+ constant c_WRAP : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+ constant c_EXT_PAR : natural := 0; -- number of external parameters
+ constant c_INT_PAR : natural := 0; -- number of internal parameters
+ constant c_N_PAR : natural := 0; -- no parameters are used
+ constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+ constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+ (0,0,0,0), (0,0,0,0) -- two dummy elements
+ );
+ --
+ -- ====================================
+ -- = Components declaration =
+ -- ====================================
+ component param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+ end component;
+
+ component READ_MUX is
+ generic (
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+ CLK : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+ end component;
+
+ component WRITE_DEMUX is
+ generic (
+ N_PORTS : natural := 1
+ );
+ port(
+ WRITES : out std_logic_vector(N_PORTS-1 downto 0);
+ WRITE : in std_logic;
+
+ FULLS : in std_logic_vector(N_PORTS-1 downto 0);
+ FULL : out std_logic;
+
+ WRITE_EN : in std_logic;
+ WRITE_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+
+ component param_stream2rtl_EXECUTION_UNIT_hwn_nd_2 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ QUANT : natural := 32;
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+ -- Func. Input parameters
+ IN_PORT_0 : in std_logic_vector(63 downto 0); -- tmp1
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Func. Output parameters
+ OUT_PORT_0 : out std_logic_vector(63 downto 0); -- tmp0
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ component INTERNAL_PARAMETERS is
+ generic (
+ PAR_BITWIDTH : natural:=1;
+ PAR_VECTOR : t_par_vector;
+ N_PAR : natural:=0;
+ START_IN_RUN : boolean := FALSE
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ HALT_RD : out std_logic;
+ HALT_WR : out std_logic;
+ SOF_RD : in std_logic;
+ SOF_WR : in std_logic;
+ LOAD_PARAM : out std_logic;
+
+ par_one_in_Rd : out std_logic;
+ par_one_in_Din : in std_logic_vector(32-1 downto 0);
+ par_one_in_Exist : in std_logic;
+ par_one_in_CLK : out std_logic;
+ par_one_in_CTRL : in std_logic;
+
+ PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+ PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+ );
+ end component;
+
+ --
+ -- ====================================
+ -- = Signals declaration =
+ -- ====================================
+ --
+ -- HW Node Input Ports
+ signal sl_IN_PORTS_0 : std_logic_vector(1*64-1 downto 0); -- tmp1
+ signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ --
+ -- Func. Input parameters
+ signal sl_in_port_0 : std_logic_vector(63 downto 0); -- tmp1
+ signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ --
+ signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+ --
+ -- HW Node Output Ports
+ signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ --
+ -- Func. Output parameters
+ signal sl_out_port_0 : std_logic_vector(63 downto 0); -- tmp0
+ signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ --
+ --
+ signal sl_halt : std_logic;
+ signal sl_halted : std_logic;
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
+ signal sl_param_halt_wr : std_logic;
+ signal sl_param_halt_rd : std_logic;
+ signal sl_done_wr : std_logic;
+ signal sl_done_rd : std_logic;
+ signal sl_stop_wr : std_logic;
+ signal sl_stop_rd : std_logic;
+ signal sl_fire_wr : std_logic;
+ signal sl_fire_rd : std_logic;
+ signal sl_sof_wr : std_logic;
+ signal sl_sof_rd : std_logic;
+ signal sl_error : std_logic;
+ signal sl_load_param : std_logic;
+
+ --
+ -- Parameter related signals
+ signal sl_param_fifo_full : std_logic;
+ signal sl_sync_num : std_logic_vector(9 downto 0);
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when RESET_HIGH=1 else not RST;
+ data_in_CLK <= CLK;
+ ND_2OP_1_CLK <= CLK;
+
+ --
+ -- ==========================================================
+ -- = HWN Input related modules =
+ -- ==========================================================
+ -- Func. Input param. "tmp1"
+ RD_MUX_0 : READ_MUX
+ generic map (
+ N_PORTS => 1,
+ PORT_WIDTH => 64
+ )
+ port map (
+ IN_PORTS => sl_IN_PORTS_0,
+ EXISTS => sl_EXISTS(0 downto 0),
+ READS => sl_READS(0 downto 0),
+ SOFS => sl_CTRLS(0 downto 0),
+
+ OUT_PORT => sl_in_port_0,
+ EXIST => sl_exist(0),
+ READ => sl_read(0),
+ SOF => sl_sof_rd,
+ CLK => CLK,
+
+ READ_EN => sl_read_en(0),
+ READ_ST => sl_read_st(0),
+ CONTROL => sl_control_rd(0 downto 0),
+ OBTAIN => sl_obtain_rd(0 downto 0),
+ RELEASE => sl_release_rd(0 downto 0)
+ );
+
+ data_in_Rd <= sl_READS(0);
+
+ sl_IN_PORTS_0 <= data_in_Din;
+
+ sl_EXISTS(0) <= data_in_Exist ;
+ sl_CTRLS(0) <= data_in_CTRL ;
+
+ EVAL_RD : param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_2
+ generic map (
+ N_IN_PORTS => c_IN_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ REG_CNTRS => sl_REG_CNTRS_RD,
+ READ_EN => sl_read_en,
+ READ_ST => sl_read_st,
+ HALT => sl_halt_rd,
+ FIRE => sl_fire_rd,
+ DONE => sl_done_rd,
+ STOP => sl_stop_rd,
+ CONTROL => sl_control_rd,
+ OBTAIN => sl_obtain_rd,
+ RELEASE => sl_release_rd
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Output related modules =
+ -- ==========================================================
+ --
+ -- Func. Output param. "tmp0"
+ DEMUX_0 : WRITE_DEMUX
+ generic map (
+ N_PORTS => 1
+ )
+ port map (
+ WRITES => sl_WRITES(0 downto 0),
+ FULLS => sl_FULLS(0 downto 0),
+ CONTROL => sl_lortnoc_wr(0 downto 0),
+ WRITE => sl_write(0),
+ FULL => sl_full(0),
+ WRITE_EN => sl_write_en(0),
+ WRITE_ST => sl_write_st(0)
+ );
+ --
+ ND_2OP_1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
+ ND_2OP_1_CTRL <= sl_sof_wr ;
+ ND_2OP_1_Wr <= sl_WRITES(0);
+ sl_FULLS(0) <= ND_2OP_1_Full;
+ sl_lortnoc_wr(0) <= sl_control_wr(0);
+ --
+ --
+ EVAL_WR : param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_2
+ generic map (
+ N_OUT_PORTS => c_OUT_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ WRITE_EN => sl_write_en,
+ WRITE_ST => sl_write_st,
+ HALT => sl_halt_wr,
+ FIRE => sl_fire_wr,
+ DONE => sl_done_wr,
+ STOP => sl_stop_wr,
+ CONTROL => sl_control_wr
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Execution Unit =
+ -- ==========================================================
+ EX : param_stream2rtl_EXECUTION_UNIT_hwn_nd_2
+ generic map (
+ N_INPORTS => c_IN_FUNC_VAR,
+ N_OUTPORTS => c_OUT_FUNC_VAR,
+ IP_RESET => c_IP_RESET,
+ QUANT => QUANT,
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => c_COUNTERS,
+ CNTR_QUANT => c_CNTR_QUANT,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Iterators
+ REG_CNTRS_RD => sl_REG_CNTRS_RD,
+ -- Func. Input parameters
+ IN_PORT_0 => sl_in_port_0,
+ READ => sl_read,
+ EXIST => sl_exist,
+ -- Func. Output parameters
+ OUT_PORT_0 => sl_out_port_0,
+ WRITE => sl_write,
+ FULL => sl_full,
+ --
+ STOP_WR => sl_stop_wr,
+ STOP_RD => sl_stop_rd,
+ ERROR => sl_error
+ );
+
+ -- ==========================================================
+ -- = PARAMETERIZATION =
+ -- ==========================================================
+ -- no parameters
+ sl_halt_rd <= '0';
+ sl_halt_wr <= '0';
+-- sl_halted <= sl_sof_rd;
+ STOP <= sl_done_wr;
+ ERROR <= sl_error;
+ BLOCK_RD <= not ( ( sl_READS(0) ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_rd.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0c2cbd4381e79fd1f81799ff849b1a2b22e269e2
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_rd.vhd
@@ -0,0 +1,286 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(0 downto 0);
+ READ_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+end param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_2;
+
+architecture RTL of param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOAD : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_i, sl_high_i : integer;
+ signal sl_loop_i, sl_loop_i_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_count : std_logic;
+
+ -- alias signals
+ alias update_i : std_logic is sl_cntr_en(0);
+ alias load_i : std_logic is sl_load(0);
+
+ -- Trigger signals
+ signal sl_trigger_i : std_logic;
+
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- Multirate related signals
+ signal sl_bla_en : std_logic_vector(0 downto 0);
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function input parameter "data_in[i]", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+
+ signal e0, e1 : boolean;
+
+ signal sl_obtain0 : std_logic;
+ signal sl_release0 : std_logic;
+
+ -- define control variables
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ -- =============================================
+ -- = Parameter Functions
+ -- =============================================
+ sl_cnt_rst <= '0';
+ sl_halt <= HALT;
+
+ -- END of Parameter definitions
+ sl_loop_i <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_i <= 0;
+ sl_high_i <= 9;
+
+
+ load_i <= '0';
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+ -- Special definitions
+
+ -- Entity and control variables
+ -- Release matrix expressions
+ e0 <= sl_loop_i_rg>=0;
+ e1 <= -sl_loop_i_rg + 9>=0;
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Read Port in_1 : EXTERNAL
+ sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
+ sl_release0 <= ('1');
+
+ sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
+ OBTAIN(0) <= sl_obtain0;
+ RELEASE(0) <= sl_release0;
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function input parameter "data_in[i]", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOAD => '0',
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ -- READ_EN indicates if READ_MUX can read data
+ sl_bla_en <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ READ_EN <= (others=>'0') when (HALT='1') else sl_bla_en;
+ sl_mr_en <= READ_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+ CNTR_RD : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOAD => sl_load(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true) then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ REG_CNTRS <= sl_reg_cntrs;
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ --
+ sl_count <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+ sl_cntr_en(0) <= sl_count; -- makes the EVAL_LOGIC count
+ --
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
+ --
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_wr.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4e1d43f013babacda8ee760c60981544a747f661
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_wr.vhd
@@ -0,0 +1,273 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ WRITE_EN : out std_logic_vector(0 downto 0);
+ WRITE_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+end param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_2;
+
+architecture RTL of param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOAD : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ -- Multirate related signals
+ signal sl_bla_en : std_logic_vector(0 downto 0);
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function output parameter "out_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_i, sl_high_i : integer;
+ signal sl_loop_i, sl_loop_i_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_count : std_logic;
+ --
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- alias signals
+ alias update_i : std_logic is sl_cntr_en(0);
+ --
+ alias load_i : std_logic is sl_load(0);
+ -- Trigger signals
+ signal sl_trigger_i : std_logic;
+
+
+ -- define control variables
+ -- MOD related signals
+
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= HALT;
+ -- END of Parameter definitions
+
+ sl_loop_i <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_i <= 0;
+ sl_high_i <= 9;
+
+
+ load_i <= '0';
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+
+ -- Special definitions
+
+ -- Entity and control variables
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Write Port out_1 : ED_1
+ sl_CONTROL(0) <= sl_fire and ('1');
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function output parameter "out_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOAD => '0',
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ -- WRITE_EN indicates if date can be written to WRITE_MUX
+ sl_bla_en <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ WRITE_EN <= (others=>'0') when (HALT='1') else sl_bla_en;
+ --
+ sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+ CNTR_WR : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOAD => sl_load(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true) then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ --
+ sl_count <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+ sl_cntr_en(0) <= sl_count; -- makes the EVAL_LOGIC count
+ --
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
+ --
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_execution_unit.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..49073ba4474398770a88c8572c697db73cd483a1
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_execution_unit.vhd
@@ -0,0 +1,109 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_param_stream2rtl_functions_1_lib;
+use compaandesign_com_param_stream2rtl_functions_1_lib.all;
+
+entity param_stream2rtl_EXECUTION_UNIT_hwn_nd_2 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ STIM_DIR : string := "bla";
+ QUANT : natural := 32;
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Funtion Input parameters
+ IN_PORT_0 : in std_logic_vector(63 downto 0); -- Param. "tmp1"
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+ -- Funtion Output parameters
+ OUT_PORT_0 : out std_logic_vector(63 downto 0); -- Param. "tmp0"
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end param_stream2rtl_EXECUTION_UNIT_hwn_nd_2 ;
+
+-- Laura implementation
+architecture Laura of param_stream2rtl_EXECUTION_UNIT_hwn_nd_2 is
+
+ component compaan_outlinedproc0 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when IP_RESET=1 else not RST;
+
+ FUNC : compaan_outlinedproc0
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Inputs
+ ip_tmp1 => IN_PORT_0,
+ -- Iterators
+ it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+ EXIST => EXIST,
+ READF => READ,
+ -- Outputs
+ op_tmp0 => OUT_PORT_0,
+ FULL => FULL,
+ WRITEF=> WRITE,
+ --
+ STOP_RD => STOP_RD,
+ STOP_WR => STOP_WR,
+ ERROR => ERROR
+ );
+
+end Laura;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/hdllib.cfg b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4438be39e0666307ef697a14a69d7c4c22c110a0
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_param_stream2rtl_hwn_nd_3_1
+hdl_library_clause_name = compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib
+hdl_lib_uses_synth = compaandesign_com_param_stream2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/param_stream2rtl_hwn_nd_3_execution_unit.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_rd.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_wr.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_3.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a7d055704a352dede507cf9276413c4d8aba380d
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3.vhd
@@ -0,0 +1,469 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity param_stream2rtl_hwn_nd_3 is
+ generic (
+ STIM_DIR : string := "bla";
+ RESET_HIGH : natural := 1;
+ PAR_WIDTH : natural := 16;
+ QUANT : natural := 32;
+ WRAP : boolean := true
+ );
+ port (
+ -- Non Syncronized Parameters
+ rf_brightness : in std_logic_vector( 32-1 downto 0); -- input
+
+ -- Dataflow input interfaces
+ -- ED_1 : in_0
+ ND_3IP_1_Rd : out std_logic;
+ ND_3IP_1_Din : in std_logic_vector(63 downto 0);
+ ND_3IP_1_Exist : in std_logic;
+ ND_3IP_1_CLK : out std_logic;
+ ND_3IP_1_CTRL : in std_logic;
+
+ -- Dataflow Control Input interfaces
+ -- Dataflow output interfaces
+ -- ED_2 : out_0
+ ND_3OP_1_Wr : out std_logic;
+ ND_3OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_3OP_1_Full : in std_logic;
+ ND_3OP_1_CLK : out std_logic;
+ ND_3OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic
+ );
+end param_stream2rtl_hwn_nd_3;
+
+architecture RTL of param_stream2rtl_hwn_nd_3 is
+ --
+ -- ====================================
+ -- = Constants declaration =
+ -- ====================================
+ -- Setting the parameters of the HW Node
+ constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
+ constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
+ constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
+ constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+ constant c_COUNTERS : natural := 1; -- number of iterators
+ -- ===========================================
+ -- = Iterators run from Inner to Outer loop =
+ -- ===========================================
+ constant c_CNTR_QUANT : natural := 5;
+ constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
+ constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
+ constant c_STAGES : natural := 1; -- number of pipeline stages or delay
+ constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
+ constant c_WRAP : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+ constant c_EXT_PAR : natural := 0; -- number of external parameters
+ constant c_INT_PAR : natural := 0; -- number of internal parameters
+ constant c_N_PAR : natural := 0; -- no parameters are used
+ constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+ constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+ (0,0,0,0), (0,0,0,0) -- two dummy elements
+ );
+ --
+ -- ====================================
+ -- = Components declaration =
+ -- ====================================
+ component param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_3 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+ end component;
+
+ component READ_MUX is
+ generic (
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+ CLK : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_3 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+ end component;
+
+ component WRITE_DEMUX is
+ generic (
+ N_PORTS : natural := 1
+ );
+ port(
+ WRITES : out std_logic_vector(N_PORTS-1 downto 0);
+ WRITE : in std_logic;
+
+ FULLS : in std_logic_vector(N_PORTS-1 downto 0);
+ FULL : out std_logic;
+
+ WRITE_EN : in std_logic;
+ WRITE_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+
+ component param_stream2rtl_EXECUTION_UNIT_hwn_nd_3 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ QUANT : natural := 32;
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ -- Non Syncronized Parameters
+ rf_brightness : in std_logic_vector( 32-1 downto 0); -- input
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+ -- Func. Input parameters
+ IN_PORT_0 : in std_logic_vector(63 downto 0); -- a
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Func. Output parameters
+ OUT_PORT_0 : out std_logic_vector(63 downto 0); -- b
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ component INTERNAL_PARAMETERS is
+ generic (
+ PAR_BITWIDTH : natural:=1;
+ PAR_VECTOR : t_par_vector;
+ N_PAR : natural:=0;
+ START_IN_RUN : boolean := FALSE
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ HALT_RD : out std_logic;
+ HALT_WR : out std_logic;
+ SOF_RD : in std_logic;
+ SOF_WR : in std_logic;
+ LOAD_PARAM : out std_logic;
+
+ par_one_in_Rd : out std_logic;
+ par_one_in_Din : in std_logic_vector(32-1 downto 0);
+ par_one_in_Exist : in std_logic;
+ par_one_in_CLK : out std_logic;
+ par_one_in_CTRL : in std_logic;
+
+ PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+ PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+ );
+ end component;
+
+ --
+ -- ====================================
+ -- = Signals declaration =
+ -- ====================================
+ --
+ -- HW Node Input Ports
+ signal sl_IN_PORTS_0 : std_logic_vector(1*64-1 downto 0); -- a
+ signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ --
+ -- Func. Input parameters
+ signal sl_in_port_0 : std_logic_vector(63 downto 0); -- a
+ signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ --
+ signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+ --
+ -- HW Node Output Ports
+ signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ --
+ -- Func. Output parameters
+ signal sl_out_port_0 : std_logic_vector(63 downto 0); -- b
+ signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ --
+ --
+ signal sl_halt : std_logic;
+ signal sl_halted : std_logic;
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
+ signal sl_param_halt_wr : std_logic;
+ signal sl_param_halt_rd : std_logic;
+ signal sl_done_wr : std_logic;
+ signal sl_done_rd : std_logic;
+ signal sl_stop_wr : std_logic;
+ signal sl_stop_rd : std_logic;
+ signal sl_fire_wr : std_logic;
+ signal sl_fire_rd : std_logic;
+ signal sl_sof_wr : std_logic;
+ signal sl_sof_rd : std_logic;
+ signal sl_error : std_logic;
+ signal sl_load_param : std_logic;
+
+ --
+ -- Parameter related signals
+ signal sl_param_fifo_full : std_logic;
+ signal sl_sync_num : std_logic_vector(9 downto 0);
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when RESET_HIGH=1 else not RST;
+ ND_3IP_1_CLK <= CLK;
+ ND_3OP_1_CLK <= CLK;
+
+ --
+ -- ==========================================================
+ -- = HWN Input related modules =
+ -- ==========================================================
+ -- Func. Input param. "a"
+ RD_MUX_0 : READ_MUX
+ generic map (
+ N_PORTS => 1,
+ PORT_WIDTH => 64
+ )
+ port map (
+ IN_PORTS => sl_IN_PORTS_0,
+ EXISTS => sl_EXISTS(0 downto 0),
+ READS => sl_READS(0 downto 0),
+ SOFS => sl_CTRLS(0 downto 0),
+
+ OUT_PORT => sl_in_port_0,
+ EXIST => sl_exist(0),
+ READ => sl_read(0),
+ SOF => sl_sof_rd,
+ CLK => CLK,
+
+ READ_EN => sl_read_en(0),
+ READ_ST => sl_read_st(0),
+ CONTROL => sl_control_rd(0 downto 0),
+ OBTAIN => sl_obtain_rd(0 downto 0),
+ RELEASE => sl_release_rd(0 downto 0)
+ );
+
+ ND_3IP_1_Rd <= sl_READS(0);
+
+ sl_IN_PORTS_0 <= ND_3IP_1_Din;
+
+ sl_EXISTS(0) <= ND_3IP_1_Exist ;
+ sl_CTRLS(0) <= ND_3IP_1_CTRL ;
+
+ EVAL_RD : param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_3
+ generic map (
+ N_IN_PORTS => c_IN_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ REG_CNTRS => sl_REG_CNTRS_RD,
+ READ_EN => sl_read_en,
+ READ_ST => sl_read_st,
+ HALT => sl_halt_rd,
+ FIRE => sl_fire_rd,
+ DONE => sl_done_rd,
+ STOP => sl_stop_rd,
+ CONTROL => sl_control_rd,
+ OBTAIN => sl_obtain_rd,
+ RELEASE => sl_release_rd
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Output related modules =
+ -- ==========================================================
+ --
+ -- Func. Output param. "b"
+ DEMUX_0 : WRITE_DEMUX
+ generic map (
+ N_PORTS => 1
+ )
+ port map (
+ WRITES => sl_WRITES(0 downto 0),
+ FULLS => sl_FULLS(0 downto 0),
+ CONTROL => sl_lortnoc_wr(0 downto 0),
+ WRITE => sl_write(0),
+ FULL => sl_full(0),
+ WRITE_EN => sl_write_en(0),
+ WRITE_ST => sl_write_st(0)
+ );
+ --
+ ND_3OP_1_Dout <= sl_out_port_0; -- Func. Output param. "b"
+ ND_3OP_1_CTRL <= sl_sof_wr ;
+ ND_3OP_1_Wr <= sl_WRITES(0);
+ sl_FULLS(0) <= ND_3OP_1_Full;
+ sl_lortnoc_wr(0) <= sl_control_wr(0);
+ --
+ --
+ EVAL_WR : param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_3
+ generic map (
+ N_OUT_PORTS => c_OUT_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ WRITE_EN => sl_write_en,
+ WRITE_ST => sl_write_st,
+ HALT => sl_halt_wr,
+ FIRE => sl_fire_wr,
+ DONE => sl_done_wr,
+ STOP => sl_stop_wr,
+ CONTROL => sl_control_wr
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Execution Unit =
+ -- ==========================================================
+ EX : param_stream2rtl_EXECUTION_UNIT_hwn_nd_3
+ generic map (
+ N_INPORTS => c_IN_FUNC_VAR,
+ N_OUTPORTS => c_OUT_FUNC_VAR,
+ IP_RESET => c_IP_RESET,
+ QUANT => QUANT,
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => c_COUNTERS,
+ CNTR_QUANT => c_CNTR_QUANT,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- RegFile
+ rf_brightness => rf_brightness,
+ -- Iterators
+ REG_CNTRS_RD => sl_REG_CNTRS_RD,
+ -- Func. Input parameters
+ IN_PORT_0 => sl_in_port_0,
+ READ => sl_read,
+ EXIST => sl_exist,
+ -- Func. Output parameters
+ OUT_PORT_0 => sl_out_port_0,
+ WRITE => sl_write,
+ FULL => sl_full,
+ --
+ STOP_WR => sl_stop_wr,
+ STOP_RD => sl_stop_rd,
+ ERROR => sl_error
+ );
+
+ -- ==========================================================
+ -- = PARAMETERIZATION =
+ -- ==========================================================
+ -- no parameters
+ sl_halt_rd <= '0';
+ sl_halt_wr <= '0';
+-- sl_halted <= sl_sof_rd;
+ STOP <= sl_done_wr;
+ ERROR <= sl_error;
+ BLOCK_RD <= not ( ( sl_READS(0) ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_rd.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f8ba87e310ff1a1d573f1115c0327970e0add39f
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_rd.vhd
@@ -0,0 +1,283 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_3 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(0 downto 0);
+ READ_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+end param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_3;
+
+architecture RTL of param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_3 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOAD : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_j, sl_high_j : integer;
+ signal sl_loop_j, sl_loop_j_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_count : std_logic;
+
+ -- alias signals
+ alias update_j : std_logic is sl_cntr_en(0);
+ alias load_j : std_logic is sl_load(0);
+
+ -- Trigger signals
+ signal sl_trigger_j : std_logic;
+
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- Multirate related signals
+ signal sl_bla_en : std_logic_vector(0 downto 0);
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function input parameter "in_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+
+
+ signal sl_obtain0 : std_logic;
+ signal sl_release0 : std_logic;
+
+ -- define control variables
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ -- =============================================
+ -- = Parameter Functions
+ -- =============================================
+ sl_cnt_rst <= '0';
+ sl_halt <= HALT;
+
+ -- END of Parameter definitions
+ sl_loop_j <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_j <= 0;
+ sl_high_j <= 9;
+
+
+ load_j <= '0';
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+ -- Special definitions
+
+ -- Entity and control variables
+ -- Release matrix expressions
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Read Port ND_3IP_1 Argument in_1 : ED_1 : 0 of type IOMM
+ sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
+ sl_release0 <= ('1');
+
+ sl_CONTROL(0) <= sl_fire and ('1');
+ OBTAIN(0) <= sl_obtain0;
+ RELEASE(0) <= sl_release0;
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function input parameter "in_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOAD => '0',
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ -- READ_EN indicates if READ_MUX can read data
+ sl_bla_en <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ READ_EN <= (others=>'0') when (HALT='1') else sl_bla_en;
+ sl_mr_en <= READ_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+ CNTR_RD : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOAD => sl_load(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true) then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ REG_CNTRS <= sl_reg_cntrs;
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ --
+ sl_count <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+ sl_cntr_en(0) <= sl_count; -- makes the EVAL_LOGIC count
+ --
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
+ --
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_wr.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cd6f2d284e64d0847aa17d708a8a7a4d4a1c0f90
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_wr.vhd
@@ -0,0 +1,273 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_3 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ WRITE_EN : out std_logic_vector(0 downto 0);
+ WRITE_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+end param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_3;
+
+architecture RTL of param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_3 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOAD : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ -- Multirate related signals
+ signal sl_bla_en : std_logic_vector(0 downto 0);
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function output parameter "out_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_j, sl_high_j : integer;
+ signal sl_loop_j, sl_loop_j_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_count : std_logic;
+ --
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- alias signals
+ alias update_j : std_logic is sl_cntr_en(0);
+ --
+ alias load_j : std_logic is sl_load(0);
+ -- Trigger signals
+ signal sl_trigger_j : std_logic;
+
+
+ -- define control variables
+ -- MOD related signals
+
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= HALT;
+ -- END of Parameter definitions
+
+ sl_loop_j <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_j <= 0;
+ sl_high_j <= 9;
+
+
+ load_j <= '0';
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+
+ -- Special definitions
+
+ -- Entity and control variables
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Write Port out_1 : ED_2
+ sl_CONTROL(0) <= sl_fire and ('1');
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function output parameter "out_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOAD => '0',
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ -- WRITE_EN indicates if date can be written to WRITE_MUX
+ sl_bla_en <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ WRITE_EN <= (others=>'0') when (HALT='1') else sl_bla_en;
+ --
+ sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+ CNTR_WR : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOAD => sl_load(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true) then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ --
+ sl_count <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+ sl_cntr_en(0) <= sl_count; -- makes the EVAL_LOGIC count
+ --
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
+ --
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_execution_unit.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ff1cb8cd41f61d1b3477ea5288a56ddac65a8121
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_execution_unit.vhd
@@ -0,0 +1,115 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_param_stream2rtl_functions_1_lib;
+use compaandesign_com_param_stream2rtl_functions_1_lib.all;
+
+entity param_stream2rtl_EXECUTION_UNIT_hwn_nd_3 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ STIM_DIR : string := "bla";
+ QUANT : natural := 32;
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Non Syncronized Parameters
+ rf_brightness : in std_logic_vector( 32-1 downto 0); -- input
+ -- Funtion Input parameters
+ IN_PORT_0 : in std_logic_vector(63 downto 0); -- Param. "a"
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+ -- Funtion Output parameters
+ OUT_PORT_0 : out std_logic_vector(63 downto 0); -- Param. "b"
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end param_stream2rtl_EXECUTION_UNIT_hwn_nd_3 ;
+
+-- Laura implementation
+architecture Laura of param_stream2rtl_EXECUTION_UNIT_hwn_nd_3 is
+
+ component transformer is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Non Syncronized Parameters
+ rf_brightness : in std_logic_vector( 32-1 downto 0); -- input
+ -- Inputs
+ ip_a : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(63 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when IP_RESET=1 else not RST;
+
+ FUNC : transformer
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Non Syncronized Parameters
+ rf_brightness => rf_brightness,
+ -- Inputs
+ ip_a => IN_PORT_0,
+ -- Iterators
+ it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+ EXIST => EXIST,
+ READF => READ,
+ -- Outputs
+ op_b => OUT_PORT_0,
+ FULL => FULL,
+ WRITEF=> WRITE,
+ --
+ STOP_RD => STOP_RD,
+ STOP_WR => STOP_WR,
+ ERROR => ERROR
+ );
+
+end Laura;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/hdllib.cfg b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..503912026ad8b86e692ad029a881f25220158735
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_param_stream2rtl_hwn_nd_4_1
+hdl_library_clause_name = compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib
+hdl_lib_uses_synth = compaandesign_com_param_stream2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/param_stream2rtl_hwn_nd_4_execution_unit.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_rd.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_wr.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_4.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..75fef670467c8b99f4c339e44f8a860332f11776
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4.vhd
@@ -0,0 +1,462 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity param_stream2rtl_hwn_nd_4 is
+ generic (
+ STIM_DIR : string := "bla";
+ RESET_HIGH : natural := 1;
+ PAR_WIDTH : natural := 16;
+ QUANT : natural := 32;
+ WRAP : boolean := true
+ );
+ port (
+
+ -- Dataflow input interfaces
+ -- ED_2 : in_0
+ ND_4IP_2_Rd : out std_logic;
+ ND_4IP_2_Din : in std_logic_vector(63 downto 0);
+ ND_4IP_2_Exist : in std_logic;
+ ND_4IP_2_CLK : out std_logic;
+ ND_4IP_2_CTRL : in std_logic;
+
+ -- Dataflow Control Input interfaces
+ -- Dataflow output interfaces
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(63 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic
+ );
+end param_stream2rtl_hwn_nd_4;
+
+architecture RTL of param_stream2rtl_hwn_nd_4 is
+ --
+ -- ====================================
+ -- = Constants declaration =
+ -- ====================================
+ -- Setting the parameters of the HW Node
+ constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
+ constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
+ constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
+ constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+ constant c_COUNTERS : natural := 1; -- number of iterators
+ -- ===========================================
+ -- = Iterators run from Inner to Outer loop =
+ -- ===========================================
+ constant c_CNTR_QUANT : natural := 5;
+ constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
+ constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
+ constant c_STAGES : natural := 1; -- number of pipeline stages or delay
+ constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
+ constant c_WRAP : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+ constant c_EXT_PAR : natural := 0; -- number of external parameters
+ constant c_INT_PAR : natural := 0; -- number of internal parameters
+ constant c_N_PAR : natural := 0; -- no parameters are used
+ constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+ constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+ (0,0,0,0), (0,0,0,0) -- two dummy elements
+ );
+ --
+ -- ====================================
+ -- = Components declaration =
+ -- ====================================
+ component param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_4 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+ end component;
+
+ component READ_MUX is
+ generic (
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+ CLK : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_4 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+ end component;
+
+ component WRITE_DEMUX is
+ generic (
+ N_PORTS : natural := 1
+ );
+ port(
+ WRITES : out std_logic_vector(N_PORTS-1 downto 0);
+ WRITE : in std_logic;
+
+ FULLS : in std_logic_vector(N_PORTS-1 downto 0);
+ FULL : out std_logic;
+
+ WRITE_EN : in std_logic;
+ WRITE_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+
+ component param_stream2rtl_EXECUTION_UNIT_hwn_nd_4 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ QUANT : natural := 32;
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+ -- Func. Input parameters
+ IN_PORT_0 : in std_logic_vector(63 downto 0); -- tmp1
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Func. Output parameters
+ OUT_PORT_0 : out std_logic_vector(63 downto 0); -- tmp0
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ component INTERNAL_PARAMETERS is
+ generic (
+ PAR_BITWIDTH : natural:=1;
+ PAR_VECTOR : t_par_vector;
+ N_PAR : natural:=0;
+ START_IN_RUN : boolean := FALSE
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ HALT_RD : out std_logic;
+ HALT_WR : out std_logic;
+ SOF_RD : in std_logic;
+ SOF_WR : in std_logic;
+ LOAD_PARAM : out std_logic;
+
+ par_one_in_Rd : out std_logic;
+ par_one_in_Din : in std_logic_vector(32-1 downto 0);
+ par_one_in_Exist : in std_logic;
+ par_one_in_CLK : out std_logic;
+ par_one_in_CTRL : in std_logic;
+
+ PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+ PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+ );
+ end component;
+
+ --
+ -- ====================================
+ -- = Signals declaration =
+ -- ====================================
+ --
+ -- HW Node Input Ports
+ signal sl_IN_PORTS_0 : std_logic_vector(1*64-1 downto 0); -- tmp1
+ signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ --
+ -- Func. Input parameters
+ signal sl_in_port_0 : std_logic_vector(63 downto 0); -- tmp1
+ signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ --
+ signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+ --
+ -- HW Node Output Ports
+ signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ --
+ -- Func. Output parameters
+ signal sl_out_port_0 : std_logic_vector(63 downto 0); -- tmp0
+ signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ --
+ --
+ signal sl_halt : std_logic;
+ signal sl_halted : std_logic;
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
+ signal sl_param_halt_wr : std_logic;
+ signal sl_param_halt_rd : std_logic;
+ signal sl_done_wr : std_logic;
+ signal sl_done_rd : std_logic;
+ signal sl_stop_wr : std_logic;
+ signal sl_stop_rd : std_logic;
+ signal sl_fire_wr : std_logic;
+ signal sl_fire_rd : std_logic;
+ signal sl_sof_wr : std_logic;
+ signal sl_sof_rd : std_logic;
+ signal sl_error : std_logic;
+ signal sl_load_param : std_logic;
+
+ --
+ -- Parameter related signals
+ signal sl_param_fifo_full : std_logic;
+ signal sl_sync_num : std_logic_vector(9 downto 0);
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when RESET_HIGH=1 else not RST;
+ ND_4IP_2_CLK <= CLK;
+ data_out_CLK <= CLK;
+
+ --
+ -- ==========================================================
+ -- = HWN Input related modules =
+ -- ==========================================================
+ -- Func. Input param. "tmp1"
+ RD_MUX_0 : READ_MUX
+ generic map (
+ N_PORTS => 1,
+ PORT_WIDTH => 64
+ )
+ port map (
+ IN_PORTS => sl_IN_PORTS_0,
+ EXISTS => sl_EXISTS(0 downto 0),
+ READS => sl_READS(0 downto 0),
+ SOFS => sl_CTRLS(0 downto 0),
+
+ OUT_PORT => sl_in_port_0,
+ EXIST => sl_exist(0),
+ READ => sl_read(0),
+ SOF => sl_sof_rd,
+ CLK => CLK,
+
+ READ_EN => sl_read_en(0),
+ READ_ST => sl_read_st(0),
+ CONTROL => sl_control_rd(0 downto 0),
+ OBTAIN => sl_obtain_rd(0 downto 0),
+ RELEASE => sl_release_rd(0 downto 0)
+ );
+
+ ND_4IP_2_Rd <= sl_READS(0);
+
+ sl_IN_PORTS_0 <= ND_4IP_2_Din;
+
+ sl_EXISTS(0) <= ND_4IP_2_Exist ;
+ sl_CTRLS(0) <= ND_4IP_2_CTRL ;
+
+ EVAL_RD : param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_4
+ generic map (
+ N_IN_PORTS => c_IN_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ REG_CNTRS => sl_REG_CNTRS_RD,
+ READ_EN => sl_read_en,
+ READ_ST => sl_read_st,
+ HALT => sl_halt_rd,
+ FIRE => sl_fire_rd,
+ DONE => sl_done_rd,
+ STOP => sl_stop_rd,
+ CONTROL => sl_control_rd,
+ OBTAIN => sl_obtain_rd,
+ RELEASE => sl_release_rd
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Output related modules =
+ -- ==========================================================
+ --
+ -- Func. Output param. "tmp0"
+ DEMUX_0 : WRITE_DEMUX
+ generic map (
+ N_PORTS => 1
+ )
+ port map (
+ WRITES => sl_WRITES(0 downto 0),
+ FULLS => sl_FULLS(0 downto 0),
+ CONTROL => sl_lortnoc_wr(0 downto 0),
+ WRITE => sl_write(0),
+ FULL => sl_full(0),
+ WRITE_EN => sl_write_en(0),
+ WRITE_ST => sl_write_st(0)
+ );
+ --
+ data_out_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
+ data_out_CTRL <= sl_sof_wr ;
+ data_out_Wr <= sl_WRITES(0);
+ sl_FULLS(0) <= data_out_Full;
+ sl_lortnoc_wr(0) <= sl_control_wr(0);
+ --
+ --
+ EVAL_WR : param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_4
+ generic map (
+ N_OUT_PORTS => c_OUT_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ WRITE_EN => sl_write_en,
+ WRITE_ST => sl_write_st,
+ HALT => sl_halt_wr,
+ FIRE => sl_fire_wr,
+ DONE => sl_done_wr,
+ STOP => sl_stop_wr,
+ CONTROL => sl_control_wr
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Execution Unit =
+ -- ==========================================================
+ EX : param_stream2rtl_EXECUTION_UNIT_hwn_nd_4
+ generic map (
+ N_INPORTS => c_IN_FUNC_VAR,
+ N_OUTPORTS => c_OUT_FUNC_VAR,
+ IP_RESET => c_IP_RESET,
+ QUANT => QUANT,
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => c_COUNTERS,
+ CNTR_QUANT => c_CNTR_QUANT,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Iterators
+ REG_CNTRS_RD => sl_REG_CNTRS_RD,
+ -- Func. Input parameters
+ IN_PORT_0 => sl_in_port_0,
+ READ => sl_read,
+ EXIST => sl_exist,
+ -- Func. Output parameters
+ OUT_PORT_0 => sl_out_port_0,
+ WRITE => sl_write,
+ FULL => sl_full,
+ --
+ STOP_WR => sl_stop_wr,
+ STOP_RD => sl_stop_rd,
+ ERROR => sl_error
+ );
+
+ -- ==========================================================
+ -- = PARAMETERIZATION =
+ -- ==========================================================
+ -- no parameters
+ sl_halt_rd <= '0';
+ sl_halt_wr <= '0';
+-- sl_halted <= sl_sof_rd;
+ STOP <= sl_done_wr;
+ ERROR <= sl_error;
+ BLOCK_RD <= not ( ( sl_READS(0) ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_rd.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..84a173a7ed87cc1b9f08f7ddd629b13a4152503e
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_rd.vhd
@@ -0,0 +1,283 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_4 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(0 downto 0);
+ READ_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+end param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_4;
+
+architecture RTL of param_stream2rtl_EVAL_LOGIC_RD_hwn_nd_4 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOAD : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_x, sl_high_x : integer;
+ signal sl_loop_x, sl_loop_x_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_count : std_logic;
+
+ -- alias signals
+ alias update_x : std_logic is sl_cntr_en(0);
+ alias load_x : std_logic is sl_load(0);
+
+ -- Trigger signals
+ signal sl_trigger_x : std_logic;
+
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- Multirate related signals
+ signal sl_bla_en : std_logic_vector(0 downto 0);
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function input parameter "in_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+
+
+ signal sl_obtain0 : std_logic;
+ signal sl_release0 : std_logic;
+
+ -- define control variables
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ -- =============================================
+ -- = Parameter Functions
+ -- =============================================
+ sl_cnt_rst <= '0';
+ sl_halt <= HALT;
+
+ -- END of Parameter definitions
+ sl_loop_x <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_x_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_x <= 0;
+ sl_high_x <= 9;
+
+
+ load_x <= '0';
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
+ -- Special definitions
+
+ -- Entity and control variables
+ -- Release matrix expressions
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Read Port ND_4IP_2 Argument in_1 : ED_2 : 0 of type IOMM
+ sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
+ sl_release0 <= ('1');
+
+ sl_CONTROL(0) <= sl_fire and ('1');
+ OBTAIN(0) <= sl_obtain0;
+ RELEASE(0) <= sl_release0;
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function input parameter "in_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOAD => '0',
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ -- READ_EN indicates if READ_MUX can read data
+ sl_bla_en <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ READ_EN <= (others=>'0') when (HALT='1') else sl_bla_en;
+ sl_mr_en <= READ_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+ CNTR_RD : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOAD => sl_load(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true) then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ REG_CNTRS <= sl_reg_cntrs;
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ --
+ sl_count <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+ sl_cntr_en(0) <= sl_count; -- makes the EVAL_LOGIC count
+ --
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
+ --
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_wr.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0a97d375759a86386471d19abfaaa3a85d9cd7d0
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_wr.vhd
@@ -0,0 +1,276 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_4 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ PAR_BITWIDTH : natural :=1;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ WRITE_EN : out std_logic_vector(0 downto 0);
+ WRITE_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+end param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_4;
+
+architecture RTL of param_stream2rtl_EVAL_LOGIC_WR_hwn_nd_4 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOAD : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ -- Multirate related signals
+ signal sl_bla_en : std_logic_vector(0 downto 0);
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function output parameter "data_out[x]", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_x, sl_high_x : integer;
+ signal sl_loop_x, sl_loop_x_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_count : std_logic;
+ --
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- alias signals
+ alias update_x : std_logic is sl_cntr_en(0);
+ --
+ alias load_x : std_logic is sl_load(0);
+ -- Trigger signals
+ signal sl_trigger_x : std_logic;
+
+ signal e0, e1 : boolean;
+
+ -- define control variables
+ -- MOD related signals
+
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= HALT;
+ -- END of Parameter definitions
+
+ sl_loop_x <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_x_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_x <= 0;
+ sl_high_x <= 9;
+
+
+ load_x <= '0';
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
+
+ -- Special definitions
+
+ -- Entity and control variables
+ e0 <= sl_loop_x_rg>=0;
+ e1 <= -sl_loop_x_rg + 9>=0;
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Write Port out_1 : EXTERNAL
+ sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function output parameter "data_out[x]", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOAD => '0',
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ -- WRITE_EN indicates if date can be written to WRITE_MUX
+ sl_bla_en <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ WRITE_EN <= (others=>'0') when (HALT='1') else sl_bla_en;
+ --
+ sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+ CNTR_WR : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOAD => sl_load(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true) then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ --
+ sl_count <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+ sl_cntr_en(0) <= sl_count; -- makes the EVAL_LOGIC count
+ --
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
+ --
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_execution_unit.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0d7a0b926659c795207e53c426dc4830e796a6d0
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_execution_unit.vhd
@@ -0,0 +1,109 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_param_stream2rtl_functions_1_lib;
+use compaandesign_com_param_stream2rtl_functions_1_lib.all;
+
+entity param_stream2rtl_EXECUTION_UNIT_hwn_nd_4 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ STIM_DIR : string := "bla";
+ QUANT : natural := 32;
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Funtion Input parameters
+ IN_PORT_0 : in std_logic_vector(63 downto 0); -- Param. "tmp1"
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+ -- Funtion Output parameters
+ OUT_PORT_0 : out std_logic_vector(63 downto 0); -- Param. "tmp0"
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end param_stream2rtl_EXECUTION_UNIT_hwn_nd_4 ;
+
+-- Laura implementation
+architecture Laura of param_stream2rtl_EXECUTION_UNIT_hwn_nd_4 is
+
+ component compaan_outlinedproc1 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(63 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(63 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when IP_RESET=1 else not RST;
+
+ FUNC : compaan_outlinedproc1
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Inputs
+ ip_tmp1 => IN_PORT_0,
+ -- Iterators
+ it_x => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+ EXIST => EXIST,
+ READF => READ,
+ -- Outputs
+ op_tmp0 => OUT_PORT_0,
+ FULL => FULL,
+ WRITEF=> WRITE,
+ --
+ STOP_RD => STOP_RD,
+ STOP_WR => STOP_WR,
+ ERROR => ERROR
+ );
+
+end Laura;
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/register_rf/hdllib.cfg b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/register_rf/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5b50761c6a7ec08b809ee3c8a8472942f7f81b5f
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/register_rf/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_param_stream2rtl_register_rf_1
+hdl_library_clause_name = compaandesign_com_param_stream2rtl_register_rf_1_lib
+hdl_lib_uses_synth =
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/register_rf.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/register_rf/src/vhdl/register_rf.vhd b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/register_rf/src/vhdl/register_rf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d1cee7509b93a4797774302154de26a94a5fc7fd
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/compaandesign_com/param_stream2rtl/register_rf/src/vhdl/register_rf.vhd
@@ -0,0 +1,80 @@
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity register_rf is
+ generic (
+ C_brightness_rf_address : std_logic_vector(18 downto 0) := B"0000000000000000000" -- 0
+ );
+
+port (
+ rst : in std_logic;
+ clk : in std_logic;
+ pci_clk : in std_logic;
+ --
+
+ -- Interface to PCIe
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ --
+ -- Interface to reg brightness
+ brightness_rf_read_data : in std_logic_vector(32-1 downto 0);
+ brightness_rf_read_en : out std_logic;
+ brightness_rf_write_en : out std_logic;
+ brightness_rf_write_data : out std_logic_vector(32-1 downto 0)
+
+);
+end register_rf;
+
+architecture RTL of register_rf is
+
+ signal sl_read_data : std_logic_vector(32-1 downto 0) := (others=>'0');
+
+begin
+process (pci_clk,rst)
+ begin
+ if (rising_edge(pci_clk)) then
+ if (rst = '1') then
+ brightness_rf_write_en <= '0';
+ brightness_rf_read_en <= '0';
+ brightness_rf_write_data <= (others => '0');
+ else
+
+ if ( (address(18 downto 2) = C_brightness_rf_address(18 downto 2)) and write_en = '1') then
+ brightness_rf_write_data <= write_data(32-1 downto 0);
+ brightness_rf_write_en <= '1';
+ else
+ brightness_rf_write_en <= '0';
+ end if;
+
+ if( (address(18 downto 2) = C_brightness_rf_address(18 downto 2)) and read_en= '1') then
+ brightness_rf_read_en <= '1';
+ else
+ brightness_rf_read_en <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+process (pci_clk,rst)
+begin
+ if (rising_edge(pci_clk)) then
+ if (rst = '1') then
+ else
+ case address(18 downto 2) is
+ when (C_brightness_rf_address(18 downto 2) ) =>
+ sl_read_data(32-1 downto 0) <= brightness_rf_read_data;
+ when others =>
+ sl_read_data <= (others => '0');
+ end case;
+ end if;
+ end if;
+end process;
+
+read_data <=sl_read_data;
+
+end RTL;
diff --git a/applications/compaan/libraries/param_stream/hdllib.cfg b/applications/compaan/libraries/param_stream/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0d2a0e3f6cd82a9e921c2667fcd0fb9a6d6cadd1
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = param_stream
+hdl_library_clause_name = param_stream_lib
+
+hdl_lib_uses_synth = compaandesign_com_param_stream2rtl_hwn_nd_3_1 compaandesign_com_altera_fifo_1 compaandesign_com_param_stream2rtl_register_rf_1 compaandesign_com_param_stream2rtl_hwn_nd_2_1 compaandesign_com_param_stream2rtl_hwn_nd_4_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/param_stream.vhd
+ src/vhdl/param_stream2rtl_ed_1_ip_wrapper.vhd
+ src/vhdl/param_stream2rtl_ed_2_ip_wrapper.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_2_ip_wrapper.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_3_ip_wrapper.vhd
+ src/vhdl/param_stream2rtl_hwn_nd_4_ip_wrapper.vhd
+ src/vhdl/param_stream2rtl_register_rf_ip_wrapper.vhd
+
+test_bench_files =
+ src/vhdl/system_ext_TB.vhd
diff --git a/applications/compaan/libraries/param_stream/modelsim_hier_timeline.tcl b/applications/compaan/libraries/param_stream/modelsim_hier_timeline.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c178c341dbc0f4b18760a47bf23363af20e4cab1
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/modelsim_hier_timeline.tcl
@@ -0,0 +1,5 @@
+divider add TIMELINE -color darkgreen
+wave add SUT/param_stream2rtl_hwn_nd_2_ip/param_stream2rtl_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:param_stream2rtl:hwn_nd_2:1
+wave add SUT/param_stream2rtl_hwn_nd_3_ip/param_stream2rtl_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:param_stream2rtl:hwn_nd_3:1
+wave add SUT/param_stream2rtl_hwn_nd_4_ip/param_stream2rtl_hwn_nd_4_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:param_stream2rtl:hwn_nd_4:1
+divider add TIMELINE -color darkgreen
diff --git a/applications/compaan/libraries/param_stream/modelsim_system.do b/applications/compaan/libraries/param_stream/modelsim_system.do
new file mode 100644
index 0000000000000000000000000000000000000000..46b2d3710da99daf99f3f07698264e9205306537
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/modelsim_system.do
@@ -0,0 +1,328 @@
+transcript on
+
+onerror {quit -f}
+onbreak {quit -f}
+config wave -signalnamewidth 1
+
+#source vhdl-library-setup.tcl
+
+set path_to_quartus /opt/Altera/15.0/quartus
+vlib lpm
+vmap lpm lpm
+vcom -work lpm -2002 -explicit $path_to_quartus/eda/sim_lib/220pack.vhd
+vcom -work lpm -2002 -explicit $path_to_quartus/eda/sim_lib/220model.vhd
+
+vlib sgate
+vmap sgate sgate
+vcom -work sgate -2002 -explicit $path_to_quartus/eda/sim_lib/sgate_pack.vhd
+vcom -work sgate -2002 -explicit $path_to_quartus/eda/sim_lib/sgate.vhd
+
+vlib altera_mf
+vmap altera_mf altera_mf
+vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf_components.vhd
+vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf.vhd
+
+vlib altera_lnsim
+vmap altera_lnsim altera_lnsim
+vcom -work altera_lnsim -2002 -explicit $path_to_quartus/eda/sim_lib/altera_lnsim_components.vhd
+vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf.vhd
+
+vlib altera
+vmap altera altera
+vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_primitives_components.vhd
+vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_primitives.vhd
+
+vlib stratixiv
+vmap stratixiv stratixiv
+vcom -work stratixiv -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_atoms.vhd
+vcom -work stratixiv -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_components.vhd
+
+vlib stratixiv_hssi
+vmap stratixiv_hssi stratixiv_hssi
+vcom -work stratixiv_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_hssi_components.vhd
+vcom -work stratixiv_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd
+
+vlib stratixiv_pcie_hip
+vmap stratixiv_pcie_hip stratixiv_pcie_hip
+vcom -work stratixiv_pcie_hip -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_pcie_hip_components.vhd
+vcom -work stratixiv_pcie_hip -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.vhd
+
+if {[file exists work]} {
+ vdel -lib work -all
+}
+vlib work
+vmap work work
+
+if {[file exists technology_lib]} {
+ vdel -lib technology_lib -all
+}
+vlib technology_lib
+vmap work technology_lib
+
+if {[file exists common_lib]} {
+ vdel -lib common_lib -all
+}
+vlib common_lib
+vmap work common_lib
+
+if {[file exists tech_memory_lib]} {
+ vdel -lib tech_memory_lib -all
+}
+vlib tech_memory_lib
+vmap work tech_memory_lib
+
+if {[file exists ip_stratixiv_fifo_lib]} {
+ vdel -lib ip_stratixiv_fifo_lib -all
+}
+vlib ip_stratixiv_fifo_lib
+vmap work ip_stratixiv_fifo_lib
+
+if {[file exists ip_stratixiv_ram_lib]} {
+ vdel -lib ip_stratixiv_ram_lib -all
+}
+vlib ip_stratixiv_ram_lib
+vmap work ip_stratixiv_ram_lib
+
+if {[file exists ip_arria10_ram_lib]} {
+ vdel -lib ip_arria10_ram_lib -all
+}
+vlib ip_arria10_ram_lib
+vmap work ip_arria10_ram_lib
+
+if {[file exists ip_arria10_fifo_lib]} {
+ vdel -lib ip_arria10_fifo_lib -all
+}
+vlib ip_arria10_fifo_lib
+vmap work ip_arria10_fifo_lib
+
+if {[file exists ip_arria10_e3sge3_fifo_lib]} {
+ vdel -lib ip_arria10_e3sge3_fifo_lib -all
+}
+vlib ip_arria10_e3sge3_fifo_lib
+vmap work ip_arria10_e3sge3_fifo_lib
+
+if {[file exists ip_arria10_e3sge3_ram_lib]} {
+ vdel -lib ip_arria10_e3sge3_ram_lib -all
+}
+vlib ip_arria10_e3sge3_ram_lib
+vmap work ip_arria10_e3sge3_ram_lib
+
+if {[file exists tech_fifo_lib]} {
+ vdel -lib tech_fifo_lib -all
+}
+vlib tech_fifo_lib
+vmap work tech_fifo_lib
+
+if {[file exists dp_lib]} {
+ vdel -lib dp_lib -all
+}
+vlib dp_lib
+vmap work dp_lib
+
+
+set SVNROOT /home/kienhuis/svnroot/UniBoard_FP7
+set RadioHDL ${SVNROOT}/RadioHDL/trunk
+set UniBoard ${SVNROOT}/UniBoard/trunk
+
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_pkg.vhd
+vcom -93 -work work ${UniBoard}/Firmware/modules/common/src/vhdl/common_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/technology/technology_pkg.vhd
+vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
+vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
+
+vcom -93 -work ip_arria10_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
+
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc.vhd
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_sc.vhd
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc_mixed_widths.vhd
+
+vcom -93 -work ip_arria10_e3sge3_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
+vcom -93 -work ip_arria10_e3sge3_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
+vcom -93 -work ip_arria10_e3sge3_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
+
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_sc.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_areset.vhd
+
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd
+vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd
+
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_pipeline.vhd
+
+vcom -93 -work ip_stratixiv_ram_lib ${RadioHDL}/libraries/technology/ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd
+vcom -93 -work ip_stratixiv_ram_lib ${RadioHDL}/libraries/technology/ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd
+
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_true_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_component_pkg.vhd
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+
+# -- Compaan Specific
+if {[file exists compaandesign_com_common_common_1_lib]} {
+ vdel -lib compaandesign_com_common_common_1_lib -all
+}
+vlib compaandesign_com_common_common_1_lib
+vmap work compaandesign_com_common_common_1_lib
+
+vcom -93 -work compaandesign_com_common_common_1_lib {compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd}
+
+if {[file exists compaandesign_com_common_const_connector_1_lib]} {
+ vdel -lib compaandesign_com_common_const_connector_1_lib -all
+}
+vlib compaandesign_com_common_const_connector_1_lib
+vmap work compaandesign_com_common_const_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_const_connector_1_lib {compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd}
+
+if {[file exists compaandesign_com_altera_fifo_1_lib]} {
+ vdel -lib compaandesign_com_altera_fifo_1_lib -all
+}
+vlib compaandesign_com_altera_fifo_1_lib
+vmap work compaandesign_com_altera_fifo_1_lib
+
+vcom -93 -work compaandesign_com_altera_fifo_1_lib {compaandesign_com/altera/fifo/src/vhdl/fsl_v20.vhd}
+
+if {[file exists compaandesign_com_altera_memory_1_lib]} {
+ vdel -lib compaandesign_com_altera_memory_1_lib -all
+}
+vlib compaandesign_com_altera_memory_1_lib
+vmap work compaandesign_com_altera_memory_1_lib
+
+vcom -93 -work compaandesign_com_altera_memory_1_lib {compaandesign_com/altera/memory/src/vhdl/sync_bram.vhd}
+
+if {[file exists compaandesign_com_common_extern_connector_1_lib]} {
+ vdel -lib compaandesign_com_common_extern_connector_1_lib -all
+}
+vlib compaandesign_com_common_extern_connector_1_lib
+vmap work compaandesign_com_common_extern_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_extern_connector_1_lib {compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd}
+
+if {[file exists compaandesign_com_common_hwnode_1_lib]} {
+ vdel -lib compaandesign_com_common_hwnode_1_lib -all
+}
+vlib compaandesign_com_common_hwnode_1_lib
+vmap work compaandesign_com_common_hwnode_1_lib
+
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/controller.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/counter.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/external_parameters.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/internal_parameters.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd}
+
+if {[file exists compaandesign_com_common_wire_connector_1_lib]} {
+ vdel -lib compaandesign_com_common_wire_connector_1_lib -all
+}
+vlib compaandesign_com_common_wire_connector_1_lib
+vmap work compaandesign_com_common_wire_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_wire_connector_1_lib {compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd}
+
+if {[file exists compaandesign_com_param_stream2rtl_functions_1_lib]} {
+ vdel -lib compaandesign_com_param_stream2rtl_functions_1_lib -all
+}
+vlib compaandesign_com_param_stream2rtl_functions_1_lib
+vmap work compaandesign_com_param_stream2rtl_functions_1_lib
+
+vcom -93 -work compaandesign_com_param_stream2rtl_functions_1_lib {compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_functions_1_lib {compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_functions_1_lib {compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_functions_1_lib {compaandesign_com/param_stream2rtl/functions/src/vhdl/transformer_pipeline.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_functions_1_lib {compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_functions_1_lib {compaandesign_com/param_stream2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd}
+
+if {[file exists compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib]} {
+ vdel -lib compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib -all
+}
+vlib compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib
+vmap work compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib
+
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_execution_unit.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_2/src/vhdl/param_stream2rtl_hwn_nd_2.vhd}
+
+if {[file exists compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib]} {
+ vdel -lib compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib -all
+}
+vlib compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib
+vmap work compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib
+
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_execution_unit.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_3/src/vhdl/param_stream2rtl_hwn_nd_3.vhd}
+
+if {[file exists compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib]} {
+ vdel -lib compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib -all
+}
+vlib compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib
+vmap work compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib
+
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_execution_unit.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib {compaandesign_com/param_stream2rtl/hwn_nd_4/src/vhdl/param_stream2rtl_hwn_nd_4.vhd}
+
+if {[file exists compaandesign_com_param_stream2rtl_register_rf_1_lib]} {
+ vdel -lib compaandesign_com_param_stream2rtl_register_rf_1_lib -all
+}
+vlib compaandesign_com_param_stream2rtl_register_rf_1_lib
+vmap work compaandesign_com_param_stream2rtl_register_rf_1_lib
+
+vcom -93 -work compaandesign_com_param_stream2rtl_register_rf_1_lib {compaandesign_com/param_stream2rtl/register_rf/src/vhdl/register_rf.vhd}
+
+
+
+
+vcom -93 -work work src/vhdl/param_stream.vhd
+vcom -93 -work work src/vhdl/param_stream2rtl_ed_1_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/param_stream2rtl_ed_2_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/param_stream2rtl_hwn_nd_2_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/param_stream2rtl_hwn_nd_3_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/param_stream2rtl_hwn_nd_4_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/param_stream2rtl_register_rf_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/system_ext_TB.vhd
+
+vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L ip_stratixiv_ram_lib -L stratixiv_pcie_hip -L stratixiv -L common_lib -L tech_memory_lib -L ip_stratixiv_fifo_lib -L tech_fifo_lib -L dp_lib -L technology_lib -L work -L compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib -L compaandesign_com_common_wire_connector_1_lib -L compaandesign_com_param_stream2rtl_functions_1_lib -L compaandesign_com_altera_fifo_1_lib -L compaandesign_com_common_const_connector_1_lib -L compaandesign_com_param_stream2rtl_register_rf_1_lib -L compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib -L compaandesign_com_altera_memory_1_lib -L compaandesign_com_common_hwnode_1_lib -L compaandesign_com_common_common_1_lib -L compaandesign_com_common_extern_connector_1_lib -L compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib -voptargs="+acc" system_ext_TB
+#add wave *
+#view structure
+#view signals
+#source isim_wave.tcl
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+run -all
+
+quit -f
+
diff --git a/applications/compaan/libraries/param_stream/run_quartus.tcl b/applications/compaan/libraries/param_stream/run_quartus.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..11201204309453b1443f01be8c753604ef2b2f9b
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/run_quartus.tcl
@@ -0,0 +1,88 @@
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+ if {[string compare $quartus(project) "param_stream"]} {
+ puts "Project param_stream is not open"
+ set make_assignments 0
+}
+} else {
+ # Only open if not already open
+ if {[project_exists param_stream]} {
+ project_open -revision param_stream param_stream
+ } else {
+ project_new -revision param_stream param_stream
+ }
+}
+set need_to_close_project 1
+
+# Make assignments
+if {$make_assignments} {
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:26 JANUARY 22, 2015"
+ set_global_assignment -name LAST_QUARTUS_VERSION 12.0
+ set_global_assignment -name FAMILY "Stratix V"
+ set_global_assignment -name TOP_LEVEL_ENTITY param_stream
+ set_global_assignment -name DEVICE auto
+ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/write_demux.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mux.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mmux.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/parameters.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mul.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mod.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/counter.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/controller.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/altera/1/fsl_v20.vhd -library compaandesign_com_common_fifo_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/common/1/hw_node_pkg.vhd -library compaandesign_com_common_common_1
+
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/param_stream2rtl/hwn_nd_2/1/sourceCode -library compaandesign_com_param_stream2rtl_hwn_nd_2_1
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/param_stream2rtl/hwn_nd_3/1/sourceCode -library compaandesign_com_param_stream2rtl_hwn_nd_3_1
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/param_stream2rtl/hwn_nd_4/1/sourceCode -library compaandesign_com_param_stream2rtl_hwn_nd_4_1
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/param_stream2rtl/register_rf/1/sourceCode -library compaandesign_com_param_stream2rtl_register_rf_1
+
+
+# add functions of Laura node into a library
+
+ set strlist [glob compaandesign_com/param_stream2rtl/functions/1/*.vhd]
+ foreach strfile $strlist {
+ set file_name $strfile
+ set_global_assignment -name VHDL_FILE $file_name -library compaandesign_com_param_stream2rtl_functions_1
+ }
+
+
+# add wrapper to library work
+ set strlist [glob *.vhd]
+ foreach strfile $strlist {
+ set file_name $strfile
+ set_global_assignment -name VHDL_FILE $file_name -library work
+ }
+
+# testbench information
+set_global_assignment -name VHDL_FILE system_ext_TB.vhd -library work
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH param_stream -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME param_stream -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME param_stream -section_id param_stream
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME param_stream -section_id param_stream
+set_global_assignment -name EDA_TEST_BENCH_FILE system_ext_TB.vhd -section_id param_stream -library work
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+# Commit assignments
+export_assignments
+
+# Close project
+if {$need_to_close_project} {
+ project_close
+}
+}
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/param_stream.vhd b/applications/compaan/libraries/param_stream/src/vhdl/param_stream.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..807b8f2ee7f5e2893f3f1b089b5bd70afffd6090
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/param_stream.vhd
@@ -0,0 +1,427 @@
+-------------------------------------------------------------------------------
+-- TOP LEVEL
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+entity param_stream is
+ port (
+
+ data_in_Data : in std_logic_vector(63 downto 0 );
+ data_in_Control : in std_logic;
+ data_in_Read : out std_logic;
+ data_in_Exists : in std_logic;
+
+ data_out_Data : out std_logic_vector(63 downto 0 );
+ data_out_Control : out std_logic;
+ data_out_Write : out std_logic;
+ data_out_Full : in std_logic;
+
+ TEST_STOP : out std_logic_vector(3 downto 0 );
+ TEST_ERROR : out std_logic_vector(3 downto 0 );
+ TEST_FIFO_FULL : out std_logic_vector(1 downto 0 );
+ TEST_BLOCK_RD : out std_logic_vector(3 downto 0 );
+ address : in std_logic_vector(18 downto 0 );
+ read_data : out std_logic_vector(31 downto 0 );
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0 );
+ pci_clk : in std_logic;
+
+ KPN_CLK : in std_logic;
+ KPN_RST : in std_logic
+ );
+end param_stream;
+
+architecture STRUCTURE of param_stream is
+
+ component param_stream2rtl_hwn_nd_2_ip_wrapper is
+ port (
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(63 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+ end component;
+
+ component param_stream2rtl_hwn_nd_3_ip_wrapper is
+ port (
+ rf_brightness : in std_logic_vector(31 downto 0);
+ ND_3IP_1_Rd : out std_logic;
+ ND_3IP_1_Din : in std_logic_vector(63 downto 0);
+ ND_3IP_1_Exist : in std_logic;
+ ND_3IP_1_CLK : out std_logic;
+ ND_3IP_1_CTRL : in std_logic;
+
+ ND_3OP_1_Wr : out std_logic;
+ ND_3OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_3OP_1_Full : in std_logic;
+ ND_3OP_1_CLK : out std_logic;
+ ND_3OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+ end component;
+
+ component param_stream2rtl_hwn_nd_4_ip_wrapper is
+ port (
+ ND_4IP_2_Rd : out std_logic;
+ ND_4IP_2_Din : in std_logic_vector(63 downto 0);
+ ND_4IP_2_Exist : in std_logic;
+ ND_4IP_2_CLK : out std_logic;
+ ND_4IP_2_CTRL : in std_logic;
+
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(63 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+ end component;
+
+component param_stream2rtl_register_rf_ip_wrapper is
+ port (
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ brightness_rf_read_data : in std_logic_vector(31 downto 0);
+ brightness_rf_read_en : out std_logic;
+ brightness_rf_write_en : out std_logic;
+ brightness_rf_write_data : out std_logic_vector(31 downto 0);
+ RST : in std_logic;
+ CLK : in std_logic
+
+ );
+end component;
+
+ component param_stream2rtl_ed_1_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 63);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 63);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+ component param_stream2rtl_ed_2_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 63);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 63);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+ -- Internal signals
+
+ signal signal_ed_1_out_FSL_M_Control : std_logic;
+ signal signal_ed_1_out_FSL_M_Data : std_logic_vector(0 to 63);
+ signal signal_ed_1_out_FSL_M_Full : std_logic;
+ signal signal_ed_1_out_FSL_M_Write : std_logic;
+ signal signal_ed_1_in_FSL_S_Control : std_logic;
+ signal signal_ed_1_in_FSL_S_Data : std_logic_vector(0 to 63);
+ signal signal_ed_1_in_FSL_S_Exists : std_logic;
+ signal signal_ed_1_in_FSL_S_Read : std_logic;
+ signal signal_ed_2_out_FSL_M_Control : std_logic;
+ signal signal_ed_2_out_FSL_M_Data : std_logic_vector(0 to 63);
+ signal signal_ed_2_out_FSL_M_Full : std_logic;
+ signal signal_ed_2_out_FSL_M_Write : std_logic;
+ signal signal_ed_2_in_FSL_S_Control : std_logic;
+ signal signal_ed_2_in_FSL_S_Data : std_logic_vector(0 to 63);
+ signal signal_ed_2_in_FSL_S_Exists : std_logic;
+ signal signal_ed_2_in_FSL_S_Read : std_logic;
+ -- Internal signals END
+ -- Internal signals getDesignAdHocConnectionIDs
+
+ -- AD HOC Internal signals
+
+ signal signal_hwn_nd_1_STOP : std_logic;
+ signal signal_hwn_nd_1_ERROR : std_logic;
+ signal signal_hwn_nd_1_BLOCK_RD : std_logic;
+ signal signal_hwn_nd_2_STOP : std_logic;
+ signal signal_hwn_nd_2_ERROR : std_logic;
+ signal signal_hwn_nd_2_BLOCK_RD : std_logic;
+ signal signal_hwn_nd_3_STOP : std_logic;
+ signal signal_hwn_nd_3_ERROR : std_logic;
+ signal signal_hwn_nd_3_BLOCK_RD : std_logic;
+ signal signal_hwn_nd_4_STOP : std_logic;
+ signal signal_hwn_nd_4_ERROR : std_logic;
+ signal signal_hwn_nd_4_BLOCK_RD : std_logic;
+ signal signal_ed_1_FIFO_FULL : std_logic;
+ signal signal_ed_2_FIFO_FULL : std_logic;
+ signal signal_PARAM_DT : std_logic_vector(10 downto 0);
+ signal signal_PARAM_LD : std_logic;
+ signal signal_PARAMETERS : std_logic_vector(0 downto 0);
+ signal signal_PARAMETERS_LD : std_logic;
+ signal signal_address : std_logic_vector(18 downto 0);
+ signal signal_read_data : std_logic_vector(31 downto 0);
+ signal signal_write_data : std_logic_vector(31 downto 0);
+ signal signal_read_en : std_logic;
+ signal signal_write_en : std_logic;
+ signal signal_SHMEM_WRITE_brightness : std_logic_vector(31 downto 0);
+ signal signal_SHMEM_READ_brightness : std_logic_vector(31 downto 0);
+ signal signal_SHMEM_READ_EN_brightness : std_logic;
+ signal signal_SHMEM_WRITE_EN_brightness : std_logic;
+ signal signal_param_ext_pci_clk : std_logic;
+ signal signal_register_rf_pci_clk : std_logic;
+ signal signal_SYNC_NUM : std_logic_vector(9 downto 0);
+ -- Internal signals writeInternalAdHocConnections
+
+ -- Hierarchical signals
+
+ signal I_data_in_Control : std_logic;
+ signal I_data_in_Data : std_logic_vector(63 downto 0);
+ signal I_data_in_Exists : std_logic;
+ signal I_data_in_Read : std_logic;
+ signal I_data_out_Control : std_logic;
+ signal I_data_out_Data : std_logic_vector(63 downto 0);
+ signal I_data_out_Full : std_logic;
+ signal I_data_out_Write : std_logic;
+ -- Internal signals writeHierarchicalConnections
+
+ -- Default signals
+
+ signal net_gnd0 : std_logic;
+ signal net_gnd16 : std_logic_vector(15 downto 0);
+
+ signal sys_clk_s : std_logic;
+ signal sys_rst_s : std_logic;
+
+
+ -- START the actual definition of a Design
+
+begin
+
+ -- Connect Clock
+
+ sys_clk_s <= KPN_CLK;
+ sys_rst_s <= KPN_RST;
+
+
+ -- Connect Hiercical Interconnections
+
+ I_data_in_Data <= data_in_Data;
+ I_data_in_Control <= data_in_Control;
+ data_in_Read <= I_data_in_Read;
+ I_data_in_Exists <= data_in_Exists;
+ data_out_Data <= I_data_out_Data;
+ data_out_Control <= I_data_out_Control;
+ data_out_Write <= I_data_out_Write;
+ I_data_out_Full <= data_out_Full;
+
+ -- AD HOC EXTERNAL CONNECTIONS
+ TEST_STOP(0) <= signal_hwn_nd_1_STOP;
+ signal_hwn_nd_1_STOP <= '1'; -- TIED VALUE
+ TEST_ERROR(0) <= signal_hwn_nd_1_ERROR;
+ signal_hwn_nd_1_ERROR <= '0'; -- TIED VALUE
+ TEST_BLOCK_RD(0) <= signal_hwn_nd_1_BLOCK_RD;
+ TEST_STOP(1) <= signal_hwn_nd_2_STOP;
+ TEST_ERROR(1) <= signal_hwn_nd_2_ERROR;
+ TEST_BLOCK_RD(1) <= signal_hwn_nd_2_BLOCK_RD;
+ TEST_STOP(2) <= signal_hwn_nd_3_STOP;
+ TEST_ERROR(2) <= signal_hwn_nd_3_ERROR;
+ TEST_BLOCK_RD(2) <= signal_hwn_nd_3_BLOCK_RD;
+ TEST_STOP(3) <= signal_hwn_nd_4_STOP;
+ TEST_ERROR(3) <= signal_hwn_nd_4_ERROR;
+ TEST_BLOCK_RD(3) <= signal_hwn_nd_4_BLOCK_RD;
+ TEST_FIFO_FULL(0) <= signal_ed_1_FIFO_FULL;
+ TEST_FIFO_FULL(1) <= signal_ed_2_FIFO_FULL;
+ signal_address <= address( 18 downto 0);
+ read_data( 31 downto 0) <= signal_read_data;
+ signal_write_data <= write_data( 31 downto 0);
+ signal_read_en <= read_en;
+ signal_write_en <= write_en;
+ signal_param_ext_pci_clk <= pci_clk;
+ signal_register_rf_pci_clk <= pci_clk;
+
+-- Give default signals, default values
+
+ net_gnd0 <= '0';
+ net_gnd16(15 downto 0) <= B"0000000000000000";
+
+-- Instanciate the wrappers (HWN and Edges)
+
+
+ param_stream2rtl_hwn_nd_2_ip : param_stream2rtl_hwn_nd_2_ip_wrapper
+ port map (
+ data_in_Rd => I_data_in_Read,
+ data_in_Din => I_data_in_Data(63 downto 0),
+ data_in_Exist => I_data_in_Exists,
+ data_in_CLK => open,
+ data_in_CTRL => I_data_in_Control,
+ ND_2OP_1_Wr => signal_ed_1_out_FSL_M_Write,
+ ND_2OP_1_Dout(63 downto 0) => signal_ed_1_out_FSL_M_Data(0 to 63),
+ ND_2OP_1_Full => signal_ed_1_out_FSL_M_Full,
+ ND_2OP_1_CLK => open,
+ ND_2OP_1_CTRL => signal_ed_1_out_FSL_M_Control,
+ PARAM_DT => signal_PARAM_DT,
+ PARAM_LD => signal_PARAM_LD,
+ STOP => signal_hwn_nd_2_STOP,
+ ERROR => signal_hwn_nd_2_ERROR,
+ BLOCK_RD => signal_hwn_nd_2_BLOCK_RD,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ param_stream2rtl_hwn_nd_3_ip : param_stream2rtl_hwn_nd_3_ip_wrapper
+ port map (
+ rf_brightness ( 31 downto 0 ) => signal_SHMEM_WRITE_brightness ( 31 downto 0 ),
+ ND_3IP_1_Rd => signal_ed_1_in_FSL_S_Read,
+ ND_3IP_1_Din(63 downto 0) => signal_ed_1_in_FSL_S_Data(0 to 63),
+ ND_3IP_1_Exist => signal_ed_1_in_FSL_S_Exists,
+ ND_3IP_1_CLK => open,
+ ND_3IP_1_CTRL => signal_ed_1_in_FSL_S_Control,
+ ND_3OP_1_Wr => signal_ed_2_out_FSL_M_Write,
+ ND_3OP_1_Dout(63 downto 0) => signal_ed_2_out_FSL_M_Data(0 to 63),
+ ND_3OP_1_Full => signal_ed_2_out_FSL_M_Full,
+ ND_3OP_1_CLK => open,
+ ND_3OP_1_CTRL => signal_ed_2_out_FSL_M_Control,
+ PARAM_DT => signal_PARAM_DT,
+ PARAM_LD => signal_PARAM_LD,
+ STOP => signal_hwn_nd_3_STOP,
+ ERROR => signal_hwn_nd_3_ERROR,
+ BLOCK_RD => signal_hwn_nd_3_BLOCK_RD,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ param_stream2rtl_hwn_nd_4_ip : param_stream2rtl_hwn_nd_4_ip_wrapper
+ port map (
+ ND_4IP_2_Rd => signal_ed_2_in_FSL_S_Read,
+ ND_4IP_2_Din(63 downto 0) => signal_ed_2_in_FSL_S_Data(0 to 63),
+ ND_4IP_2_Exist => signal_ed_2_in_FSL_S_Exists,
+ ND_4IP_2_CLK => open,
+ ND_4IP_2_CTRL => signal_ed_2_in_FSL_S_Control,
+ data_out_Wr => I_data_out_Write,
+ data_out_Dout => I_data_out_Data(63 downto 0),
+ data_out_Full => I_data_out_Full,
+ data_out_CLK => open,
+ data_out_CTRL => I_data_out_Control,
+ PARAM_DT => signal_PARAM_DT,
+ PARAM_LD => signal_PARAM_LD,
+ STOP => signal_hwn_nd_4_STOP,
+ ERROR => signal_hwn_nd_4_ERROR,
+ BLOCK_RD => signal_hwn_nd_4_BLOCK_RD,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ param_stream2rtl_register_rf_ip : param_stream2rtl_register_rf_ip_wrapper
+ port map (
+ address => signal_address,
+ read_data => signal_read_data,
+ read_en => signal_read_en,
+ write_en => signal_write_en,
+ write_data => signal_write_data,
+ pci_clk => signal_register_rf_pci_clk,
+ brightness_rf_read_data => signal_SHMEM_READ_brightness,
+ brightness_rf_read_en => signal_SHMEM_READ_EN_brightness,
+ brightness_rf_write_en => signal_SHMEM_WRITE_EN_brightness,
+ brightness_rf_write_data => signal_SHMEM_WRITE_brightness,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ param_stream2rtl_ed_1 : param_stream2rtl_ed_1_ip_wrapper
+ port map (
+ FSL_Clk => sys_clk_s,
+ SYS_Rst => sys_rst_s,
+ FSL_Rst => open,
+ FSL_M_Clk => net_gnd0,
+ FSL_M_Data => signal_ed_1_out_FSL_M_Data,
+ FSL_M_Control => signal_ed_1_out_FSL_M_Control,
+ FSL_M_Write => signal_ed_1_out_FSL_M_Write,
+ FSL_M_Full => signal_ed_1_out_FSL_M_Full,
+ FSL_S_Data => signal_ed_1_in_FSL_S_Data,
+ FSL_S_Control => signal_ed_1_in_FSL_S_Control,
+ FSL_S_Read => signal_ed_1_in_FSL_S_Read,
+ FSL_S_Exists => signal_ed_1_in_FSL_S_Exists,
+ FSL_S_Clk => net_gnd0,
+ FSL_FULL => signal_ed_1_FIFO_FULL,
+ FSL_Has_Data => open,
+ FSL_Control_IRQ => open
+ );
+
+ param_stream2rtl_ed_2 : param_stream2rtl_ed_2_ip_wrapper
+ port map (
+ FSL_Clk => sys_clk_s,
+ SYS_Rst => sys_rst_s,
+ FSL_Rst => open,
+ FSL_M_Clk => net_gnd0,
+ FSL_M_Data => signal_ed_2_out_FSL_M_Data,
+ FSL_M_Control => signal_ed_2_out_FSL_M_Control,
+ FSL_M_Write => signal_ed_2_out_FSL_M_Write,
+ FSL_M_Full => signal_ed_2_out_FSL_M_Full,
+ FSL_S_Data => signal_ed_2_in_FSL_S_Data,
+ FSL_S_Control => signal_ed_2_in_FSL_S_Control,
+ FSL_S_Read => signal_ed_2_in_FSL_S_Read,
+ FSL_S_Exists => signal_ed_2_in_FSL_S_Exists,
+ FSL_S_Clk => net_gnd0,
+ FSL_FULL => signal_ed_2_FIFO_FULL,
+ FSL_Has_Data => open,
+ FSL_Control_IRQ => open
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_ed_1_ip_wrapper.vhd b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_ed_1_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..345ff987ed154afade429a62c43daca65c86313c
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_ed_1_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- param_stream2rtl_ed_1_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity param_stream2rtl_ed_1_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 63);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 63);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+
+
+end param_stream2rtl_ed_1_ip_wrapper;
+
+architecture STRUCTURE of param_stream2rtl_ed_1_ip_wrapper is
+
+ component fsl_v20 is
+ generic (
+ C_EXT_RESET_HIGH : INTEGER := 1;
+ C_ASYNC_CLKS : INTEGER := 0;
+ C_IMPL_STYLE : INTEGER := 0;
+ C_USE_CONTROL : INTEGER := 1;
+ C_FSL_DWIDTH : INTEGER := 32;
+ C_FSL_DEPTH : INTEGER := 16;
+ C_READ_CLOCK_PERIOD : INTEGER := 0
+ );
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 63);
+ FSL_M_Control: in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 63);
+ FSL_S_Control: out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+begin
+
+ param_stream2rtl_ed_1 : fsl_v20
+ generic map (
+ C_EXT_RESET_HIGH => 1,
+ C_ASYNC_CLKS => 0,
+ C_IMPL_STYLE => 0,
+ C_USE_CONTROL => 1,
+ C_FSL_DWIDTH => 64,
+ C_FSL_DEPTH => 16,
+ C_READ_CLOCK_PERIOD => 0
+ )
+ port map (
+ FSL_Clk => FSL_Clk,
+ SYS_Rst => SYS_Rst,
+ FSL_Rst => FSL_Rst,
+ FSL_M_Clk => FSL_M_Clk,
+ FSL_M_Data => FSL_M_Data,
+ FSL_M_Control => FSL_M_Control,
+ FSL_M_Write => FSL_M_Write,
+ FSL_M_Full => FSL_M_Full,
+ FSL_S_Clk => FSL_S_Clk,
+ FSL_S_Data => FSL_S_Data,
+ FSL_S_Control => FSL_S_Control,
+ FSL_S_Read => FSL_S_Read,
+ FSL_S_Exists => FSL_S_Exists,
+ FSL_Full => FSL_Full,
+ FSL_Has_Data => FSL_Has_Data,
+ FSL_Control_IRQ => FSL_Control_IRQ
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_ed_2_ip_wrapper.vhd b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_ed_2_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0766ba0cccd665d430c07cdb7f24d4d9797040be
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_ed_2_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- param_stream2rtl_ed_2_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity param_stream2rtl_ed_2_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 63);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 63);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+
+
+end param_stream2rtl_ed_2_ip_wrapper;
+
+architecture STRUCTURE of param_stream2rtl_ed_2_ip_wrapper is
+
+ component fsl_v20 is
+ generic (
+ C_EXT_RESET_HIGH : INTEGER := 1;
+ C_ASYNC_CLKS : INTEGER := 0;
+ C_IMPL_STYLE : INTEGER := 0;
+ C_USE_CONTROL : INTEGER := 1;
+ C_FSL_DWIDTH : INTEGER := 32;
+ C_FSL_DEPTH : INTEGER := 16;
+ C_READ_CLOCK_PERIOD : INTEGER := 0
+ );
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 63);
+ FSL_M_Control: in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 63);
+ FSL_S_Control: out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+begin
+
+ param_stream2rtl_ed_2 : fsl_v20
+ generic map (
+ C_EXT_RESET_HIGH => 1,
+ C_ASYNC_CLKS => 0,
+ C_IMPL_STYLE => 0,
+ C_USE_CONTROL => 1,
+ C_FSL_DWIDTH => 64,
+ C_FSL_DEPTH => 16,
+ C_READ_CLOCK_PERIOD => 0
+ )
+ port map (
+ FSL_Clk => FSL_Clk,
+ SYS_Rst => SYS_Rst,
+ FSL_Rst => FSL_Rst,
+ FSL_M_Clk => FSL_M_Clk,
+ FSL_M_Data => FSL_M_Data,
+ FSL_M_Control => FSL_M_Control,
+ FSL_M_Write => FSL_M_Write,
+ FSL_M_Full => FSL_M_Full,
+ FSL_S_Clk => FSL_S_Clk,
+ FSL_S_Data => FSL_S_Data,
+ FSL_S_Control => FSL_S_Control,
+ FSL_S_Read => FSL_S_Read,
+ FSL_S_Exists => FSL_S_Exists,
+ FSL_Full => FSL_Full,
+ FSL_Has_Data => FSL_Has_Data,
+ FSL_Control_IRQ => FSL_Control_IRQ
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_2_ip_wrapper.vhd b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_2_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3920cd515712cc8bb7c5b5e13998f32f86a09782
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_2_ip_wrapper.vhd
@@ -0,0 +1,100 @@
+-------------------------------------------------------------------------------
+-- param_stream2rtl_hwn_nd_2_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib;
+use compaandesign_com_param_stream2rtl_hwn_nd_2_1_lib.all;
+
+entity param_stream2rtl_hwn_nd_2_ip_wrapper is
+ port (
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(63 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end param_stream2rtl_hwn_nd_2_ip_wrapper;
+
+architecture STRUCTURE of param_stream2rtl_hwn_nd_2_ip_wrapper is
+
+ component param_stream2rtl_hwn_nd_2 is
+ generic (
+ RESET_HIGH : NATURAL := 1;
+ PAR_WIDTH : NATURAL := 16;
+ QUANT : NATURAL := 32;
+ WRAP : BOOLEAN := true;
+ STIM_DIR : STRING := "hwn_nd_2"
+ );
+ port (
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(63 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+param_stream2rtl_hwn_nd_2_ip_wrapper_ip : param_stream2rtl_hwn_nd_2
+ generic map (
+ RESET_HIGH => 1,
+ PAR_WIDTH => 1,
+ QUANT => 32,
+ WRAP => true,
+ STIM_DIR => "compaandesign_com/param_stream2rtl/hwn_nd_2/tb/data/"
+ )
+ port map (
+ data_in_Rd => data_in_Rd,
+ data_in_Din => data_in_Din,
+ data_in_Exist => data_in_Exist,
+ data_in_CLK => data_in_CLK,
+ data_in_CTRL => data_in_CTRL,
+ ND_2OP_1_Wr => ND_2OP_1_Wr,
+ ND_2OP_1_Dout => ND_2OP_1_Dout,
+ ND_2OP_1_Full => ND_2OP_1_Full,
+ ND_2OP_1_CLK => ND_2OP_1_CLK,
+ ND_2OP_1_CTRL => ND_2OP_1_CTRL,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ STOP => STOP,
+ ERROR => ERROR,
+ BLOCK_RD => BLOCK_RD,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_3_ip_wrapper.vhd b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_3_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a4cf951cbefc4a14d9482786dd5f99148227c574
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_3_ip_wrapper.vhd
@@ -0,0 +1,103 @@
+-------------------------------------------------------------------------------
+-- param_stream2rtl_hwn_nd_3_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib;
+use compaandesign_com_param_stream2rtl_hwn_nd_3_1_lib.all;
+
+entity param_stream2rtl_hwn_nd_3_ip_wrapper is
+ port (
+ rf_brightness : in std_logic_vector(31 downto 0);
+ ND_3IP_1_Rd : out std_logic;
+ ND_3IP_1_Din : in std_logic_vector(63 downto 0);
+ ND_3IP_1_Exist : in std_logic;
+ ND_3IP_1_CLK : out std_logic;
+ ND_3IP_1_CTRL : in std_logic;
+ ND_3OP_1_Wr : out std_logic;
+ ND_3OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_3OP_1_Full : in std_logic;
+ ND_3OP_1_CLK : out std_logic;
+ ND_3OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end param_stream2rtl_hwn_nd_3_ip_wrapper;
+
+architecture STRUCTURE of param_stream2rtl_hwn_nd_3_ip_wrapper is
+
+ component param_stream2rtl_hwn_nd_3 is
+ generic (
+ RESET_HIGH : NATURAL := 1;
+ PAR_WIDTH : NATURAL := 16;
+ QUANT : NATURAL := 32;
+ WRAP : BOOLEAN := true;
+ STIM_DIR : STRING := "hwn_nd_3"
+ );
+ port (
+ rf_brightness : in std_logic_vector(31 downto 0);
+ ND_3IP_1_Rd : out std_logic;
+ ND_3IP_1_Din : in std_logic_vector(63 downto 0);
+ ND_3IP_1_Exist : in std_logic;
+ ND_3IP_1_CLK : out std_logic;
+ ND_3IP_1_CTRL : in std_logic;
+ ND_3OP_1_Wr : out std_logic;
+ ND_3OP_1_Dout : out std_logic_vector(63 downto 0);
+ ND_3OP_1_Full : in std_logic;
+ ND_3OP_1_CLK : out std_logic;
+ ND_3OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+param_stream2rtl_hwn_nd_3_ip_wrapper_ip : param_stream2rtl_hwn_nd_3
+ generic map (
+ RESET_HIGH => 1,
+ PAR_WIDTH => 1,
+ QUANT => 32,
+ WRAP => true,
+ STIM_DIR => "compaandesign_com/param_stream2rtl/hwn_nd_3/tb/data/"
+ )
+ port map (
+ rf_brightness => rf_brightness,
+ ND_3IP_1_Rd => ND_3IP_1_Rd,
+ ND_3IP_1_Din => ND_3IP_1_Din,
+ ND_3IP_1_Exist => ND_3IP_1_Exist,
+ ND_3IP_1_CLK => ND_3IP_1_CLK,
+ ND_3IP_1_CTRL => ND_3IP_1_CTRL,
+ ND_3OP_1_Wr => ND_3OP_1_Wr,
+ ND_3OP_1_Dout => ND_3OP_1_Dout,
+ ND_3OP_1_Full => ND_3OP_1_Full,
+ ND_3OP_1_CLK => ND_3OP_1_CLK,
+ ND_3OP_1_CTRL => ND_3OP_1_CTRL,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ STOP => STOP,
+ ERROR => ERROR,
+ BLOCK_RD => BLOCK_RD,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_4_ip_wrapper.vhd b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_4_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f76ec82d4abd843e49a0eb023502f4eecae91e49
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_hwn_nd_4_ip_wrapper.vhd
@@ -0,0 +1,100 @@
+-------------------------------------------------------------------------------
+-- param_stream2rtl_hwn_nd_4_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib;
+use compaandesign_com_param_stream2rtl_hwn_nd_4_1_lib.all;
+
+entity param_stream2rtl_hwn_nd_4_ip_wrapper is
+ port (
+ ND_4IP_2_Rd : out std_logic;
+ ND_4IP_2_Din : in std_logic_vector(63 downto 0);
+ ND_4IP_2_Exist : in std_logic;
+ ND_4IP_2_CLK : out std_logic;
+ ND_4IP_2_CTRL : in std_logic;
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(63 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end param_stream2rtl_hwn_nd_4_ip_wrapper;
+
+architecture STRUCTURE of param_stream2rtl_hwn_nd_4_ip_wrapper is
+
+ component param_stream2rtl_hwn_nd_4 is
+ generic (
+ RESET_HIGH : NATURAL := 1;
+ PAR_WIDTH : NATURAL := 16;
+ QUANT : NATURAL := 32;
+ WRAP : BOOLEAN := true;
+ STIM_DIR : STRING := "hwn_nd_4"
+ );
+ port (
+ ND_4IP_2_Rd : out std_logic;
+ ND_4IP_2_Din : in std_logic_vector(63 downto 0);
+ ND_4IP_2_Exist : in std_logic;
+ ND_4IP_2_CLK : out std_logic;
+ ND_4IP_2_CTRL : in std_logic;
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(63 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+param_stream2rtl_hwn_nd_4_ip_wrapper_ip : param_stream2rtl_hwn_nd_4
+ generic map (
+ RESET_HIGH => 1,
+ PAR_WIDTH => 1,
+ QUANT => 32,
+ WRAP => true,
+ STIM_DIR => "compaandesign_com/param_stream2rtl/hwn_nd_4/tb/data/"
+ )
+ port map (
+ ND_4IP_2_Rd => ND_4IP_2_Rd,
+ ND_4IP_2_Din => ND_4IP_2_Din,
+ ND_4IP_2_Exist => ND_4IP_2_Exist,
+ ND_4IP_2_CLK => ND_4IP_2_CLK,
+ ND_4IP_2_CTRL => ND_4IP_2_CTRL,
+ data_out_Wr => data_out_Wr,
+ data_out_Dout => data_out_Dout,
+ data_out_Full => data_out_Full,
+ data_out_CLK => data_out_CLK,
+ data_out_CTRL => data_out_CTRL,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ STOP => STOP,
+ ERROR => ERROR,
+ BLOCK_RD => BLOCK_RD,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_register_rf_ip_wrapper.vhd b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_register_rf_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b0e1325c6b387a4747c8062c9b342d5870425292
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/param_stream2rtl_register_rf_ip_wrapper.vhd
@@ -0,0 +1,77 @@
+-------------------------------------------------------------------------------
+-- param_stream2rtl_register_rf_ip_wrapper.vhd
+-- LEAF true
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_param_stream2rtl_register_rf_1_lib;
+use compaandesign_com_param_stream2rtl_register_rf_1_lib.all;
+
+entity param_stream2rtl_register_rf_ip_wrapper is
+ port (
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ brightness_rf_read_data : in std_logic_vector(31 downto 0);
+ brightness_rf_read_en : out std_logic;
+ brightness_rf_write_en : out std_logic;
+ brightness_rf_write_data : out std_logic_vector(31 downto 0);
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end param_stream2rtl_register_rf_ip_wrapper;
+
+architecture STRUCTURE of param_stream2rtl_register_rf_ip_wrapper is
+
+ component register_rf is
+ generic (
+ C_brightness_rf_address : std_logic_vector := B"0000000000000000000"
+ );
+ port (
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ brightness_rf_read_data : in std_logic_vector(31 downto 0);
+ brightness_rf_read_en : out std_logic;
+ brightness_rf_write_en : out std_logic;
+ brightness_rf_write_data : out std_logic_vector(31 downto 0);
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+param_stream2rtl_register_rf_ip_wrapper_ip : register_rf
+ generic map (
+ C_brightness_rf_address => B"0000000000000000000"
+ )
+ port map (
+ address => address,
+ read_data => read_data,
+ read_en => read_en,
+ write_en => write_en,
+ write_data => write_data,
+ pci_clk => pci_clk,
+ brightness_rf_read_data => brightness_rf_read_data,
+ brightness_rf_read_en => brightness_rf_read_en,
+ brightness_rf_write_en => brightness_rf_write_en,
+ brightness_rf_write_data => brightness_rf_write_data,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/param_stream/src/vhdl/system_ext_TB.vhd b/applications/compaan/libraries/param_stream/src/vhdl/system_ext_TB.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5615e599ba872351f0afbea2f1c01716dffa3333
--- /dev/null
+++ b/applications/compaan/libraries/param_stream/src/vhdl/system_ext_TB.vhd
@@ -0,0 +1,421 @@
+-- System TestBench; automatically generated by KpnMapper
+-- Use this file to test the system generated by XPS
+-- The interface of the tested System includes only the FIFO interfaces
+-- declared as external interfaces and not the FIFO interfaces connected
+-- to platform FIFOs
+-- To generate a System with complete interface select the *noboard* platform option
+--
+-- =====================================================================================
+-- To use this testbench file you have to:
+-- 1. Set propper Time-Out interval (constant TIMEOUT)
+-- 2. If you read stimuli from files, provide a path to the directory that contains the stimuli files (constant STIM_DIR)
+-- 3. For each input select whether stimuli is read from a file (default) or from a table (see processes *_STIM_DRV)
+-- 4. For each output select whether stimuli is read from a file (default) or from a table (see processes *_STIM_CMP)
+-- 5. For each stimuli that is read from a table fill the stimuli data in the table (constant *_STIM)
+-- =====================================================================================
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+entity system_ext_TB is
+end system_ext_TB;
+
+architecture RTL of system_ext_TB is
+
+ constant CLK_PERIOD : TIME := 10 ns; -- Period of the system clock
+ constant RESET_LENGTH : natural := 5; -- Reset duration [clock cycles]
+ constant STIM_DELAY : natural := RESET_LENGTH + 5; -- When stimuli supply starts [clock cycles]
+ --
+ -- Set Time-0ut interval sufficienly long for your application to complete
+ constant TIMEOUT : natural := 10000000; -- Time-Out [clock cycles]
+ --
+ constant STIM_DIR : string := "D:/Bureaublad/Astron/Bijbaan/compaan/workspace/param_stream/vhdl_altera/"; -- Provide here the path to your stimuli files directory
+ -- Input stimuli files: to provide data streams to input FIFOs
+ constant STIM_FILE_data_in : string := "STIM_FILE_data_in.txt";
+ constant STIM_FILE_data_out : string := "STIM_FILE_data_out.txt";
+
+ signal ENDSIM : boolean := false; -- Simulation has finished
+ signal ENDSTIM_IN : boolean := false; -- All input stimuli has been sent
+ signal ENDSTIM_OUT : boolean := false; -- All expected data has been received
+ signal ENDTIMEOUT : boolean := false; -- Simulation Time-Out has occured
+ signal timeout_cntr : natural;
+ signal ERROR_SYS : boolean := false; -- Error: Some of te system nodes indicated error
+ signal ERROR_OUT : boolean := false; -- Error: Detected output data differs from the expected output data
+ signal FIRST_ERROR : time; -- The time when the first error occured
+ signal ENDSTOP : boolean := false; -- All system nodes have flagged 'Stop'
+
+ --
+ -- Component Under Test
+ component param_stream is
+ port (
+ -- FIFO_In Interface: data_in
+ data_in_Data : in std_logic_vector(63 downto 0);
+ data_in_Control : in std_logic;
+ data_in_Read : out std_logic;
+ data_in_Exists : in std_logic;
+
+ -- FIFO_Out Interface: data_out
+ data_out_Data : out std_logic_vector(63 downto 0);
+ data_out_Control : out std_logic;
+ data_out_Write : out std_logic;
+ data_out_Full : in std_logic;
+
+ TEST_STOP : out std_logic_vector(3 downto 0);
+ TEST_ERROR : out std_logic_vector(3 downto 0);
+ TEST_FIFO_FULL : out std_logic_vector(1 downto 0);
+ TEST_BLOCK_RD : out std_logic_vector(3 downto 0);
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ --
+ KPN_CLK : in std_logic;
+ KPN_RST : in std_logic
+ );
+ end component;
+ --
+ signal RST : STD_LOGIC := '0';
+ signal CLK : STD_LOGIC := '0';
+ --
+ type FIFO_SRC_REC is record
+ Data : integer;
+ Control : std_logic;
+ Read : std_logic;
+ Exists : std_logic;
+ --
+ Count : natural;
+ Done : boolean;
+ end record;
+ --
+ type FIFO_SNK_REC is record
+ Data : integer;
+ Control : std_logic;
+ Write : std_logic;
+ Full : std_logic;
+ --
+ Count : natural;
+ Done : boolean;
+ Error : boolean;
+ First_error : time;
+ end record;
+ --
+ signal data_in : FIFO_SRC_REC;
+ signal data_out : FIFO_SNK_REC;
+ --
+ signal data_in_Data : std_logic_vector(63 downto 0);
+ signal data_out_Data : std_logic_vector(63 downto 0);
+ signal TEST_STOP : std_logic_vector(3 downto 0);
+ signal TEST_ERROR : std_logic_vector(3 downto 0);
+ signal TEST_FIFO_FULL : std_logic_vector(1 downto 0);
+ signal TEST_BLOCK_RD : std_logic_vector(3 downto 0);
+ signal address : std_logic_vector(18 downto 0);
+ signal read_data : std_logic_vector(31 downto 0);
+ signal read_en : std_logic;
+ signal write_en : std_logic;
+ signal write_data : std_logic_vector(31 downto 0);
+ signal pci_clk : std_logic;
+ --
+ -- record keeping values of input and output stimuli
+ type STIM_REC is record
+ Data : integer;
+ Control : std_logic;
+ end record;
+ --
+ -- Function that reads a STIM_REC from a (stimuli) file
+ impure function FREAD_STIM(file F : TEXT) return STIM_REC is
+ variable VECTOR : STIM_REC;
+ variable IN_LINE : LINE;
+ begin
+ readline(F ,IN_LINE);
+ read(IN_LINE, VECTOR.Data);
+ deallocate(IN_LINE);
+ VECTOR.Control := '0'; -- Control bit is not used at the moment
+ return VECTOR;
+ end;
+ --
+ -- table of records
+ type STIM_ARRAY is array(positive range <>) of STIM_REC;
+ --
+ -- Stimuli can be read either from a file or from the constant tables below
+ -- If you will use constant tables, uncomment below those you need
+-- constant data_in_STIM : STIM_ARRAY := (
+-- -- Provide your stimuli here
+-- -- ( Data, Control),
+-- -- e.g. ( 0, '0'),
+-- -- e.g. ( 0, '0')
+-- );
+ --
+-- constant data_out_STIM : STIM_ARRAY := (
+-- -- Provide your stimuli here
+-- -- ( Data, Control),
+-- -- e.g. ( 0, '0'),
+-- -- e.g. ( 0, '0')
+-- );
+ --
+begin
+ --
+ -- =============================================
+ -- = System Under Test
+ -- =============================================
+ SUT : param_stream port map(
+ --
+ data_in_Data => data_in_Data ,
+ data_in_Control => data_in.Control ,
+ data_in_Read => data_in.Read ,
+ data_in_Exists => data_in.Exists ,
+ --
+ data_out_Data => data_out_Data ,
+ data_out_Control => data_out.Control ,
+ data_out_Write => data_out.Write ,
+ data_out_Full => data_out.Full ,
+ TEST_STOP => TEST_STOP ,
+ TEST_ERROR => TEST_ERROR ,
+ TEST_FIFO_FULL => TEST_FIFO_FULL ,
+ TEST_BLOCK_RD => TEST_BLOCK_RD ,
+ address => address ,
+ read_data => read_data ,
+ read_en => read_en ,
+ write_en => write_en ,
+ write_data => write_data ,
+ pci_clk => pci_clk ,
+ --
+ KPN_CLK => CLK,
+ KPN_RST => RST
+ );
+ --
+ pci_clk <= CLK;
+ --
+ data_in_Data <= STD_LOGIC_VECTOR(TO_SIGNED(data_in.Data, data_in_Data'Length));
+ data_out.Data <= TO_INTEGER(SIGNED(data_out_Data));
+
+ -- Adjust these values to changes values in the Register file to change parameters and shmem
+reg_file : process
+ variable read_in : std_logic_vector(31 downto 0);
+begin
+ address <= (others => '0');
+ write_en <= '0';
+ read_en <= '0';
+ address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
+ write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
+
+-- wait for 100ns;
+-- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
+-- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
+-- wait for 1*CLK_PERIOD;
+-- write_en <= '1';
+-- wait for 2*CLK_PERIOD;
+-- write_en <= '0';
+-- wait for 1*CLK_PERIOD;
+-- --read_en <= '1';
+-- wait for 2*CLK_PERIOD;
+-- --read_en <= '0';
+-- wait for 1*CLK_PERIOD;
+-- wait for 300ns;
+ wait;
+end process;
+
+ --
+ -- Stimuli Driver for input stream : data_in
+ data_in_STIM_DRV : process
+ variable VECTOR : STIM_REC;
+ file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_in;
+ begin
+ data_in.Exists <= '0';
+ data_in.Count <= 0;
+ data_in.Done <= false;
+ wait for STIM_DELAY*CLK_PERIOD;
+ wait until rising_edge(CLK);
+----------------------------------------------
+-- -- Uncomment if stimuli for data_in is read from a constant tables
+-- for i in data_in_STIM'range loop
+-- VECTOR:= data_in_STIM(i);
+----------------------------------------------
+ -- Uncomment if stimuli for data_in is read from a file
+ while not( endfile(STIM_FILE)) loop
+ VECTOR := FREAD_STIM(STIM_FILE);
+--------------------------------------------
+ data_in.Data <= VECTOR.Data;
+ data_in.Control <= VECTOR.Control;
+ data_in.Exists <= '1';
+ L1: loop
+ wait until rising_edge(CLK);
+ exit L1 when (data_in.Read = '1');
+ end loop L1;
+ data_in.Count <= data_in.Count + 1;
+ end loop;
+ data_in.Exists <= '0';
+ data_in.Done <= true;
+ wait for 10*CLK_PERIOD;
+ wait;
+ end process;
+ --
+ ENDSTIM_IN <= data_in.Done;
+ --
+ -- Stimuli Comparator for output stream data_out
+ data_out_STIM_CMP : process
+ variable VECTOR : STIM_REC;
+ file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_out;
+ begin
+ data_out.Full <= '1';
+ data_out.Count <= 0;
+ data_out.Done <= false;
+ data_out.Error <= false;
+ wait for STIM_DELAY*CLK_PERIOD;
+ wait until rising_edge(CLK);
+----------------------------------------------
+-- -- Uncomment if stimuli for data_out is read from a constant tables
+-- for i in data_out_STIM'range loop
+-- VECTOR := data_out_STIM(i);
+----------------------------------------------
+ -- Uncomment if stimuli for data_out is read from a file
+ while not( endfile(STIM_FILE)) loop
+ VECTOR := FREAD_STIM(STIM_FILE);
+----------------------------------------------
+ --
+ data_out.Full <= '0';
+ L1: loop
+ wait until rising_edge(CLK);
+ exit L1 when (data_out.Write = '1');
+ end loop L1;
+ data_out.Count <= data_out.Count + 1;
+ if (data_out.Data /= VECTOR.Data) then
+ report "TB_ERROR: Output 'data_out': the detected value " & integer'image(data_out.Data) & " differs from the expected value " & integer'image(VECTOR.Data) & "!!! (@time " & time'image(now) & ")."
+ severity WARNING;
+ if (not data_out.Error) then
+ data_out.First_error <= now;
+ end if;
+ data_out.Error <= true;
+ end if;
+ end loop;
+ data_out.Full <= '1';
+ data_out.Done <= true;
+ wait for 10*CLK_PERIOD;
+ wait;
+ end process;
+ --
+ ENDSTIM_OUT <= data_out.Done;
+ ERROR_OUT <= data_out.Error;
+ --
+ -- Record the time when the first error occures
+ FIRST_ERROR_TIME : process
+ begin
+ wait until (ERROR_OUT'event and ERROR_OUT=true) or (ERROR_SYS'event and ERROR_SYS=true);
+ FIRST_ERROR <= now;
+ wait;
+ end process;
+ --
+--=============================================
+--= All Nodes stopped ?
+--=============================================
+ process(test_stop)
+ variable s : std_logic;
+ variable e : std_logic;
+ begin
+ s := '1';
+ e := '0';
+ --
+ for i in 0 to TEST_ERROR'Length-1 loop
+ s := s and test_stop(i);
+ e := e or test_error(i);
+ end loop;
+ --
+ ENDSTOP <= (s = '1');
+ ERROR_SYS <= (e = '1');
+ --
+ end process;
+ -- Timeout counter
+ TO_CTRL : process(CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RST = '1') then
+ timeout_cntr <= 0;
+ else
+ if (timeout_cntr = TIMEOUT) then
+ ENDTIMEOUT <= true;
+ else
+ timeout_cntr <= timeout_cntr + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ -- Simulation control
+ ENDSIM <= (ENDSTIM_IN and ENDSTOP and ENDSTIM_OUT) or ENDTIMEOUT;
+ --
+ PRINT_REPORT : process
+ variable ERROR_CODE : natural;
+ variable l : line;
+ begin
+ -- write(l, "***TB_REPOT: Simulation in progress...");
+ writeline(output,l);
+ wait until ENDSIM=true;
+ -- write(l, "***TB_REPOT: Simulation END.");
+ writeline(output,l);
+ ERROR_CODE := 0;
+ --
+ if (ENDTIMEOUT) then
+ ERROR_CODE := ERROR_CODE + 1;
+ write(l, "***TB_REPOT: [TIMEOUT] Simulation terminated by a TIMEOUT after " & integer'image(timeout_cntr) & " clock cycles.");
+ writeline(output,l);
+ write(l, "*** ENDSTIM_IN = " & boolean'image(ENDSTIM_IN) );
+ writeline(output,l);
+ write(l, "*** ENDSTIM_OUT = " & boolean'image(ENDSTIM_OUT) );
+ writeline(output,l);
+ for i in 0 to TEST_FIFO_FULL'Length-1 loop
+ if (TEST_FIFO_FULL(i)='1') then
+ write(l, "*** TEST_FIFO_FULL(" & integer'image(i) & ") ");
+ writeline(output,l);
+ end if;
+ end loop;
+ end if;
+ --
+ if (ERROR_OUT or ERROR_SYS) then
+ ERROR_CODE := ERROR_CODE + 2;
+ write(l, "***TB_REPOT: [ERROR] Simulation terminated in " & integer'image(timeout_cntr) & " cycles with ERRORS!!! First error occured at time " & time'image(FIRST_ERROR) & ".");
+ writeline(output,l);
+ -- write(l, "***TB_REPOT: [ERROR] Flags ERROR = b");
+ -- write(l, test_error, RIGHT, test_error'Length);
+ -- writeline(output,l);
+ end if;
+ --
+ write(l, "***TB_REPOT: [ERROR_CODE=" & integer'image(ERROR_CODE) & "]");
+ writeline(output,l);
+ --
+ if (ERROR_CODE = 0) then
+ write(l, "***TB_REPOT: [OK] Simulation completed successfully in " & integer'image(timeout_cntr) & " cycles !!!");
+ writeline(output,l);
+ -- write(l, "None of the processors flagged ERROR. ");
+ writeline(output,l);
+ end if;
+ wait;
+ end process;
+ --
+ -- CLK generator
+ CLK_GEN: process
+ begin
+ if (ENDSIM=false) then
+ CLK <= '0';
+ wait for CLK_PERIOD/2;
+ CLK <= '1';
+ wait for CLK_PERIOD/2;
+ else
+ wait;
+ end if;
+ end process;
+ --
+ -- RESET generator
+ RST_GEN: process
+ begin
+ RST <='1';
+ wait for RESET_LENGTH*CLK_PERIOD;
+ RST <='0';
+ wait;
+ end process;
+ --
+end RTL;