diff --git a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
index e0c5d02a0d86bc1b4930d3db098162bc3086720b..3ef74ed4aa3e21c184de1a27d457e0bbc2a01e92 100644
--- a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
@@ -117,7 +117,11 @@ END common_clock_phase_detector;
 ARCHITECTURE str OF common_clock_phase_detector IS
 
   CONSTANT c_period_len : NATURAL := 2*g_clk_factor;
-  CONSTANT c_delay_len  : NATURAL := ceil_value(g_meta_delay_len, c_period_len)+1 + g_offset_delay_len;  -- detect clock phase relation independent of g_meta_delay_len
+  CONSTANT c_delay_len  : NATURAL := ceil_div(g_meta_delay_len, c_period_len)*c_period_len+1 + g_offset_delay_len;  -- detect clock phase relation independent of g_meta_delay_len
+  
+  SIGNAL dbg_g_meta_delay_len : NATURAL := g_meta_delay_len;  -- to view it in the wave window
+  SIGNAL dbg_c_period_len     : NATURAL := c_period_len;  -- to view it in the wave window
+  SIGNAL dbg_c_delay_len      : NATURAL := c_delay_len;   -- to view it in the wave window
   
   SIGNAL in_phs_cap    : STD_LOGIC;
   SIGNAL in_phs        : STD_LOGIC;