From a4a516681eb64dfa8010697f9d93ce3277878c47 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 21 Apr 2016 16:20:14 +0000
Subject: [PATCH] added the c_rom_version and c_technology fields to system
info
---
.../libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd | 5 ++++-
.../unb2_board/src/vhdl/mms_unb2_board_system_info.vhd | 5 ++++-
.../unb2_board/src/vhdl/unb2_board_system_info.vhd | 10 +++++++---
.../unb2_board/src/vhdl/unb2_board_system_info_reg.vhd | 2 +-
4 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 91853d9cca..9499f34dbc 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -248,6 +248,8 @@ END ctrl_unb2_board;
ARCHITECTURE str OF ctrl_unb2_board IS
+ CONSTANT c_rom_version : NATURAL := 1; -- Only increment when something changes to the register map of rom_system_info.
+
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
-- Clock and reset
@@ -495,7 +497,8 @@ BEGIN
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
)
PORT MAP (
mm_clk => i_mm_clk,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index 7e70d05b55..69c9f0c602 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -36,6 +36,7 @@ ENTITY mms_unb2_board_system_info IS
g_stamp_time : NATURAL := 0;
g_stamp_svn : NATURAL := 0;
g_design_note : STRING := "";
+ g_rom_version : NATURAL := 1;
g_aux : t_c_unb2_board_aux := c_unb2_board_aux -- aux contains the hardware version
);
PORT (
@@ -90,7 +91,9 @@ BEGIN
u_unb2_board_system_info: ENTITY work.unb2_board_system_info
GENERIC MAP (
g_sim => g_sim,
- g_fw_version => g_fw_version
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
)
PORT MAP (
clk => mm_clk,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
index 7bf92453fe..a2be55ca47 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
@@ -20,10 +20,11 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE work.unb2_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
@@ -33,7 +34,9 @@ ENTITY unb2_board_system_info IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y (4b.4b)
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux -- aux contains the hardware version
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux; -- aux contains the hardware version
+ g_rom_version: NATURAL := 1;
+ g_technology : NATURAL := c_tech_arria10
);
PORT (
clk : IN STD_LOGIC;
@@ -82,7 +85,8 @@ BEGIN
p_info : PROCESS(cs_sim, hw_version_reg, id_reg)
BEGIN
- nxt_info <= (OTHERS=>'0');
+ nxt_info(31 DOWNTO 27) <= TO_UVEC(g_technology, 5);
+ nxt_info(26 DOWNTO 24) <= TO_UVEC(g_rom_version, 3);
nxt_info(23 DOWNTO 20) <= TO_UVEC(g_fw_version.hi, 4);
nxt_info(19 DOWNTO 16) <= TO_UVEC(g_fw_version.lo, 4);
nxt_info(10) <= cs_sim;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index d528a8d4b5..1622f91ceb 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -30,7 +30,7 @@
--
-- wi Bits R/W Name Default Description |REG_UNB2_BOARD_SYSTEM_INFO|
-- =============================================================================
--- 0 [23..0] RO info
+-- 0 [31..0] RO info
-- 1 [7..0] RO 0
-- 2 [31..0] RO design_name
-- . .. . ..
--
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