From a49dc03092e373ba17ba5456c867a4672f93301d Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 10 Oct 2019 07:39:44 +0200
Subject: [PATCH] changes needed for synthesize unb2b_minimal in quartus
---
.../unb1_board/quartus/unb1_board.qsf | 4 +-
.../unb1_board/quartus/unb1_board_head.qsf | 4 +-
.../unb2_board/quartus/unb2_board.qsf | 4 +-
.../unb2a_board/quartus/unb2a_board.qsf | 4 +-
.../quartus/unb2b_heater_pins.tcl | 2 +-
.../designs/unb2b_minimal/hdllib.cfg | 2 +-
.../unb2b_test/quartus/unb2b_test_pins.tcl | 6 +-
.../libraries/unb2b_board/hdllib.cfg | 60 +-
.../quartus/pinning/unb2b_10GbE_pins.tcl | 2510 +++++++++++++++++
.../quartus/pinning/unb2b_ddr_pins.tcl | 561 ++++
.../quartus/pinning/unb2b_minimal_pins.tcl | 327 +++
.../unb2b_board/quartus/unb2b_board.qsf | 4 +-
...rl_unb2_board.vhd => ctrl_unb2b_board.vhd} | 0
...oard_sens.vhd => mms_unb2b_board_sens.vhd} | 0
...fo.vhd => mms_unb2b_board_system_info.vhd} | 0
..._fpga_sens.vhd => mms_unb2b_fpga_sens.vhd} | 0
...rd_back_io.vhd => unb2b_board_back_io.vhd} | 0
...125_pll.vhd => unb2b_board_clk125_pll.vhd} | 0
...200_pll.vhd => unb2b_board_clk200_pll.vhd} | 0
...lk25_pll.vhd => unb2b_board_clk25_pll.vhd} | 0
...rd_clk_rst.vhd => unb2b_board_clk_rst.vhd} | 0
..._front_io.vhd => unb2b_board_front_io.vhd} | 0
..._hmc_ctrl.vhd => unb2b_board_hmc_ctrl.vhd} | 0
...ode_ctrl.vhd => unb2b_board_node_ctrl.vhd} | 0
...kg.vhd => unb2b_board_peripherals_pkg.vhd} | 0
...unb2_board_pkg.vhd => unb2b_board_pkg.vhd} | 0
...us_ctrl.vhd => unb2b_board_pmbus_ctrl.vhd} | 0
...sfp_leds.vhd => unb2b_board_qsfp_leds.vhd} | 0
...rd_ring_io.vhd => unb2b_board_ring_io.vhd} | 0
...b2_board_sens.vhd => unb2b_board_sens.vhd} | 0
...ens_ctrl.vhd => unb2b_board_sens_ctrl.vhd} | 0
..._sens_reg.vhd => unb2b_board_sens_reg.vhd} | 0
...m_info.vhd => unb2b_board_system_info.vhd} | 0
...eg.vhd => unb2b_board_system_info_reg.vhd} | 0
..._extend.vhd => unb2b_board_wdi_extend.vhd} | 0
...rd_wdi_reg.vhd => unb2b_board_wdi_reg.vhd} | 0
...a_sens_reg.vhd => unb2b_fpga_sens_reg.vhd} | 0
...d_sens.vhd => tb_mms_unb2b_board_sens.vhd} | 0
..._pll.vhd => tb_unb2b_board_clk125_pll.vhd} | 0
..._pll.vhd => tb_unb2b_board_clk200_pll.vhd} | 0
...5_pll.vhd => tb_unb2b_board_clk25_pll.vhd} | 0
..._ctrl.vhd => tb_unb2b_board_node_ctrl.vhd} | 0
..._leds.vhd => tb_unb2b_board_qsfp_leds.vhd} | 0
.../libraries/unb2b_board_10gbe/hdllib.cfg | 2 +-
..._board_10gbe.vhd => unb2b_board_10gbe.vhd} | 0
libraries/base/common/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/complex_mult/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/ddio/hdllib.cfg | 4 +-
.../ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg | 2 +-
.../ip_arria10_e1sg_ddr4_8g_2400.csv | 6 +-
.../ip_arria10_e1sg_ddr4_8g_2400.html | 4 +-
.../ip_arria10_e1sg_ddr4_8g_2400.qip | 4 +-
.../ip_arria10_e1sg_ddr4_8g_2400.sopcinfo | 4 +-
.../ip_arria10_e1sg_ddr4_8g_2400.xml | 12 +-
...p_arria10_e1sg_ddr4_8g_2400_generation.rpt | 10 +-
..._e1sg_ddr4_8g_2400_generation_previous.rpt | 14 +-
.../sim/aldec/rivierapro_setup.tcl | 2 +-
.../sim/cadence/ncsim_setup.sh | 4 +-
.../sim/mentor/msim_setup.tcl | 2 +-
.../sim/synopsys/vcsmx/vcsmx_setup.sh | 4 +-
.../flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/mac_10g/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/hdllib.cfg | 2 +-
.../phy_10gbase_r_3/hdllib.cfg | 2 +-
.../phy_10gbase_r_4/hdllib.cfg | 2 +-
.../phy_10gbase_r_48/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/pll_clk125/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/temp_sense/hdllib.cfg | 7 +-
.../transceiver_pll_10g/hdllib.cfg | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 2 +-
.../hdllib.cfg | 2 +-
.../hdllib.cfg | 2 +-
.../transceiver_reset_controller_3/hdllib.cfg | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 2 +-
.../hdllib.cfg | 2 +-
.../ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg | 2 +-
.../ip_arria10_e1sg/voltage_sense/hdllib.cfg | 3 +-
90 files changed, 3518 insertions(+), 114 deletions(-)
create mode 100644 boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
create mode 100644 boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
create mode 100644 boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{ctrl_unb2_board.vhd => ctrl_unb2b_board.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{mms_unb2_board_sens.vhd => mms_unb2b_board_sens.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{mms_unb2_board_system_info.vhd => mms_unb2b_board_system_info.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{mms_unb2_fpga_sens.vhd => mms_unb2b_fpga_sens.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_back_io.vhd => unb2b_board_back_io.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_clk125_pll.vhd => unb2b_board_clk125_pll.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_clk200_pll.vhd => unb2b_board_clk200_pll.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_clk25_pll.vhd => unb2b_board_clk25_pll.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_clk_rst.vhd => unb2b_board_clk_rst.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_front_io.vhd => unb2b_board_front_io.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_hmc_ctrl.vhd => unb2b_board_hmc_ctrl.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_node_ctrl.vhd => unb2b_board_node_ctrl.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_peripherals_pkg.vhd => unb2b_board_peripherals_pkg.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_pkg.vhd => unb2b_board_pkg.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_pmbus_ctrl.vhd => unb2b_board_pmbus_ctrl.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_qsfp_leds.vhd => unb2b_board_qsfp_leds.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_ring_io.vhd => unb2b_board_ring_io.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_sens.vhd => unb2b_board_sens.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_sens_ctrl.vhd => unb2b_board_sens_ctrl.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_sens_reg.vhd => unb2b_board_sens_reg.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_system_info.vhd => unb2b_board_system_info.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_system_info_reg.vhd => unb2b_board_system_info_reg.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_wdi_extend.vhd => unb2b_board_wdi_extend.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_board_wdi_reg.vhd => unb2b_board_wdi_reg.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/src/vhdl/{unb2_fpga_sens_reg.vhd => unb2b_fpga_sens_reg.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/tb/vhdl/{tb_mms_unb2_board_sens.vhd => tb_mms_unb2b_board_sens.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/tb/vhdl/{tb_unb2_board_clk125_pll.vhd => tb_unb2b_board_clk125_pll.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/tb/vhdl/{tb_unb2_board_clk200_pll.vhd => tb_unb2b_board_clk200_pll.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/tb/vhdl/{tb_unb2_board_clk25_pll.vhd => tb_unb2b_board_clk25_pll.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/tb/vhdl/{tb_unb2_board_node_ctrl.vhd => tb_unb2b_board_node_ctrl.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board/tb/vhdl/{tb_unb2_board_qsfp_leds.vhd => tb_unb2b_board_qsfp_leds.vhd} (100%)
rename boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/{unb2_board_10gbe.vhd => unb2b_board_10gbe.vhd} (100%)
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
index 35e67d8844..df08798116 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
@@ -49,7 +49,7 @@ set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN revision $::env(HDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(HDL_GIT_REVISION)] ""]
}
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
index 4d46b5409c..98f793e901 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
@@ -54,7 +54,7 @@ set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libr
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_GIT_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN revision $::env(HDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(HDL_GIT_REVISION)] ""]
}
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
index 072fd6fb68..0cedbdb8b4 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
@@ -107,7 +107,7 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_GIT_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN $::env(HDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(HDL_GIT_REVISION)] ""]
}
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
index 422aa619aa..b0c03d5eff 100644
--- a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
@@ -311,8 +311,8 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_GIT_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
+ post_message -type info "RADIOHDL: using SVN $::env(HDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(HDL_GIT_REVISION)] ""]
}
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
diff --git a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
index ba69570cfa..8201bf923e 100644
--- a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
@@ -18,4 +18,4 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 2c45357259..652892608d 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -20,7 +20,6 @@ test_bench_files =
synth_top_level_entity =
quartus_copy_files =
- #quartus/qsys_unb2b_minimal.qsys .
quartus .
quartus_qsf_files =
@@ -36,6 +35,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+ #$HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/unb2b_minimal_lib.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
index c0483d1585..5269edaf0f 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
diff --git a/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg b/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg
index eeaa49ec3f..d6751c34cd 100644
--- a/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg
+++ b/boards/uniboard2b/libraries/unb2b_board/hdllib.cfg
@@ -12,38 +12,38 @@ hdl_lib_include_ip = ip_arria10_e1sg_tse_sgmii_lvds
#ip_arria10_e1sg_pll_clk125
synth_files =
- src/vhdl/unb2_board_pkg.vhd
- src/vhdl/unb2_board_system_info.vhd
- src/vhdl/unb2_board_system_info_reg.vhd
- src/vhdl/mms_unb2_board_system_info.vhd
- src/vhdl/unb2_board_clk200_pll.vhd
- src/vhdl/unb2_board_clk25_pll.vhd
- src/vhdl/unb2_board_clk125_pll.vhd
-# src/vhdl/unb2_board_clk200mm_pll.vhd
- src/vhdl/unb2_board_wdi_extend.vhd
- src/vhdl/unb2_board_node_ctrl.vhd
- src/vhdl/unb2_board_pmbus_ctrl.vhd
- src/vhdl/unb2_board_sens_ctrl.vhd
- src/vhdl/unb2_board_hmc_ctrl.vhd
- src/vhdl/unb2_board_sens.vhd
- src/vhdl/unb2_board_sens_reg.vhd
- src/vhdl/unb2_fpga_sens_reg.vhd
- src/vhdl/mms_unb2_board_sens.vhd
- src/vhdl/mms_unb2_fpga_sens.vhd
- src/vhdl/unb2_board_wdi_reg.vhd
- src/vhdl/unb2_board_qsfp_leds.vhd
- src/vhdl/ctrl_unb2_board.vhd
- src/vhdl/unb2_board_front_io.vhd
- src/vhdl/unb2_board_back_io.vhd
- src/vhdl/unb2_board_ring_io.vhd
- src/vhdl/unb2_board_peripherals_pkg.vhd
+ src/vhdl/unb2b_board_pkg.vhd
+ src/vhdl/unb2b_board_system_info.vhd
+ src/vhdl/unb2b_board_system_info_reg.vhd
+ src/vhdl/mms_unb2b_board_system_info.vhd
+ src/vhdl/unb2b_board_clk200_pll.vhd
+ src/vhdl/unb2b_board_clk25_pll.vhd
+ src/vhdl/unb2b_board_clk125_pll.vhd
+# src/vhdl/unb2b_board_clk200mm_pll.vhd
+ src/vhdl/unb2b_board_wdi_extend.vhd
+ src/vhdl/unb2b_board_node_ctrl.vhd
+ src/vhdl/unb2b_board_pmbus_ctrl.vhd
+ src/vhdl/unb2b_board_sens_ctrl.vhd
+ src/vhdl/unb2b_board_hmc_ctrl.vhd
+ src/vhdl/unb2b_board_sens.vhd
+ src/vhdl/unb2b_board_sens_reg.vhd
+ src/vhdl/unb2b_fpga_sens_reg.vhd
+ src/vhdl/mms_unb2b_board_sens.vhd
+ src/vhdl/mms_unb2b_fpga_sens.vhd
+ src/vhdl/unb2b_board_wdi_reg.vhd
+ src/vhdl/unb2b_board_qsfp_leds.vhd
+ src/vhdl/ctrl_unb2b_board.vhd
+ src/vhdl/unb2b_board_front_io.vhd
+ src/vhdl/unb2b_board_back_io.vhd
+ src/vhdl/unb2b_board_ring_io.vhd
+ src/vhdl/unb2b_board_peripherals_pkg.vhd
test_bench_files =
- tb/vhdl/tb_mms_unb2_board_sens.vhd
- tb/vhdl/tb_unb2_board_clk200_pll.vhd
- tb/vhdl/tb_unb2_board_clk25_pll.vhd
- tb/vhdl/tb_unb2_board_node_ctrl.vhd
- tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+ tb/vhdl/tb_mms_unb2b_board_sens.vhd
+ tb/vhdl/tb_unb2b_board_clk200_pll.vhd
+ tb/vhdl/tb_unb2b_board_clk25_pll.vhd
+ tb/vhdl/tb_unb2b_board_node_ctrl.vhd
+ tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
[modelsim_project_file]
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
new file mode 100644
index 0000000000..e7aa9a9a57
--- /dev/null
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
@@ -0,0 +1,2510 @@
+
+set_location_assignment PIN_AL32 -to CLKUSR
+
+
+set_location_assignment PIN_Y36 -to SA_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
+# internal termination should be enabled.
+set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK
+
+
+set_location_assignment PIN_AH9 -to SB_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
+# internal termination should be enabled.
+set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SB_CLK
+
+
+set_location_assignment PIN_V9 -to BCK_REF_CLK
+set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+
+
+
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
+
+# QSFP_0_RX
+set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
+set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
+set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
+set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
+
+# QSFP_0_TX
+set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
+set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
+set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
+set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
+
+
+# QSFP_1_RX
+set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[3]
+
+
+#
+# QSFP_1_TX
+set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[3]
+
+
+
+
+# QSFP_2_RX
+set_location_assignment PIN_AL38 -to QSFP_2_RX[0]
+set_location_assignment PIN_AH40 -to QSFP_2_RX[1]
+set_location_assignment PIN_AE38 -to QSFP_2_RX[2]
+set_location_assignment PIN_AB40 -to QSFP_2_RX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[3]
+
+
+
+# QSFP_2_TX
+set_location_assignment PIN_AL42 -to QSFP_2_TX[0]
+set_location_assignment PIN_AH44 -to QSFP_2_TX[1]
+set_location_assignment PIN_AE42 -to QSFP_2_TX[2]
+set_location_assignment PIN_AB44 -to QSFP_2_TX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_2_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[3]
+
+
+
+# QSFP_3_RX
+set_location_assignment PIN_W38 -to QSFP_3_RX[0]
+set_location_assignment PIN_T40 -to QSFP_3_RX[1]
+set_location_assignment PIN_N38 -to QSFP_3_RX[2]
+set_location_assignment PIN_K40 -to QSFP_3_RX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[3]
+
+
+# QSFP_3_TX
+set_location_assignment PIN_W42 -to QSFP_3_TX[0]
+set_location_assignment PIN_T44 -to QSFP_3_TX[1]
+set_location_assignment PIN_N42 -to QSFP_3_TX[2]
+set_location_assignment PIN_K44 -to QSFP_3_TX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_3_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[3]
+
+
+# QSFP_4_RX
+set_location_assignment PIN_AA38 -to QSFP_4_RX[0]
+set_location_assignment PIN_Y40 -to QSFP_4_RX[1]
+set_location_assignment PIN_V40 -to QSFP_4_RX[2]
+set_location_assignment PIN_U38 -to QSFP_4_RX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[3]
+
+
+# QSFP_4_TX
+set_location_assignment PIN_AA42 -to QSFP_4_TX[0]
+set_location_assignment PIN_Y44 -to QSFP_4_TX[1]
+set_location_assignment PIN_V44 -to QSFP_4_TX[2]
+set_location_assignment PIN_U42 -to QSFP_4_TX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_4_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[3]
+
+
+# QSFP_5_RX
+set_location_assignment PIN_L38 -to QSFP_5_RX[0]
+set_location_assignment PIN_M40 -to QSFP_5_RX[1]
+set_location_assignment PIN_P40 -to QSFP_5_RX[2]
+set_location_assignment PIN_R38 -to QSFP_5_RX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[3]
+
+
+
+# QSFP_5_TX
+set_location_assignment PIN_L42 -to QSFP_5_TX[0]
+set_location_assignment PIN_M44 -to QSFP_5_TX[1]
+set_location_assignment PIN_P44 -to QSFP_5_TX[2]
+set_location_assignment PIN_R42 -to QSFP_5_TX[3]
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_5_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[3]
+
+
+
+
+
+
+set_location_assignment PIN_B9 -to BCK_RX[0]
+set_location_assignment PIN_D9 -to BCK_RX[1]
+set_location_assignment PIN_C11 -to BCK_RX[2]
+set_location_assignment PIN_F9 -to BCK_RX[3]
+set_location_assignment PIN_C7 -to BCK_RX[4]
+set_location_assignment PIN_E11 -to BCK_RX[5]
+set_location_assignment PIN_E7 -to BCK_RX[6]
+set_location_assignment PIN_D5 -to BCK_RX[7]
+set_location_assignment PIN_G7 -to BCK_RX[8]
+set_location_assignment PIN_F5 -to BCK_RX[9]
+set_location_assignment PIN_J7 -to BCK_RX[10]
+set_location_assignment PIN_H5 -to BCK_RX[11]
+set_location_assignment PIN_L7 -to BCK_RX[12]
+set_location_assignment PIN_K5 -to BCK_RX[13]
+set_location_assignment PIN_N7 -to BCK_RX[14]
+set_location_assignment PIN_M5 -to BCK_RX[15]
+set_location_assignment PIN_R7 -to BCK_RX[16]
+set_location_assignment PIN_P5 -to BCK_RX[17]
+set_location_assignment PIN_U7 -to BCK_RX[18]
+set_location_assignment PIN_T5 -to BCK_RX[19]
+set_location_assignment PIN_W7 -to BCK_RX[20]
+set_location_assignment PIN_V5 -to BCK_RX[21]
+set_location_assignment PIN_AA7 -to BCK_RX[22]
+set_location_assignment PIN_Y5 -to BCK_RX[23]
+set_location_assignment PIN_AC7 -to BCK_RX[24]
+set_location_assignment PIN_AB5 -to BCK_RX[25]
+set_location_assignment PIN_AE7 -to BCK_RX[26]
+set_location_assignment PIN_AD5 -to BCK_RX[27]
+set_location_assignment PIN_AG7 -to BCK_RX[28]
+set_location_assignment PIN_AF5 -to BCK_RX[29]
+set_location_assignment PIN_AJ7 -to BCK_RX[30]
+set_location_assignment PIN_AH5 -to BCK_RX[31]
+set_location_assignment PIN_AL7 -to BCK_RX[32]
+set_location_assignment PIN_AK5 -to BCK_RX[33]
+set_location_assignment PIN_AN7 -to BCK_RX[34]
+set_location_assignment PIN_AM5 -to BCK_RX[35]
+set_location_assignment PIN_AR7 -to BCK_RX[36]
+set_location_assignment PIN_AP5 -to BCK_RX[37]
+set_location_assignment PIN_AU7 -to BCK_RX[38]
+set_location_assignment PIN_AT5 -to BCK_RX[39]
+set_location_assignment PIN_AW7 -to BCK_RX[40]
+set_location_assignment PIN_AV5 -to BCK_RX[41]
+set_location_assignment PIN_BA7 -to BCK_RX[42]
+set_location_assignment PIN_AY5 -to BCK_RX[43]
+set_location_assignment PIN_BC7 -to BCK_RX[44]
+set_location_assignment PIN_BB5 -to BCK_RX[45]
+set_location_assignment PIN_AY9 -to BCK_RX[46]
+set_location_assignment PIN_BB9 -to BCK_RX[47]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[11]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[12]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[12]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[12]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[13]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[13]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[13]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[14]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[14]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[14]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[15]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[15]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[15]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[16]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[16]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[16]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[17]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[17]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[17]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[18]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[18]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[18]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[19]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[19]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[19]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[20]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[20]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[20]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[21]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[21]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[21]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[22]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[22]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[22]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[23]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[23]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[23]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[24]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[24]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[24]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[25]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[25]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[25]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[26]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[26]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[26]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[27]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[27]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[27]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[28]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[28]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[28]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[29]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[29]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[29]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[30]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[30]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[30]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[31]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[31]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[31]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[32]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[32]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[32]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[33]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[33]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[33]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[34]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[34]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[34]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[35]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[35]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[35]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[36]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[36]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[36]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[37]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[37]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[37]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[38]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[38]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[38]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[39]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[39]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[39]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[40]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[40]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[40]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[41]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[41]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[41]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[42]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[42]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[42]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[43]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[43]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[43]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[44]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[44]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[44]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[45]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[45]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[45]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[46]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[46]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[46]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[47]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[47]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[47]
+
+
+
+
+set_location_assignment PIN_B5 -to BCK_TX[0]
+set_location_assignment PIN_A3 -to BCK_TX[1]
+set_location_assignment PIN_A11 -to BCK_TX[2]
+set_location_assignment PIN_B1 -to BCK_TX[3]
+set_location_assignment PIN_C3 -to BCK_TX[4]
+set_location_assignment PIN_A7 -to BCK_TX[5]
+set_location_assignment PIN_D1 -to BCK_TX[6]
+set_location_assignment PIN_E3 -to BCK_TX[7]
+set_location_assignment PIN_F1 -to BCK_TX[8]
+set_location_assignment PIN_G3 -to BCK_TX[9]
+set_location_assignment PIN_J3 -to BCK_TX[10]
+set_location_assignment PIN_H1 -to BCK_TX[11]
+set_location_assignment PIN_L3 -to BCK_TX[12]
+set_location_assignment PIN_K1 -to BCK_TX[13]
+set_location_assignment PIN_N3 -to BCK_TX[14]
+set_location_assignment PIN_M1 -to BCK_TX[15]
+set_location_assignment PIN_R3 -to BCK_TX[16]
+set_location_assignment PIN_P1 -to BCK_TX[17]
+set_location_assignment PIN_U3 -to BCK_TX[18]
+set_location_assignment PIN_T1 -to BCK_TX[19]
+set_location_assignment PIN_W3 -to BCK_TX[20]
+set_location_assignment PIN_V1 -to BCK_TX[21]
+set_location_assignment PIN_AA3 -to BCK_TX[22]
+set_location_assignment PIN_Y1 -to BCK_TX[23]
+set_location_assignment PIN_AC3 -to BCK_TX[24]
+set_location_assignment PIN_AB1 -to BCK_TX[25]
+set_location_assignment PIN_AE3 -to BCK_TX[26]
+set_location_assignment PIN_AD1 -to BCK_TX[27]
+set_location_assignment PIN_AG3 -to BCK_TX[28]
+set_location_assignment PIN_AF1 -to BCK_TX[29]
+set_location_assignment PIN_AJ3 -to BCK_TX[30]
+set_location_assignment PIN_AH1 -to BCK_TX[31]
+set_location_assignment PIN_AL3 -to BCK_TX[32]
+set_location_assignment PIN_AK1 -to BCK_TX[33]
+set_location_assignment PIN_AN3 -to BCK_TX[34]
+set_location_assignment PIN_AM1 -to BCK_TX[35]
+set_location_assignment PIN_AR3 -to BCK_TX[36]
+set_location_assignment PIN_AP1 -to BCK_TX[37]
+set_location_assignment PIN_AU3 -to BCK_TX[38]
+set_location_assignment PIN_AT1 -to BCK_TX[39]
+set_location_assignment PIN_AW3 -to BCK_TX[40]
+set_location_assignment PIN_AV1 -to BCK_TX[41]
+set_location_assignment PIN_BB1 -to BCK_TX[42]
+set_location_assignment PIN_AY1 -to BCK_TX[43]
+set_location_assignment PIN_BD5 -to BCK_TX[44]
+set_location_assignment PIN_BA3 -to BCK_TX[45]
+set_location_assignment PIN_BC3 -to BCK_TX[46]
+set_location_assignment PIN_BD9 -to BCK_TX[47]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[12]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[13]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[13]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[14]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[14]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[15]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[15]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[16]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[16]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[17]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[17]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[18]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[18]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[19]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[19]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[20]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[20]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[21]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[21]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[22]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[22]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[23]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[24]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[24]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[25]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[25]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[26]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[26]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[27]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[27]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[28]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[28]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[29]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[29]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[30]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[30]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[31]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[31]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[32]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[32]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[33]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[33]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[34]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[34]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[35]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[35]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[36]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[36]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[37]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[37]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[38]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[38]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[39]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[39]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[40]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[40]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[41]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[41]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[42]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[42]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[43]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[43]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[44]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[44]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[45]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[45]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[46]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[46]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[47]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[47]
+
+
+
+
+
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+
+set_location_assignment PIN_AV40 -to RING_0_RX[4]
+set_location_assignment PIN_AW38 -to RING_0_RX[5]
+set_location_assignment PIN_AY40 -to RING_0_RX[6]
+set_location_assignment PIN_BA38 -to RING_0_RX[7]
+set_location_assignment PIN_BB40 -to RING_0_RX[8]
+set_location_assignment PIN_BC38 -to RING_0_RX[9]
+set_location_assignment PIN_AY36 -to RING_0_RX[10]
+set_location_assignment PIN_BB36 -to RING_0_RX[11]
+set_location_assignment PIN_AV44 -to RING_0_TX[4]
+set_location_assignment PIN_AW42 -to RING_0_TX[5]
+set_location_assignment PIN_AY44 -to RING_0_TX[6]
+set_location_assignment PIN_BB44 -to RING_0_TX[7]
+set_location_assignment PIN_BA42 -to RING_0_TX[8]
+set_location_assignment PIN_BD40 -to RING_0_TX[9]
+set_location_assignment PIN_BC42 -to RING_0_TX[10]
+set_location_assignment PIN_BD36 -to RING_0_TX[11]
+set_location_assignment PIN_D40 -to RING_1_RX[4]
+set_location_assignment PIN_E38 -to RING_1_RX[5]
+set_location_assignment PIN_F36 -to RING_1_RX[6]
+set_location_assignment PIN_C38 -to RING_1_RX[7]
+set_location_assignment PIN_B36 -to RING_1_RX[8]
+set_location_assignment PIN_D36 -to RING_1_RX[9]
+set_location_assignment PIN_E34 -to RING_1_RX[10]
+set_location_assignment PIN_C34 -to RING_1_RX[11]
+set_location_assignment PIN_E42 -to RING_1_TX[4]
+set_location_assignment PIN_D44 -to RING_1_TX[5]
+set_location_assignment PIN_B44 -to RING_1_TX[6]
+set_location_assignment PIN_C42 -to RING_1_TX[7]
+set_location_assignment PIN_B40 -to RING_1_TX[8]
+set_location_assignment PIN_A42 -to RING_1_TX[9]
+set_location_assignment PIN_A38 -to RING_1_TX[10]
+set_location_assignment PIN_A34 -to RING_1_TX[11]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[11]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[11]
+
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[4]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[4]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[5]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[5]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[6]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[6]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[7]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[7]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[8]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[8]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[9]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[9]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[10]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[10]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[11]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[11]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[11]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[4]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[4]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[5]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[5]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[6]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[6]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[7]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[7]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[8]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[8]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[9]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[9]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[10]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[10]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[11]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[11]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[11]
+
+
+
+#set_location_assignment PIN_BA25 -to PMBUS_SC
+#set_location_assignment PIN_BD25 -to PMBUS_SD
+#set_location_assignment PIN_BD26 -to PMBUS_ALERT
+#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
+#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
+#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
+
+
+
+
+set_location_assignment PIN_R14 -to BCK_SCL[0]
+set_location_assignment PIN_Y13 -to BCK_SCL[1]
+set_location_assignment PIN_U14 -to BCK_SCL[2]
+set_location_assignment PIN_P14 -to BCK_SDA[0]
+set_location_assignment PIN_T12 -to BCK_SDA[1]
+set_location_assignment PIN_V12 -to BCK_SDA[2]
+
+set_location_assignment PIN_AT31 -to QSFP_RST
+
+set_location_assignment PIN_AY33 -to QSFP_SCL[0]
+set_location_assignment PIN_AY32 -to QSFP_SCL[1]
+set_location_assignment PIN_AY30 -to QSFP_SCL[2]
+set_location_assignment PIN_AN33 -to QSFP_SCL[3]
+set_location_assignment PIN_AN31 -to QSFP_SCL[4]
+set_location_assignment PIN_AJ33 -to QSFP_SCL[5]
+set_location_assignment PIN_BA32 -to QSFP_SDA[0]
+set_location_assignment PIN_BA31 -to QSFP_SDA[1]
+set_location_assignment PIN_AP33 -to QSFP_SDA[2]
+set_location_assignment PIN_AM33 -to QSFP_SDA[3]
+set_location_assignment PIN_AK33 -to QSFP_SDA[4]
+set_location_assignment PIN_AH32 -to QSFP_SDA[5]
+set_location_assignment PIN_M13 -to BCK_ERR[0]
+set_location_assignment PIN_R13 -to BCK_ERR[1]
+set_location_assignment PIN_U12 -to BCK_ERR[2]
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[2]
+
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
new file mode 100644
index 0000000000..cef7b78587
--- /dev/null
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
@@ -0,0 +1,561 @@
+# module I:
+set_location_assignment PIN_AP20 -to MB_I_OU.a[0]
+set_location_assignment PIN_AR20 -to MB_I_OU.a[1]
+set_location_assignment PIN_AP19 -to MB_I_OU.a[2]
+set_location_assignment PIN_AR19 -to MB_I_OU.a[3]
+set_location_assignment PIN_AR18 -to MB_I_OU.a[4]
+set_location_assignment PIN_AT17 -to MB_I_OU.a[5]
+set_location_assignment PIN_AU19 -to MB_I_OU.a[6]
+set_location_assignment PIN_AT18 -to MB_I_OU.a[7]
+set_location_assignment PIN_AL17 -to MB_I_OU.a[8]
+set_location_assignment PIN_AM18 -to MB_I_OU.a[9]
+set_location_assignment PIN_AM19 -to MB_I_OU.a[10]
+set_location_assignment PIN_AN19 -to MB_I_OU.a[11]
+set_location_assignment PIN_BA17 -to MB_I_OU.a[12]
+set_location_assignment PIN_BD17 -to MB_I_OU.a[13]
+set_location_assignment PIN_AY18 -to MB_I_OU.act_n
+set_location_assignment PIN_AV29 -to MB_I_IN.alert_n
+set_location_assignment PIN_BB16 -to MB_I_OU.ba[0]
+set_location_assignment PIN_BD16 -to MB_I_OU.ba[1]
+set_location_assignment PIN_BC16 -to MB_I_OU.bg[0]
+set_location_assignment PIN_AW19 -to MB_I_OU.bg[1]
+set_location_assignment PIN_BA15 -to MB_I_OU.a[15]
+set_location_assignment PIN_BC21 -to MB_I_IO.dq[64]
+set_location_assignment PIN_BA22 -to MB_I_IO.dq[65]
+set_location_assignment PIN_BD21 -to MB_I_IO.dq[66]
+set_location_assignment PIN_BB20 -to MB_I_IO.dq[67]
+set_location_assignment PIN_BA20 -to MB_I_IO.dq[68]
+set_location_assignment PIN_BD20 -to MB_I_IO.dq[69]
+set_location_assignment PIN_AY20 -to MB_I_IO.dq[70]
+set_location_assignment PIN_AY22 -to MB_I_IO.dq[71]
+set_location_assignment PIN_AU18 -to MB_I_OU.ck[0]
+#set_location_assignment PIN_AV18 -to MB_I_OU.ck_n[0]
+set_location_assignment PIN_AT16 -to MB_I_OU.ck[1]
+#set_location_assignment PIN_AU16 -to MB_I_OU.ck_n[1]
+set_location_assignment PIN_BB19 -to MB_I_OU.cke[0]
+set_location_assignment PIN_AP16 -to MB_I_OU.cke[1]
+set_location_assignment PIN_AY19 -to MB_I_OU.cs_n[0]
+set_location_assignment PIN_AN16 -to MB_I_OU.cs_n[1]
+set_location_assignment PIN_BC29 -to MB_I_IO.dbi_n[0]
+set_location_assignment PIN_AR27 -to MB_I_IO.dbi_n[1]
+set_location_assignment PIN_BD24 -to MB_I_IO.dbi_n[2]
+set_location_assignment PIN_AM23 -to MB_I_IO.dbi_n[3]
+set_location_assignment PIN_AU12 -to MB_I_IO.dbi_n[4]
+set_location_assignment PIN_AU13 -to MB_I_IO.dbi_n[5]
+set_location_assignment PIN_AM14 -to MB_I_IO.dbi_n[6]
+set_location_assignment PIN_AM16 -to MB_I_IO.dbi_n[7]
+set_location_assignment PIN_BA21 -to MB_I_IO.dbi_n[8]
+set_location_assignment PIN_BA28 -to MB_I_IO.dqs[0]
+set_location_assignment PIN_AM28 -to MB_I_IO.dqs[1]
+set_location_assignment PIN_AV24 -to MB_I_IO.dqs[2]
+set_location_assignment PIN_AN24 -to MB_I_IO.dqs[3]
+set_location_assignment PIN_BC14 -to MB_I_IO.dqs[4]
+set_location_assignment PIN_AW14 -to MB_I_IO.dqs[5]
+set_location_assignment PIN_AN12 -to MB_I_IO.dqs[6]
+set_location_assignment PIN_AK15 -to MB_I_IO.dqs[7]
+set_location_assignment PIN_BC22 -to MB_I_IO.dqs[8]
+
+set_location_assignment PIN_BD19 -to MB_I_OU.odt[0]
+set_location_assignment PIN_AR17 -to MB_I_OU.odt[1]
+set_location_assignment PIN_BC18 -to MB_I_OU.par
+set_location_assignment PIN_BB15 -to MB_I_OU.a[16]
+
+set_location_assignment PIN_AW17 -to MB_I_REF_CLK
+
+set_location_assignment PIN_AV19 -to MB_I_OU.reset_n
+set_location_assignment PIN_AY17 -to MB_I_IN.oct_rzqin
+set_location_assignment PIN_BC17 -to MB_I_OU.a[14]
+
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cke[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.odt[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_REF_CLK
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.oct_rzqin
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[2]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[3]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[4]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[5]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[6]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[7]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[8]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[9]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[10]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[11]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[12]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[13]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.act_n
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.ba[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.ba[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.bg[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.bg[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cke[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.par
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[16]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_OU.reset_n
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[14]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.odt[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.alert_n
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[8]
+
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[8]
+
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[63]
+
+# locations changed 30 sept
+set_location_assignment PIN_Y12 -to MB_SCL
+set_location_assignment PIN_AA12 -to MB_SDA
+set_location_assignment PIN_M16 -to MB_I_IN.evt
+
+
+set_location_assignment PIN_AU29 -to MB_I_IO.dq[0]
+set_location_assignment PIN_BC28 -to MB_I_IO.dq[1]
+set_location_assignment PIN_AY29 -to MB_I_IO.dq[2]
+set_location_assignment PIN_BB28 -to MB_I_IO.dq[3]
+set_location_assignment PIN_BB29 -to MB_I_IO.dq[4]
+set_location_assignment PIN_AW29 -to MB_I_IO.dq[5]
+set_location_assignment PIN_BC27 -to MB_I_IO.dq[6]
+set_location_assignment PIN_BD29 -to MB_I_IO.dq[7]
+set_location_assignment PIN_AR28 -to MB_I_IO.dq[8]
+set_location_assignment PIN_AR29 -to MB_I_IO.dq[9]
+set_location_assignment PIN_AV27 -to MB_I_IO.dq[10]
+set_location_assignment PIN_AU28 -to MB_I_IO.dq[11]
+set_location_assignment PIN_AW27 -to MB_I_IO.dq[12]
+set_location_assignment PIN_AT28 -to MB_I_IO.dq[13]
+set_location_assignment PIN_AV28 -to MB_I_IO.dq[14]
+set_location_assignment PIN_AP27 -to MB_I_IO.dq[15]
+set_location_assignment PIN_BC24 -to MB_I_IO.dq[16]
+set_location_assignment PIN_BB24 -to MB_I_IO.dq[17]
+set_location_assignment PIN_BB23 -to MB_I_IO.dq[18]
+set_location_assignment PIN_AW22 -to MB_I_IO.dq[19]
+set_location_assignment PIN_BA23 -to MB_I_IO.dq[20]
+set_location_assignment PIN_BC23 -to MB_I_IO.dq[21]
+set_location_assignment PIN_AY23 -to MB_I_IO.dq[22]
+set_location_assignment PIN_AY24 -to MB_I_IO.dq[23]
+set_location_assignment PIN_AP22 -to MB_I_IO.dq[24]
+set_location_assignment PIN_AN23 -to MB_I_IO.dq[25]
+set_location_assignment PIN_AR23 -to MB_I_IO.dq[26]
+set_location_assignment PIN_AT23 -to MB_I_IO.dq[27]
+set_location_assignment PIN_AU23 -to MB_I_IO.dq[28]
+set_location_assignment PIN_AV23 -to MB_I_IO.dq[29]
+set_location_assignment PIN_AR24 -to MB_I_IO.dq[30]
+set_location_assignment PIN_AP24 -to MB_I_IO.dq[31]
+set_location_assignment PIN_AV12 -to MB_I_IO.dq[32]
+set_location_assignment PIN_AY13 -to MB_I_IO.dq[33]
+set_location_assignment PIN_BD14 -to MB_I_IO.dq[34]
+set_location_assignment PIN_AY12 -to MB_I_IO.dq[35]
+set_location_assignment PIN_BA13 -to MB_I_IO.dq[36]
+set_location_assignment PIN_BA12 -to MB_I_IO.dq[37]
+set_location_assignment PIN_AW12 -to MB_I_IO.dq[38]
+set_location_assignment PIN_BB13 -to MB_I_IO.dq[39]
+set_location_assignment PIN_AV13 -to MB_I_IO.dq[40]
+set_location_assignment PIN_AR13 -to MB_I_IO.dq[41]
+set_location_assignment PIN_AR15 -to MB_I_IO.dq[42]
+set_location_assignment PIN_AP15 -to MB_I_IO.dq[43]
+set_location_assignment PIN_AT15 -to MB_I_IO.dq[44]
+set_location_assignment PIN_AU14 -to MB_I_IO.dq[45]
+set_location_assignment PIN_AU15 -to MB_I_IO.dq[46]
+set_location_assignment PIN_AV14 -to MB_I_IO.dq[47]
+set_location_assignment PIN_AM13 -to MB_I_IO.dq[48]
+set_location_assignment PIN_AT13 -to MB_I_IO.dq[49]
+set_location_assignment PIN_AT12 -to MB_I_IO.dq[50]
+set_location_assignment PIN_AP14 -to MB_I_IO.dq[51]
+set_location_assignment PIN_AN13 -to MB_I_IO.dq[52]
+set_location_assignment PIN_AK13 -to MB_I_IO.dq[53]
+set_location_assignment PIN_AM12 -to MB_I_IO.dq[54]
+set_location_assignment PIN_AL13 -to MB_I_IO.dq[55]
+set_location_assignment PIN_AH13 -to MB_I_IO.dq[56]
+set_location_assignment PIN_AL15 -to MB_I_IO.dq[57]
+set_location_assignment PIN_AM15 -to MB_I_IO.dq[58]
+set_location_assignment PIN_AJ14 -to MB_I_IO.dq[59]
+set_location_assignment PIN_AJ12 -to MB_I_IO.dq[60]
+set_location_assignment PIN_AL16 -to MB_I_IO.dq[61]
+set_location_assignment PIN_AK12 -to MB_I_IO.dq[62]
+set_location_assignment PIN_AH14 -to MB_I_IO.dq[63]
+set_location_assignment PIN_AY28 -to MB_I_IO.dqs_n[0]
+set_location_assignment PIN_AN28 -to MB_I_IO.dqs_n[1]
+set_location_assignment PIN_AU24 -to MB_I_IO.dqs_n[2]
+set_location_assignment PIN_AM24 -to MB_I_IO.dqs_n[3]
+set_location_assignment PIN_BB14 -to MB_I_IO.dqs_n[4]
+set_location_assignment PIN_AY14 -to MB_I_IO.dqs_n[5]
+set_location_assignment PIN_AP12 -to MB_I_IO.dqs_n[6]
+set_location_assignment PIN_AK14 -to MB_I_IO.dqs_n[7]
+set_location_assignment PIN_BD22 -to MB_I_IO.dqs_n[8]
+
+
+
+
+
+# module II:
+set_location_assignment PIN_A29 -to MB_II_OU.a[0]
+set_location_assignment PIN_B29 -to MB_II_OU.a[1]
+set_location_assignment PIN_H29 -to MB_II_OU.a[2]
+set_location_assignment PIN_G29 -to MB_II_OU.a[3]
+set_location_assignment PIN_D29 -to MB_II_OU.a[4]
+set_location_assignment PIN_E29 -to MB_II_OU.a[5]
+set_location_assignment PIN_C29 -to MB_II_OU.a[6]
+set_location_assignment PIN_C28 -to MB_II_OU.a[7]
+set_location_assignment PIN_E30 -to MB_II_OU.a[8]
+set_location_assignment PIN_D30 -to MB_II_OU.a[9]
+set_location_assignment PIN_B28 -to MB_II_OU.a[10]
+set_location_assignment PIN_A28 -to MB_II_OU.a[11]
+set_location_assignment PIN_H27 -to MB_II_OU.a[12]
+set_location_assignment PIN_E28 -to MB_II_OU.a[13]
+set_location_assignment PIN_K28 -to MB_II_OU.act_n
+set_location_assignment PIN_C16 -to MB_II_IN.alert_n
+set_location_assignment PIN_C27 -to MB_II_OU.ba[0]
+set_location_assignment PIN_A27 -to MB_II_OU.ba[1]
+set_location_assignment PIN_B26 -to MB_II_OU.bg[0]
+set_location_assignment PIN_L27 -to MB_II_OU.bg[1]
+set_location_assignment PIN_F28 -to MB_II_OU.a[15]
+set_location_assignment PIN_E24 -to MB_II_IO.dq[64]
+set_location_assignment PIN_J25 -to MB_II_IO.dq[65]
+set_location_assignment PIN_A25 -to MB_II_IO.dq[66]
+set_location_assignment PIN_G25 -to MB_II_IO.dq[67]
+set_location_assignment PIN_D25 -to MB_II_IO.dq[68]
+set_location_assignment PIN_K25 -to MB_II_IO.dq[69]
+set_location_assignment PIN_D24 -to MB_II_IO.dq[70]
+set_location_assignment PIN_F25 -to MB_II_IO.dq[71]
+set_location_assignment PIN_N27 -to MB_II_OU.ck[0]
+#set_location_assignment PIN_M28 -to MB_II_OU.ck_n[0] ;#
+set_location_assignment PIN_K27 -to MB_II_OU.ck[1]
+#set_location_assignment PIN_J26 -to MB_II_OU.ck_n[1] ;#
+set_location_assignment PIN_N28 -to MB_II_OU.cke[0]
+set_location_assignment PIN_P26 -to MB_II_OU.cke[1]
+set_location_assignment PIN_K29 -to MB_II_OU.cs_n[0]
+set_location_assignment PIN_H26 -to MB_II_OU.cs_n[1]
+set_location_assignment PIN_A16 -to MB_II_IO.dbi_n[0]
+set_location_assignment PIN_M21 -to MB_II_IO.dbi_n[1]
+set_location_assignment PIN_K22 -to MB_II_IO.dbi_n[2]
+set_location_assignment PIN_D19 -to MB_II_IO.dbi_n[3]
+set_location_assignment PIN_G30 -to MB_II_IO.dbi_n[4]
+set_location_assignment PIN_R32 -to MB_II_IO.dbi_n[5]
+set_location_assignment PIN_G32 -to MB_II_IO.dbi_n[6]
+set_location_assignment PIN_AC32 -to MB_II_IO.dbi_n[7]
+set_location_assignment PIN_E25 -to MB_II_IO.dbi_n[8]
+set_location_assignment PIN_F17 -to MB_II_IO.dqs[0]
+set_location_assignment PIN_L20 -to MB_II_IO.dqs[1]
+set_location_assignment PIN_J22 -to MB_II_IO.dqs[2]
+set_location_assignment PIN_B19 -to MB_II_IO.dqs[3]
+set_location_assignment PIN_L31 -to MB_II_IO.dqs[4]
+set_location_assignment PIN_P31 -to MB_II_IO.dqs[5]
+set_location_assignment PIN_N33 -to MB_II_IO.dqs[6]
+set_location_assignment PIN_T33 -to MB_II_IO.dqs[7]
+set_location_assignment PIN_A26 -to MB_II_IO.dqs[8]
+
+set_location_assignment PIN_K30 -to MB_II_OU.odt[0]
+set_location_assignment PIN_R27 -to MB_II_OU.odt[1]
+set_location_assignment PIN_R28 -to MB_II_OU.par
+set_location_assignment PIN_G28 -to MB_II_OU.a[16]
+
+set_location_assignment PIN_J29 -to MB_II_REF_CLK
+
+set_location_assignment PIN_L28 -to MB_II_OU.reset_n
+set_location_assignment PIN_J27 -to MB_II_IN.oct_rzqin
+set_location_assignment PIN_F27 -to MB_II_OU.a[14]
+
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cke[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.odt[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_REF_CLK ;#
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IN.oct_rzqin ;#
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[2]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[3]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[4]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[5]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[6]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[7]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[8]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[9]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[10]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[11]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[12]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[13]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.act_n
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.ba[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.ba[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.bg[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.bg[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cke[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.par
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[16]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_OU.reset_n ;#
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[14]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.odt[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IN.alert_n ;#
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[8]
+
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[8]
+
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[63]
+
+
+
+
+set_location_assignment PIN_A17 -to MB_II_IO.dq[0]
+set_location_assignment PIN_B16 -to MB_II_IO.dq[1]
+set_location_assignment PIN_D16 -to MB_II_IO.dq[2]
+set_location_assignment PIN_A18 -to MB_II_IO.dq[3]
+set_location_assignment PIN_B18 -to MB_II_IO.dq[4]
+set_location_assignment PIN_C17 -to MB_II_IO.dq[5]
+set_location_assignment PIN_E18 -to MB_II_IO.dq[6]
+set_location_assignment PIN_F18 -to MB_II_IO.dq[7]
+set_location_assignment PIN_R22 -to MB_II_IO.dq[8]
+set_location_assignment PIN_J20 -to MB_II_IO.dq[9]
+set_location_assignment PIN_L21 -to MB_II_IO.dq[10]
+set_location_assignment PIN_M20 -to MB_II_IO.dq[11]
+set_location_assignment PIN_J21 -to MB_II_IO.dq[12]
+set_location_assignment PIN_P21 -to MB_II_IO.dq[13]
+set_location_assignment PIN_R20 -to MB_II_IO.dq[14]
+set_location_assignment PIN_N21 -to MB_II_IO.dq[15]
+set_location_assignment PIN_L22 -to MB_II_IO.dq[16]
+set_location_assignment PIN_G20 -to MB_II_IO.dq[17]
+set_location_assignment PIN_H21 -to MB_II_IO.dq[18]
+set_location_assignment PIN_N22 -to MB_II_IO.dq[19]
+set_location_assignment PIN_P22 -to MB_II_IO.dq[20]
+set_location_assignment PIN_F20 -to MB_II_IO.dq[21]
+set_location_assignment PIN_G21 -to MB_II_IO.dq[22]
+set_location_assignment PIN_F21 -to MB_II_IO.dq[23]
+set_location_assignment PIN_E19 -to MB_II_IO.dq[24]
+set_location_assignment PIN_B20 -to MB_II_IO.dq[25]
+set_location_assignment PIN_A20 -to MB_II_IO.dq[26]
+set_location_assignment PIN_G19 -to MB_II_IO.dq[27]
+set_location_assignment PIN_D20 -to MB_II_IO.dq[28]
+set_location_assignment PIN_E20 -to MB_II_IO.dq[29]
+set_location_assignment PIN_D17 -to MB_II_IO.dq[30]
+set_location_assignment PIN_C18 -to MB_II_IO.dq[31]
+set_location_assignment PIN_F30 -to MB_II_IO.dq[32]
+set_location_assignment PIN_L30 -to MB_II_IO.dq[33]
+set_location_assignment PIN_M30 -to MB_II_IO.dq[34]
+set_location_assignment PIN_C31 -to MB_II_IO.dq[35]
+set_location_assignment PIN_D31 -to MB_II_IO.dq[36]
+set_location_assignment PIN_H31 -to MB_II_IO.dq[37]
+set_location_assignment PIN_J31 -to MB_II_IO.dq[38]
+set_location_assignment PIN_F31 -to MB_II_IO.dq[39]
+set_location_assignment PIN_P32 -to MB_II_IO.dq[40]
+set_location_assignment PIN_R30 -to MB_II_IO.dq[41]
+set_location_assignment PIN_U31 -to MB_II_IO.dq[42]
+set_location_assignment PIN_W31 -to MB_II_IO.dq[43]
+set_location_assignment PIN_P29 -to MB_II_IO.dq[44]
+set_location_assignment PIN_P30 -to MB_II_IO.dq[45]
+set_location_assignment PIN_V31 -to MB_II_IO.dq[46]
+set_location_assignment PIN_R29 -to MB_II_IO.dq[47]
+set_location_assignment PIN_M33 -to MB_II_IO.dq[48]
+set_location_assignment PIN_J33 -to MB_II_IO.dq[49]
+set_location_assignment PIN_H33 -to MB_II_IO.dq[50]
+set_location_assignment PIN_H32 -to MB_II_IO.dq[51]
+set_location_assignment PIN_J32 -to MB_II_IO.dq[52]
+set_location_assignment PIN_K33 -to MB_II_IO.dq[53]
+set_location_assignment PIN_K32 -to MB_II_IO.dq[54]
+set_location_assignment PIN_L32 -to MB_II_IO.dq[55]
+set_location_assignment PIN_AB33 -to MB_II_IO.dq[56]
+set_location_assignment PIN_AA32 -to MB_II_IO.dq[57]
+set_location_assignment PIN_W32 -to MB_II_IO.dq[58]
+set_location_assignment PIN_U33 -to MB_II_IO.dq[59]
+set_location_assignment PIN_Y33 -to MB_II_IO.dq[60]
+set_location_assignment PIN_AA33 -to MB_II_IO.dq[61]
+set_location_assignment PIN_V33 -to MB_II_IO.dq[62]
+set_location_assignment PIN_Y32 -to MB_II_IO.dq[63]
+set_location_assignment PIN_E17 -to MB_II_IO.dqs_n[0]
+set_location_assignment PIN_K20 -to MB_II_IO.dqs_n[1]
+set_location_assignment PIN_H22 -to MB_II_IO.dqs_n[2]
+set_location_assignment PIN_C19 -to MB_II_IO.dqs_n[3]
+set_location_assignment PIN_M31 -to MB_II_IO.dqs_n[4]
+set_location_assignment PIN_N31 -to MB_II_IO.dqs_n[5]
+set_location_assignment PIN_P33 -to MB_II_IO.dqs_n[6]
+set_location_assignment PIN_T32 -to MB_II_IO.dqs_n[7]
+set_location_assignment PIN_B25 -to MB_II_IO.dqs_n[8]
+
+
+
+
+
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
new file mode 100644
index 0000000000..f554b7b6e3
--- /dev/null
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
@@ -0,0 +1,327 @@
+
+set_location_assignment PIN_K15 -to CLK
+set_location_assignment PIN_J15 -to "CLK(n)"
+set_location_assignment PIN_N12 -to ETH_CLK
+set_location_assignment PIN_K14 -to PPS
+set_location_assignment PIN_J14 -to "PPS(n)"
+
+# enable 100 ohm termination:
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to CLK
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to PPS
+
+#set_location_assignment PIN_AT33 -to CFG_DATA[0]
+#set_location_assignment PIN_AT32 -to CFG_DATA[1]
+#set_location_assignment PIN_BB33 -to CFG_DATA[2]
+#set_location_assignment PIN_BA33 -to CFG_DATA[3]
+
+
+
+
+# IO Standard Assignments from Gijs (excluding memory)
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ETH_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[1](n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTA
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTB
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SC
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SD
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to WDI
+
+# locations changed 30 sept
+set_location_assignment PIN_P16 -to ID[0]
+set_location_assignment PIN_P15 -to ID[1]
+set_location_assignment PIN_K13 -to ID[2]
+set_location_assignment PIN_L13 -to ID[3]
+set_location_assignment PIN_N16 -to ID[4]
+set_location_assignment PIN_N14 -to ID[5]
+set_location_assignment PIN_U13 -to ID[6]
+
+set_location_assignment PIN_T13 -to ID[7]
+set_location_assignment PIN_AU31 -to INTA
+set_location_assignment PIN_AR30 -to INTB
+
+set_location_assignment PIN_BC31 -to SENS_SC
+set_location_assignment PIN_BB31 -to SENS_SD
+
+set_location_assignment PIN_BA25 -to PMBUS_SC
+set_location_assignment PIN_BD25 -to PMBUS_SD
+set_location_assignment PIN_BD26 -to PMBUS_ALERT
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
+
+
+set_location_assignment PIN_AN32 -to TESTIO[0]
+set_location_assignment PIN_AP32 -to TESTIO[1]
+set_location_assignment PIN_AT30 -to TESTIO[2]
+set_location_assignment PIN_BD31 -to TESTIO[3]
+set_location_assignment PIN_AU30 -to TESTIO[4]
+set_location_assignment PIN_BD30 -to TESTIO[5]
+
+set_location_assignment PIN_AB12 -to VERSION[0]
+set_location_assignment PIN_AB13 -to VERSION[1]
+set_location_assignment PIN_BB30 -to WDI
+
+set_location_assignment PIN_K12 -to ETH_SGIN[0]
+set_location_assignment PIN_J12 -to "ETH_SGIN[0](n)"
+set_location_assignment PIN_AF33 -to ETH_SGIN[1]
+set_location_assignment PIN_AE33 -to "ETH_SGIN[1](n)"
+set_location_assignment PIN_H13 -to ETH_SGOUT[0]
+set_location_assignment PIN_H12 -to "ETH_SGOUT[0](n)"
+set_location_assignment PIN_AW31 -to ETH_SGOUT[1]
+set_location_assignment PIN_AV31 -to "ETH_SGOUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD LVDS -to PPS
+set_instance_assignment -name IO_STANDARD LVDS -to "PPS(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "CLK(n)"
+
+# Enable internal termination for LVDS inputs
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PPS
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CLK
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ETH_SGIN[0]
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ETH_SGIN[1]
+
+# Enable 100 ohm termination resistors
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to "ETH_SGIN[0](n)"
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to ETH_SGIN[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to ETH_SGIN[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to "ETH_SGIN[1](n)"
+
+set_location_assignment PIN_AG31 -to altera_reserved_tms
+set_location_assignment PIN_AJ31 -to altera_reserved_tck
+set_location_assignment PIN_AK18 -to altera_reserved_tdi
+set_location_assignment PIN_AH31 -to altera_reserved_ntrst
+set_location_assignment PIN_AM29 -to altera_reserved_tdo
+#set_location_assignment PIN_AV33 -to ~ALTERA_DATA0~
+
+
+set_location_assignment PIN_BA33 -to QSFP_LED[0]
+set_location_assignment PIN_BA30 -to QSFP_LED[1]
+set_location_assignment PIN_BB33 -to QSFP_LED[2]
+set_location_assignment PIN_AU33 -to QSFP_LED[3]
+set_location_assignment PIN_AV32 -to QSFP_LED[4]
+set_location_assignment PIN_AW30 -to QSFP_LED[5]
+set_location_assignment PIN_AP31 -to QSFP_LED[6]
+set_location_assignment PIN_AP30 -to QSFP_LED[7]
+set_location_assignment PIN_AT33 -to QSFP_LED[8]
+set_location_assignment PIN_AG32 -to QSFP_LED[9]
+set_location_assignment PIN_AF32 -to QSFP_LED[10]
+set_location_assignment PIN_AE32 -to QSFP_LED[11]
+
+
+
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_0_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_0_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_0_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_0_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_0_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_0_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_0_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_1_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_2_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_3_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_4_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to QSFP_5_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[4]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[5]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[6]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[7]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[8]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[9]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[10]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[11]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[12]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[13]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[14]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[15]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[16]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[17]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[18]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[19]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[20]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[21]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[22]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[23]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[24]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[25]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[26]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[27]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[28]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[29]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[30]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[31]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[32]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[33]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[34]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[35]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[36]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[37]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[38]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[39]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[40]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[41]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[42]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[43]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[44]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[45]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[46]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_RX[47]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[4]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[5]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[6]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[7]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[8]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[9]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[10]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[11]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[12]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[13]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[14]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[15]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[16]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[17]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[18]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[19]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[20]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[21]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[22]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[23]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[24]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[25]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[26]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[27]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[28]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[29]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[30]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[31]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[32]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[33]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[34]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[35]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[36]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[37]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[38]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[39]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[40]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[41]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[42]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[43]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[44]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[45]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[46]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BCK_TX[47]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[0]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[1]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[2]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[3]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[4]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[5]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[6]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[7]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[8]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[9]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[10]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_RX[11]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[4]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[5]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[6]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[7]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[8]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[9]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[10]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_0_TX[11]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[4]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[5]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[6]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[7]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[8]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[9]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[10]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_RX[11]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[4]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[5]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[6]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[7]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[8]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[9]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[10]
+#set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to RING_1_TX[11]
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
index 3b4085e313..94cfb0fe9a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
@@ -311,8 +311,8 @@ set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_1
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
- post_message -type info "RADIOHDL: using GIT $::env(RADIOHDL_GIT_REVISION)"
- set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_GIT_REVISION)] ""]
+ post_message -type info "RADIOHDL: using GIT $::env(HDL_GIT_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(HDL_GIT_REVISION)] ""]
}
#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e1sg:\\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2_board.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2_board_sens.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2_board_system_info.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2_fpga_sens.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_back_io.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk125_pll.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk200_pll.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk25_pll.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_clk_rst.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_front_io.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_hmc_ctrl.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_node_ctrl.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_peripherals_pkg.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_pkg.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_qsfp_leds.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_ring_io.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_sens.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_sens_ctrl.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_sens_reg.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_system_info.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_system_info_reg.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_wdi_extend.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_board_wdi_reg.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_fpga_sens_reg.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2_fpga_sens_reg.vhd
rename to boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_fpga_sens_reg.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
rename to boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
rename to boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
rename to boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
rename to boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
rename to boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
rename to boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/hdllib.cfg b/boards/uniboard2b/libraries/unb2b_board_10gbe/hdllib.cfg
index b0c75a7f6b..2ec3347a47 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/hdllib.cfg
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
- src/vhdl/unb2_board_10gbe.vhd
+ src/vhdl/unb2b_board_10gbe.vhd
test_bench_files =
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
similarity index 100%
rename from boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
rename to boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index ea74660cd7..209919bdf6 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology =
synth_files =
- src/vhdl/common_pkg.vhd
+ $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd
src/vhdl/common_str_pkg.vhd
src/vhdl/common_mem_pkg.vhd
src/vhdl/common_math_pkg.vhd
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 9e1a2696f1..acc0049b6d 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_clkbuf_global.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index 792d355bb4..0fb297e058 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_complex_mult.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index f2b64c3ae4..0da02d5cf9 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_ddio_in_1.qip
- ip_arria10_e1sg_ddio_out_1.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddio_in_1.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 275820f5ff..342197bd9f 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_ddr4_4g_1600.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 20bde73a26..2d3e4f44fa 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_ddr4_4g_2000.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index a1e0f76eba..7a50076c7e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_ddr4_8g_1600.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 305e04c17e..fb483b95fe 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_ddr4_8g_2400.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.csv b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.csv
index 0c0b9dbd7b..7928e6edff 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.csv
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.csv
@@ -1,12 +1,12 @@
-# system info ip_arria10_e1sg_ddr4_8g_2400 on 2019.10.09.08:45:39
+# system info ip_arria10_e1sg_ddr4_8g_2400 on 2019.10.09.19:37:27
system_info:
name,value
DEVICE,10AX115S2F45E1SG
DEVICE_FAMILY,Arria 10
-GENERATION_ID,1570603537
+GENERATION_ID,1570642646
#
#
-# Files generated for ip_arria10_e1sg_ddr4_8g_2400 on 2019.10.09.08:45:39
+# Files generated for ip_arria10_e1sg_ddr4_8g_2400 on 2019.10.09.19:37:27
files:
filepath,kind,attributes,module,is_top
sim/ip_arria10_e1sg_ddr4_8g_2400.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,ip_arria10_e1sg_ddr4_8g_2400,true
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.html b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.html
index 958b0867f7..6e86d23739 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.html
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.html
@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
- <td class="l">2019.10.09.08:45:42</td>
+ <td class="l">2019.10.09.19:37:30</td>
<td class="r">Datasheet</td>
</tr>
</table>
@@ -19570,7 +19570,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.18 seconds</td>
+ <td class="r">rendering took 0.19 seconds</td>
</tr>
</table>
</body>
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
index 93b075b27f..86d14bae65 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
@@ -2,7 +2,7 @@ set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria1
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_TOOL_VERSION "17.0.2"
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -library "ip_arria10_e1sg_ddr4_8g_2400" -name SOPCINFO_FILE [file join $::quartus(qip_path) "ip_arria10_e1sg_ddr4_8g_2400.sopcinfo"]
-set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name SLD_INFO "QSYS_NAME ip_arria10_e1sg_ddr4_8g_2400 HAS_SOPCINFO 1 GENERATION_ID 1570603542"
+set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name SLD_INFO "QSYS_NAME ip_arria10_e1sg_ddr4_8g_2400 HAS_SOPCINFO 1 GENERATION_ID 1570642650"
set_global_assignment -library "ip_arria10_e1sg_ddr4_8g_2400" -name MISC_FILE [file join $::quartus(qip_path) "ip_arria10_e1sg_ddr4_8g_2400.cmp"]
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_TARGETED_PART_TRAIT "part.SUPPORTS_VID::0"
@@ -5489,7 +5489,7 @@ set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria1
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU3MDYwMzU0Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU3MDY0MjY1MA==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVMyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "ip_arria10_e1sg_ddr4_8g_2400" -library "ip_arria10_e1sg_ddr4_8g_2400" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.sopcinfo b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.sopcinfo
index 5f6ee8c88a..306fd32f3d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.sopcinfo
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.sopcinfo
@@ -5,11 +5,11 @@
version="1.0"
fabric="QSYS">
<!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2019.10.09.08:45:42 -->
+ <!-- 2019.10.09.19:37:30 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
- <value>1570603542</value>
+ <value>1570642650</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.xml b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.xml
index c978552b42..a0fd4e1eb0 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.xml
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.xml
@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<deploy
- date="2019.10.09.08:45:43"
+ date="2019.10.09.19:37:31"
outputDirectory="/home/donker/git/hdl/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/">
<perimeter>
<parameter
@@ -185,7 +185,7 @@
version="1.0"
name="ip_arria10_e1sg_ddr4_8g_2400">
<parameter name="AUTO_PLL_REF_CLK_CLOCK_SINK_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1570603542" />
+ <parameter name="AUTO_GENERATION_ID" value="1570642650" />
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_PLL_REF_CLK_CLOCK_SINK_RESET_DOMAIN" value="-1" />
@@ -234,7 +234,7 @@
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: altera_avalon_mm_bridge"</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"</message>
<message level="Info" culprit="ioaux_soft_ram">Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
- <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
+ <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="ioaux_soft_ram">Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki"</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: altera_merlin_master_translator"</message>
@@ -1985,7 +1985,7 @@
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: altera_avalon_mm_bridge"</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"</message>
<message level="Info" culprit="ioaux_soft_ram">Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
- <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
+ <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="ioaux_soft_ram">Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki"</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: altera_merlin_master_translator"</message>
@@ -5525,7 +5525,7 @@
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: altera_avalon_mm_bridge"</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"</message>
<message level="Info" culprit="ioaux_soft_ram">Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
- <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
+ <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="ioaux_soft_ram">Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki"</message>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: altera_merlin_master_translator"</message>
@@ -5634,7 +5634,7 @@
<messages>
<message level="Info" culprit="ip_arria10_e1sg_ddr4_8g_2400">"Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"</message>
<message level="Info" culprit="ioaux_soft_ram">Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
- <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
+ <message level="Info" culprit="ioaux_soft_ram"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="ioaux_soft_ram">Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'</message>
</messages>
</entity>
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation.rpt b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation.rpt
index 1d8ca851a2..7feb0bbf6d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation.rpt
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation.rpt
@@ -44,7 +44,7 @@ Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave i
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has address signal 16 bit wide, but the slave is 12 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has read signal 1 bit wide, but the slave is 0 bit wide.
-Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.147s
+Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.142s
Info: mm_interconnect_0: Running transform interconnect_transform_chooser
Info: mm_interconnect_0: Running transform interconnect_transform_chooser took 0.033s
Info: ip_arria10_e1sg_ddr4_8g_2400: "Naming system components in system: ip_arria10_e1sg_ddr4_8g_2400"
@@ -56,7 +56,7 @@ Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_al
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_avalon_mm_bridge"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"
Info: ioaux_soft_ram: Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
-Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_2243741118461074668.dir/0004_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --vhdl --config=/tmp/alt8178_2243741118461074668.dir/0004_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt8178_2243741118461074668.dir/0004_ioaux_soft_ram_gen/ ]
+Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1526419091961342961.dir/0004_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --vhdl --config=/tmp/alt8178_1526419091961342961.dir/0004_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt8178_1526419091961342961.dir/0004_ioaux_soft_ram_gen/ ]
Info: ioaux_soft_ram: Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_reset_controller"
@@ -123,14 +123,14 @@ Info: ioaux_soft_ram: Running transform generation_view_transform took 0.000s
Info: ip_arria10_e1sg_ddr4_8g_2400: Running transform interconnect_transform_chooser
Info: ip_arria10_e1sg_ddr4_8g_2400: Running transform interconnect_transform_chooser took 0.008s
Info: ddr4_inst: Running transform interconnect_transform_chooser
-Info: ddr4_inst: Running transform interconnect_transform_chooser took 0.032s
+Info: ddr4_inst: Running transform interconnect_transform_chooser took 0.033s
Info: cal_slave_component: Running transform interconnect_transform_chooser
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has address signal 16 bit wide, but the slave is 12 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has read signal 1 bit wide, but the slave is 0 bit wide.
-Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.079s
+Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.074s
Info: mm_interconnect_0: Running transform interconnect_transform_chooser
Info: mm_interconnect_0: Running transform interconnect_transform_chooser took 0.032s
Info: ip_arria10_e1sg_ddr4_8g_2400: "Naming system components in system: ip_arria10_e1sg_ddr4_8g_2400"
@@ -142,7 +142,7 @@ Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_al
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_avalon_mm_bridge"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"
Info: ioaux_soft_ram: Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
-Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_2243741118461074668.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]
+Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_1526419091961342961.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]
Info: ioaux_soft_ram: Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_reset_controller"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation_previous.rpt b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation_previous.rpt
index 9769e286d3..279a17d42e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation_previous.rpt
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_generation_previous.rpt
@@ -35,16 +35,16 @@ Info: ioaux_master_bridge: Running transform generation_view_transform took 0.00
Info: ioaux_soft_ram: Running transform generation_view_transform
Info: ioaux_soft_ram: Running transform generation_view_transform took 0.000s
Info: ip_arria10_e1sg_ddr4_8g_2400: Running transform interconnect_transform_chooser
-Info: ip_arria10_e1sg_ddr4_8g_2400: Running transform interconnect_transform_chooser took 0.026s
+Info: ip_arria10_e1sg_ddr4_8g_2400: Running transform interconnect_transform_chooser took 0.027s
Info: ddr4_inst: Running transform interconnect_transform_chooser
-Info: ddr4_inst: Running transform interconnect_transform_chooser took 0.058s
+Info: ddr4_inst: Running transform interconnect_transform_chooser took 0.059s
Info: cal_slave_component: Running transform interconnect_transform_chooser
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has address signal 16 bit wide, but the slave is 12 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has read signal 1 bit wide, but the slave is 0 bit wide.
-Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.142s
+Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.149s
Info: mm_interconnect_0: Running transform interconnect_transform_chooser
Info: mm_interconnect_0: Running transform interconnect_transform_chooser took 0.033s
Info: ip_arria10_e1sg_ddr4_8g_2400: "Naming system components in system: ip_arria10_e1sg_ddr4_8g_2400"
@@ -56,7 +56,7 @@ Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_al
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_avalon_mm_bridge"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"
Info: ioaux_soft_ram: Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
-Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_7750543412987747309.dir/0004_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --vhdl --config=/tmp/alt8178_7750543412987747309.dir/0004_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt8178_7750543412987747309.dir/0004_ioaux_soft_ram_gen/ ]
+Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1705704913097557955.dir/0004_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --vhdl --config=/tmp/alt8178_1705704913097557955.dir/0004_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt8178_1705704913097557955.dir/0004_ioaux_soft_ram_gen/ ]
Info: ioaux_soft_ram: Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_reset_controller"
@@ -123,14 +123,14 @@ Info: ioaux_soft_ram: Running transform generation_view_transform took 0.000s
Info: ip_arria10_e1sg_ddr4_8g_2400: Running transform interconnect_transform_chooser
Info: ip_arria10_e1sg_ddr4_8g_2400: Running transform interconnect_transform_chooser took 0.008s
Info: ddr4_inst: Running transform interconnect_transform_chooser
-Info: ddr4_inst: Running transform interconnect_transform_chooser took 0.036s
+Info: ddr4_inst: Running transform interconnect_transform_chooser took 0.032s
Info: cal_slave_component: Running transform interconnect_transform_chooser
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has address signal 16 bit wide, but the slave is 12 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has read signal 1 bit wide, but the slave is 0 bit wide.
-Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.131s
+Info: cal_slave_component: Running transform interconnect_transform_chooser took 0.074s
Info: mm_interconnect_0: Running transform interconnect_transform_chooser
Info: mm_interconnect_0: Running transform interconnect_transform_chooser took 0.033s
Info: ip_arria10_e1sg_ddr4_8g_2400: "Naming system components in system: ip_arria10_e1sg_ddr4_8g_2400"
@@ -142,7 +142,7 @@ Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_al
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_avalon_mm_bridge"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy"
Info: ioaux_soft_ram: Starting RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
-Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_7750543412987747309.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_7750543412987747309.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]
+Info: ioaux_soft_ram: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy --dir=/tmp/alt8178_1705704913097557955.dir/0011_ioaux_soft_ram_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt8178_1705704913097557955.dir/0011_ioaux_soft_ram_gen//ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy_component_configuration.pl --do_build_sim=0 ]
Info: ioaux_soft_ram: Done RTL generation for module 'ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy'
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki"
Info: ip_arria10_e1sg_ddr4_8g_2400: "Generating: altera_reset_controller"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/aldec/rivierapro_setup.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/aldec/rivierapro_setup.tcl
index 5c059fdcbf..821d232dcd 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/aldec/rivierapro_setup.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/aldec/rivierapro_setup.tcl
@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
-# ACDS 17.0.2 297 linux 2019.10.09.08:45:40
+# ACDS 17.0.2 297 linux 2019.10.09.19:37:28
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/cadence/ncsim_setup.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/cadence/ncsim_setup.sh
index 9e0d18cf60..816eb84d03 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/cadence/ncsim_setup.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/cadence/ncsim_setup.sh
@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
-# ACDS 17.0.2 297 linux 2019.10.09.08:45:39
+# ACDS 17.0.2 297 linux 2019.10.09.19:37:28
# ----------------------------------------
# ncsim - auto-generated simulation script
@@ -106,7 +106,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Intel IP within the design.
# ----------------------------------------
-# ACDS 17.0.2 297 linux 2019.10.09.08:45:39
+# ACDS 17.0.2 297 linux 2019.10.09.19:37:28
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="ip_arria10_e1sg_ddr4_8g_2400.ip_arria10_e1sg_ddr4_8g_2400"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/mentor/msim_setup.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/mentor/msim_setup.tcl
index beec10d7a0..f3cab85826 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/mentor/msim_setup.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/mentor/msim_setup.tcl
@@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Intel IP within the design.
# ----------------------------------------
-# ACDS 17.0.2 297 linux 2019.10.09.08:45:39
+# ACDS 17.0.2 297 linux 2019.10.09.19:37:28
# ----------------------------------------
# Initialize variables
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/synopsys/vcsmx/vcsmx_setup.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/synopsys/vcsmx/vcsmx_setup.sh
index 95cfba4645..22e9a1018e 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/synopsys/vcsmx/vcsmx_setup.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
-# ACDS 17.0.2 297 linux 2019.10.09.08:45:39
+# ACDS 17.0.2 297 linux 2019.10.09.19:37:28
# ----------------------------------------
# vcsmx - auto-generated simulation script
@@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Intel IP within the design.
# ----------------------------------------
-# ACDS 17.0.2 297 linux 2019.10.09.08:45:39
+# ACDS 17.0.2 297 linux 2019.10.09.19:37:28
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="ip_arria10_e1sg_ddr4_8g_2400.ip_arria10_e1sg_ddr4_8g_2400"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index 63faeffb57..e2f256dcdb 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_asmi_parallel.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index dd59deef2f..b134d0ea3e 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_remote_update.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index bd4e4eff0a..52f1d94556 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_fractional_pll_clk125.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 0b2de2be9b..df35422b3d 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_fractional_pll_clk200.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 8e576bcb2a..1b97f1135e 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_mac_10g.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 29c2cd4a06..275ad15cc8 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_phy_10gbase_r.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index adcef5d58c..35002dd42d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_phy_10gbase_r_12.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 84069a7a0d..b6946fadb1 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_phy_10gbase_r_24.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index 72f4164679..baa59d44bf 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_phy_10gbase_r_3.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 40308d30b6..3bab51b920 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_phy_10gbase_r_4.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index a439f350cf..3d5f7563e9 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_phy_10gbase_r_48.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 4be4605015..361af8b8f8 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_pll_clk125.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index 214a794d79..cf73f3b1e1 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_pll_clk200.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index 0c91441dd8..77d9567516 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_pll_clk25.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 4f77d20d79..92b2f2712c 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 3a72010b5e..4ad2baec31 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -15,4 +15,9 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = ip_arria10_e1sg_temp_sense.qip
+quartus_qip_files =
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_temp_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_temp_sense.qsys
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index b5d432d88e..b41e0f876f 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -16,4 +16,4 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_transceiver_pll_10g.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index e8426aa936..0034bdc551 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_transceiver_reset_controller_1.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index da3c791351..509fc8b1dc 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_transceiver_reset_controller_12.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index d6ecda1740..be2f19a032 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_transceiver_reset_controller_24.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index c4267c2954..e542216d13 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -16,4 +16,4 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_transceiver_reset_controller_3.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 83fd058fc8..1112b245c3 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_transceiver_reset_controller_4.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 256927382b..8115462191 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_transceiver_reset_controller_48.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index fc7ebd16d8..e45525fc7c 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_tse_sgmii_gx.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index ab4006d191..97f18f8a16 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- ip_arria10_e1sg_tse_sgmii_lvds.qip
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 150159a14e..1edb0c7a59 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -16,7 +16,8 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = ip_arria10_e1sg_voltage_sense.qip
+quartus_qip_files =
+ $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
--
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