diff --git a/libraries/base/common/tb/vhdl/tb_round.vhd b/libraries/base/common/tb/vhdl/tb_round.vhd
index 8f029daca7bbb6542de687569f50f13b730f06eb..5d63ec8dd1ca72fa3cd65f44065794bb370faad4 100644
--- a/libraries/base/common/tb/vhdl/tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_round.vhd
@@ -61,6 +61,20 @@ ARCHITECTURE tb OF tb_round IS
CONSTANT c_in_umax : INTEGER := 2**g_in_dat_w - 1;
CONSTANT c_in_umax_no_clip : INTEGER := c_in_umax - c_in_half;
+ -- Expected rounded results from [2] for w = g_in_dat_w = 5 and r = c_round_w = 2
+ CONSTANT c_exp_w5_r2_signed_truncate : t_integer_arr(0 TO 31) := (-4, -4, -4, -4, -3, -3, -3, -3, -2, -2, -2, -2, -1, -1, -1, -1, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3);
+ CONSTANT c_exp_w5_r2_signed_round_half_away : t_integer_arr(0 TO 31) := (-4, -4, -4, -3, -3, -3, -3, -2, -2, -2, -2, -1, -1, -1, -1, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, -4, -4);
+ CONSTANT c_exp_w5_r2_signed_round_half_away_clip : t_integer_arr(0 TO 31) := (-4, -4, -4, -3, -3, -3, -3, -2, -2, -2, -2, -1, -1, -1, -1, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3);
+ CONSTANT c_exp_w5_r2_signed_round_half_even : t_integer_arr(0 TO 31) := (-4, -4, -4, -3, -3, -3, -2, -2, -2, -2, -2, -1, -1, -1, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, -4, -4);
+ CONSTANT c_exp_w5_r2_signed_round_half_even_clip : t_integer_arr(0 TO 31) := (-4, -4, -4, -3, -3, -3, -2, -2, -2, -2, -2, -1, -1, -1, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3);
+
+ CONSTANT c_exp_w5_r2_unsigned_truncate : t_natural_arr(0 TO 31) := (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7);
+ CONSTANT c_exp_w5_r2_unsigned_truncate_symmetric : t_natural_arr(0 TO 31) := (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7);
+ CONSTANT c_exp_w5_r2_unsigned_round_half_up : t_natural_arr(0 TO 31) := (0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 0, 0);
+ CONSTANT c_exp_w5_r2_unsigned_round_half_up_clip : t_natural_arr(0 TO 31) := (0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7);
+ CONSTANT c_exp_w5_r2_unsigned_round_half_even : t_natural_arr(0 TO 31) := (0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 0, 0);
+ CONSTANT c_exp_w5_r2_unsigned_round_half_even_clip : t_natural_arr(0 TO 31) := (0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7);
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
@@ -79,6 +93,12 @@ ARCHITECTURE tb OF tb_round IS
SIGNAL fs_signed_round_half_even : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL fs_signed_round_half_even_clip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL S_w5_r2 : NATURAL; -- lookup index for signed
+ SIGNAL exp_w5_r2_signed_truncate : INTEGER;
+ SIGNAL exp_w5_r2_signed_round_half_away : INTEGER;
+ SIGNAL exp_w5_r2_signed_round_half_away_clip : INTEGER;
+ SIGNAL exp_w5_r2_signed_round_half_even : INTEGER;
+ SIGNAL exp_w5_r2_signed_round_half_even_clip : INTEGER;
-- . show as real in Wave window
SIGNAL fs_sreal_fixed_point : REAL := 0.0;
SIGNAL fs_sreal_truncate : REAL := 0.0;
@@ -96,6 +116,13 @@ ARCHITECTURE tb OF tb_round IS
SIGNAL fs_unsigned_round_half_even : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL fs_unsigned_round_half_even_clip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL U_w5_r2 : NATURAL; -- lookup index for unsigned
+ SIGNAL exp_w5_r2_unsigned_truncate : INTEGER;
+ SIGNAL exp_w5_r2_unsigned_round_half_up : INTEGER;
+ SIGNAL exp_w5_r2_unsigned_round_half_up_clip : INTEGER;
+ SIGNAL exp_w5_r2_unsigned_round_half_even : INTEGER;
+ SIGNAL exp_w5_r2_unsigned_round_half_even_clip : INTEGER;
+
-- . show as real in Wave window
SIGNAL fs_ureal_fixed_point : REAL := 0.0;
SIGNAL fs_ureal_truncate : REAL := 0.0;
@@ -104,6 +131,13 @@ ARCHITECTURE tb OF tb_round IS
SIGNAL fs_ureal_round_half_even : REAL := 0.0;
SIGNAL fs_ureal_round_half_even_clip : REAL := 0.0;
+ -- Debug signals, for view in Wave window
+ SIGNAL dbg_c_exp_w5_r2_signed_truncate : t_integer_arr(0 TO 31) := c_exp_w5_r2_signed_truncate;
+ SIGNAL dbg_c_exp_w5_r2_signed_round_half_away : t_integer_arr(0 TO 31) := c_exp_w5_r2_signed_round_half_away;
+ SIGNAL dbg_c_exp_w5_r2_signed_round_half_away_clip : t_integer_arr(0 TO 31) := c_exp_w5_r2_signed_round_half_away_clip;
+ SIGNAL dbg_c_exp_w5_r2_signed_round_half_even : t_integer_arr(0 TO 31) := c_exp_w5_r2_signed_round_half_even;
+ SIGNAL dbg_c_exp_w5_r2_signed_round_half_even_clip : t_integer_arr(0 TO 31) := c_exp_w5_r2_signed_round_half_even_clip;
+
BEGIN
-- Stimuli
@@ -190,7 +224,7 @@ BEGIN
GENERIC MAP (
g_representation => "SIGNED",
g_round => TRUE,
- g_round_clip => TRUE,
+ g_round_clip => FALSE,
g_round_even => TRUE,
g_pipeline_input => c_pipeline_input,
g_pipeline_output => c_pipeline_output,
@@ -325,6 +359,20 @@ BEGIN
fs_ureal_round_half_even <= TO_UREAL(fs_unsigned_round_half_even, 0);
fs_ureal_round_half_even_clip <= TO_UREAL(fs_unsigned_round_half_even_clip, 0);
+ -- Expected rounded values
+ S_w5_r2 <= (TO_UINT(in_dat) + 16) MOD 32;
+ exp_w5_r2_signed_truncate <= c_exp_w5_r2_signed_truncate(S_w5_r2);
+ exp_w5_r2_signed_round_half_away <= c_exp_w5_r2_signed_round_half_away(S_w5_r2);
+ exp_w5_r2_signed_round_half_away_clip <= c_exp_w5_r2_signed_round_half_away_clip(S_w5_r2);
+ exp_w5_r2_signed_round_half_even <= c_exp_w5_r2_signed_round_half_even(S_w5_r2);
+ exp_w5_r2_signed_round_half_even_clip <= c_exp_w5_r2_signed_round_half_even_clip(S_w5_r2);
+ U_w5_r2 <= TO_UINT(in_dat);
+ exp_w5_r2_unsigned_truncate <= c_exp_w5_r2_unsigned_truncate(U_w5_r2);
+ exp_w5_r2_unsigned_round_half_up <= c_exp_w5_r2_unsigned_round_half_up(U_w5_r2);
+ exp_w5_r2_unsigned_round_half_up_clip <= c_exp_w5_r2_unsigned_round_half_up_clip(U_w5_r2);
+ exp_w5_r2_unsigned_round_half_even <= c_exp_w5_r2_unsigned_round_half_even(U_w5_r2);
+ exp_w5_r2_unsigned_round_half_even_clip <= c_exp_w5_r2_unsigned_round_half_even_clip(U_w5_r2);
+
-- Verification
p_verify : PROCESS
BEGIN
@@ -333,11 +381,11 @@ BEGIN
IF c_round_w = 0 THEN
-- Without rounding the expected value is same as input value
-- . signed
- ASSERT SIGNED(fs_signed_truncate ) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_truncate" SEVERITY ERROR;
- ASSERT SIGNED(fs_signed_round_half_away ) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_away" SEVERITY ERROR;
- ASSERT SIGNED(fs_signed_round_half_away_clip) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_away_clip" SEVERITY ERROR;
- ASSERT SIGNED(fs_signed_round_half_even ) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_even" SEVERITY ERROR;
- ASSERT SIGNED(fs_signed_round_half_even_clip) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_even_clip" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_truncate ) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_truncate" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_away ) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_away" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_away_clip) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_away_clip" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_even ) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_even" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_even_clip) = SIGNED(reg_dat) REPORT "Wrong wired fs_signed_round_half_even_clip" SEVERITY ERROR;
-- . unsigned
ASSERT UNSIGNED(fs_unsigned_truncate ) = UNSIGNED(reg_dat) REPORT "Wrong wired fs_unsigned_truncate" SEVERITY ERROR;
ASSERT UNSIGNED(fs_unsigned_round_half_up ) = UNSIGNED(reg_dat) REPORT "Wrong wired fs_unsigned_round_half_up" SEVERITY ERROR;
@@ -345,8 +393,21 @@ BEGIN
ASSERT UNSIGNED(fs_unsigned_round_half_even ) = UNSIGNED(reg_dat) REPORT "Wrong wired fs_unsigned_round_half_even" SEVERITY ERROR;
ASSERT UNSIGNED(fs_unsigned_round_half_even_clip) = UNSIGNED(reg_dat) REPORT "Wrong wired fs_unsigned_round_half_even_clip" SEVERITY ERROR;
ELSE
- -- For reduced width compare with expected list of values from common_round_tb.py
-
+ -- With rounding then compare with expected list of values from common_round_tb.py
+ IF g_in_dat_w = 5 AND c_round_w = 2 THEN
+ -- . signed
+ ASSERT SIGNED(fs_signed_truncate ) = exp_w5_r2_signed_truncate REPORT "Wrong exp_w5_r2_signed_truncate" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_away ) = exp_w5_r2_signed_round_half_away REPORT "Wrong exp_w5_r2_signed_round_half_away" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_away_clip) = exp_w5_r2_signed_round_half_away_clip REPORT "Wrong exp_w5_r2_signed_round_half_away_clip" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_even ) = exp_w5_r2_signed_round_half_even REPORT "Wrong exp_w5_r2_signed_round_half_even" SEVERITY ERROR;
+ ASSERT SIGNED(fs_signed_round_half_even_clip) = exp_w5_r2_signed_round_half_even_clip REPORT "Wrong exp_w5_r2_signed_round_half_even_clip" SEVERITY ERROR;
+ -- . unsigned
+ ASSERT UNSIGNED(fs_unsigned_truncate ) = exp_w5_r2_unsigned_truncate REPORT "Wrong exp_w5_r2_unsigned_truncate" SEVERITY ERROR;
+ ASSERT UNSIGNED(fs_unsigned_round_half_up ) = exp_w5_r2_unsigned_round_half_up REPORT "Wrong exp_w5_r2_unsigned_round_half_up" SEVERITY ERROR;
+ ASSERT UNSIGNED(fs_unsigned_round_half_up_clip ) = exp_w5_r2_unsigned_round_half_up_clip REPORT "Wrong exp_w5_r2_unsigned_round_half_up_clip" SEVERITY ERROR;
+ ASSERT UNSIGNED(fs_unsigned_round_half_even ) = exp_w5_r2_unsigned_round_half_even REPORT "Wrong exp_w5_r2_unsigned_round_half_even" SEVERITY ERROR;
+ ASSERT UNSIGNED(fs_unsigned_round_half_even_clip) = exp_w5_r2_unsigned_round_half_even_clip REPORT "Wrong exp_w5_r2_unsigned_round_half_even_clip" SEVERITY ERROR;
+ END IF;
END IF;
END IF;
END PROCESS;