From a340151f52725a509fc1918c527ebf3cb44260cc Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Wed, 15 Nov 2017 13:15:35 +0000
Subject: [PATCH] -Fixed wrong generic name in comment.
---
libraries/base/dp/src/vhdl/dp_counter.vhd | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index 7048f118f6..78858f8422 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -27,7 +27,7 @@
-- . See dp_counter_func.
-- . dp_counter_func contains only functional logic (no pipelining).
-- . This wrapper adds pipelining for the source side outputs (g_pipeline_src_out)
--- and source side inputs (g_pipeline_snk_in).
+-- and source side inputs (g_pipeline_src_in).
LIBRARY IEEE,common_lib;
USE IEEE.std_logic_1164.ALL;
@@ -85,7 +85,7 @@ BEGIN
);
------------------------------------------------------------------------------
- -- dp_pipeline
+ -- dp_pipeline if g_pipeline_src_out > 0
------------------------------------------------------------------------------
gen_dp_pipeline : IF g_pipeline_src_out > 0 GENERATE
u_dp_pipeline_snk_in : ENTITY work.dp_pipeline
@@ -126,7 +126,7 @@ BEGIN
END GENERATE;
------------------------------------------------------------------------------
- -- dp_pipeline_ready
+ -- dp_pipeline_ready if g_pipeline_src_in > 0
------------------------------------------------------------------------------
gen_dp_pipeline_ready : IF g_pipeline_src_in > 0 GENERATE
u_dp_pipeline_ready : ENTITY work.dp_pipeline_ready
--
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