diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
index 1ad8c0ef3061ad9ea5983c4c3b9ceae73e703ff2..06ef74274b9d1dea1c90fc2eb73d8d9bf0ff6499 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
@@ -7,10 +7,10 @@ hdl_lib_include_ip =
ip_arria10_e1sg_mac_10g
ip_arria10_e1sg_pll_xgmii_mac_clocks
ip_arria10_e1sg_transceiver_pll_10g
-
ip_arria10_e1sg_phy_10gbase_r
-
+ ip_arria10_e1sg_phy_10gbase_r_3
ip_arria10_e1sg_transceiver_reset_controller_1
+ ip_arria10_e1sg_transceiver_reset_controller_3
synth_files =
src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 930b1b6496ac4f82ceba721970d004df804014e2..03dbe0e4275428f130989cd2766888fee4706020 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -234,7 +234,7 @@ peripherals:
#############################################################################
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
-
+
- peripheral_name: dp/dp_bsn_sync_scheduler
peripheral_group: xsub
mm_port_names:
@@ -267,6 +267,8 @@ peripherals:
- peripheral_name: dp/dp_bsn_align_v2
peripheral_group: xsub
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- REG_BSN_ALIGN
@@ -314,7 +316,7 @@ peripherals:
parameter_overrides:
- { name: g_nof_err_counts, value: c_lane_nof_err_counts }
mm_port_names:
- - REG_DP_BLOCK_VALIDATE_ERR__XST
+ - REG_DP_BLOCK_VALIDATE_ERR_XST
- peripheral_name: dp/dp_block_validate_bsn_at_sync
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index ae0888536aeedbec63c93cb0f41f88047f2254bb..d9ec6d491a768558510f923304dbc447798c4309 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -2008,6 +2008,76 @@
internal="reg_bsn_monitor_input.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_address"
+ internal="reg_bsn_monitor_v2_bsn_align_input.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_clk"
+ internal="reg_bsn_monitor_v2_bsn_align_input.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_read"
+ internal="reg_bsn_monitor_v2_bsn_align_input.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_readdata"
+ internal="reg_bsn_monitor_v2_bsn_align_input.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_reset"
+ internal="reg_bsn_monitor_v2_bsn_align_input.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_write"
+ internal="reg_bsn_monitor_v2_bsn_align_input.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_writedata"
+ internal="reg_bsn_monitor_v2_bsn_align_input.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_address"
+ internal="reg_bsn_monitor_v2_bsn_align_output.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_clk"
+ internal="reg_bsn_monitor_v2_bsn_align_output.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_read"
+ internal="reg_bsn_monitor_v2_bsn_align_output.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_readdata"
+ internal="reg_bsn_monitor_v2_bsn_align_output.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_reset"
+ internal="reg_bsn_monitor_v2_bsn_align_output.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_write"
+ internal="reg_bsn_monitor_v2_bsn_align_output.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_writedata"
+ internal="reg_bsn_monitor_v2_bsn_align_output.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_monitor_v2_ring_rx_xst_address"
internal="reg_bsn_monitor_v2_ring_rx_xst.address"
@@ -2634,41 +2704,6 @@
internal="reg_hdr_dat.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_input_monitor_address"
- internal="reg_bsn_monitor_v2_bsn_align_input.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_clk"
- internal="reg_bsn_monitor_v2_bsn_align_input.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_read"
- internal="reg_bsn_monitor_v2_bsn_align_input.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_input.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_reset"
- internal="reg_bsn_monitor_v2_bsn_align_input.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_write"
- internal="reg_bsn_monitor_v2_bsn_align_input.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_input.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_mmdp_ctrl_address"
internal="reg_mmdp_ctrl.address"
@@ -2844,41 +2879,6 @@
internal="reg_nw_10gbe_mac.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_output_monitor_address"
- internal="reg_bsn_monitor_v2_bsn_align_output.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_clk"
- internal="reg_bsn_monitor_v2_bsn_align_output.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_read"
- internal="reg_bsn_monitor_v2_bsn_align_output.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_output.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_reset"
- internal="reg_bsn_monitor_v2_bsn_align_output.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_write"
- internal="reg_bsn_monitor_v2_bsn_align_output.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_output.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_remu_address"
internal="reg_remu.address"
@@ -20804,7 +20804,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">/home/walle/git-lofar/hdl/build/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -21420,7 +21420,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">/home/walle/git-lofar/hdl/build/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
index a794505be0ddfe6ad85c2d1eba571ece74bc2348..8057d50655a1a0ccd51c795fd4669846d07fe783 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
@@ -8,6 +8,7 @@ hdl_lib_technology = ip_arria10_e1sg
lofar2_unb2b_sdp_station_xsub_ring.vhd
test_bench_files =
+ tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
regression_test_vhdl =
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9ae1074186aa6132c583d7fde0ca595bfd437d4e
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -0,0 +1,487 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_xsub_ring using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- freq = 19.921875MHz = subband index 102
+-- ampl = 0.5 * 2**13, full scale amplitude is 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Read crosslets statistics (XST) via ram_st_xsq and verify that the values
+-- are as expected. This is done by comparing the values in the outgoing square
+-- correlation matrix.
+--
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+-- Takes about 40 m
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_xsub_ring IS
+END tb_lofar2_unb2b_sdp_station_xsub_ring;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_ring IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_nof_rn : NATURAL := 2;
+ CONSTANT c_P_sq : NATURAL := (c_nof_rn / 2) + 1;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 24;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+ CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync;
+
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
+ CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
+ CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
+ CONSTANT c_nof_lanes : NATURAL := 1;
+
+ -- WG
+ CONSTANT c_FS_adc : REAL := REAL(c_sdp_FS_adc); -- = full scale of WG
+ CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_FS_adc; -- amplitude in number of LSbit resolution steps
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
+
+ -- WPFB
+ CONSTANT c_nof_pfb : NATURAL := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ CONSTANT c_wb_leakage_bin : NATURAL := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ CONSTANT c_exp_sp_subband_power_ratio : REAL := 1.0/8.0; -- depends on internal WPFB quantization and FIR coefficients
+ CONSTANT c_exp_sp_subband_power_sum_ratio : REAL := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ CONSTANT c_exp_subband_power_sp_0 : REAL := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
+
+ TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+ CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
+ CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
+ CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+
+ SIGNAL i_QSFP_0_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_QSFP_0_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_0_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_0_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_1_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_1_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+
+ -- WG
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- WPFB
+ SIGNAL xsub_stats_arr : t_slv_64_arr(0 TO c_P_sq * c_nof_complex * c_sdp_X_sq -1);
+
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '1';
+ SIGNAL SA_CLK : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ gen_dut : FOR RN IN 0 TO c_nof_rn -1 GENERATE
+ u_lofar_unb2b_sdp_station_xsub_ring : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_ring",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN MOD c_quad,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => NATURAL(c_subband_sp_0)
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2b_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+ END GENERATE;
+
+ -- Ring connections
+ gen_ring : FOR I IN 0 TO c_nof_rn -2 GENERATE
+ -- Connect consecutive nodes with RING interfaces (PCB)
+ i_RING_0_RX(I+1) <= i_RING_1_TX(I);
+ i_RING_1_RX(I) <= i_RING_0_TX(I+1);
+ END GENERATE;
+ -- Connect first and last nodes with QSFP interface.
+ i_QSFP_0_RX(0) <= i_QSFP_0_TX(c_nof_rn-1);
+ i_QSFP_0_RX(c_nof_rn-1) <= i_QSFP_0_TX(0);
+
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even, v_SQ_offset: NATURAL; -- array indicies
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ ----------------------------------------------------------------------------
+ -- Enable BSN
+ ----------------------------------------------------------------------------
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 3, 0, tb_clk);
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+ END LOOP;
+
+ -- Release PPS pulser, to get first PPS now and to start BSN source
+ WAIT FOR 1 us;
+ pps_rst <= '0';
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ ----------------------------------------------------------------------------
+ -- Ring config
+ ----------------------------------------------------------------------------
+ -- Write ring configuration to all nodes.
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 2, c_nof_rn, tb_clk); -- N_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
+ END LOOP;
+
+ -- Start node specific settings
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk); -- use_ring_to_previous_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
+
+ -- End node specific settings
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
+
+ -- Access scheme 3. Each RN creates packets and sends them along the ring.
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ -- Set transport_nof_hops to N_rn-1 on all nodes.
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_LANE_INFO_XST", I*2+1, c_nof_rn-1, tb_clk);
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Disable unused streams in dp_bsn_align_v2
+ ----------------------------------------------------------------------------
+ FOR I IN 0 TO c_sdp_P_sq-1 LOOP
+ IF I >= c_P_sq THEN
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_ALIGN", I, 0, tb_clk);
+ END IF;
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Crosslets Info
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_CROSSLETS_INFO", 0, INTEGER(c_subband_sp_0), tb_clk); -- offset
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_CROSSLETS_INFO", 15, 0 , tb_clk); -- stepsize
+ END LOOP;
+ ----------------------------------------------------------------------------
+ -- Enable WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+ END LOOP;
+ END LOOP;
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+
+
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SCHEDULER", 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ -- bsn_scheduler_xsub
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 1, c_ctrl_interval_size, tb_clk); -- Interval size
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 2, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 3, 0, tb_clk); -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 0, 1, tb_clk); -- enable
+ END LOOP;
+
+ -- Wait for enough WG data and start of sync interval
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ ---------------------------------------------------------------------------
+ -- Read crosslet statistics
+ ---------------------------------------------------------------------------
+ -- Only checking P_sq index = 1 (correlating singnals from node 0 and 1) as P_sq index = 0 is verified in tb_lofar2_unb2b_sdp_station_xsub_one.
+ -- Also in simulation, the MM file IO is too slow to read and verify more than 1 P_sq during 1 sync interval. Also, this way the simulation duration is shorter.
+ FOR I IN 0 TO c_nof_complex * c_sdp_X_sq * (c_longword_sz/c_word_sz) -1 LOOP
+ v_W := I MOD 2;
+ v_B := I / 2;
+ v_SQ_offset := 2**ceil_log2(c_sdp_N_crosslets_max * c_nof_complex * c_sdp_X_sq * (c_longword_sz/c_word_sz)); -- Address offset for next P_sq.
+ IF v_W=0 THEN
+ -- low part
+ mmf_mm_bus_rd(c_mm_file_ram_st_xsq, v_SQ_offset + I, rd_data, tb_clk);
+ xsub_stats_arr(v_B)(31 DOWNTO 0) <= rd_data;
+ ELSE
+ -- high part
+ mmf_mm_bus_rd(c_mm_file_ram_st_xsq, v_SQ_offset + I, rd_data, tb_clk);
+ xsub_stats_arr(v_B)(63 DOWNTO 32) <= rd_data;
+ END IF;
+ END LOOP;
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ ---------------------------------------------------------------------------
+ -- Verify crosslet statistics
+ ---------------------------------------------------------------------------
+ -- With all WGs having the same input all crosslets should be identical. Due to quantization cross talk
+ -- between the two real inputs of the filterbank the two signals in the output pairs per P_pfb differ
+ -- slightly, therefore 3 slightly different correlation values are expected. 1 for each correlation
+ -- between even indexed signals, 1 for odd indexed signals and 1 for correlations between even and odd
+ -- indexed signals. This is verified by checking if these values are the same.
+ FOR I IN 0 TO c_nof_complex * c_sdp_X_sq -1 LOOP
+ v_C := I MOD 2;
+ v_X := I /c_nof_complex;
+ v_A := v_X MOD c_sdp_S_pn;
+ v_B := v_X / c_sdp_S_pn;
+ v_A_even := v_A MOD 2;
+ v_B_even := v_B MOD 2;
+
+ -- Check real values of even indices
+ IF v_C=0 AND v_A_even=0 AND v_B_even=0 THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr(0)) REPORT "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check real values of odd indices
+ IF v_C=0 AND v_A_even=1 AND v_B_even=1 THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) REPORT "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check real values of even correlated with odd indices
+ IF v_C=0 AND (v_A_even=0 XOR v_B_even=0) THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr(1 * c_nof_complex)) REPORT "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
+ -- Check im values of even indices
+ IF v_C=1 AND v_A_even=0 AND v_B_even=0 THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr(1))) REPORT "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check im values of odd indices
+ IF v_C=1 AND v_A_even=1 AND v_B_even=1 THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) REPORT "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check im values of even correlated with odd indices
+ IF v_C=1 AND (v_A_even=0 XOR v_B_even=0) THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr(1 * c_nof_complex + 1))) REPORT "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check if values are > 0
+ IF v_C=0 THEN ASSERT (SIGNED(xsub_stats_arr(I)) > TO_SIGNED(0, c_longword_w)) REPORT "correlation is 0 which is unexpected! at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Reporting BSN monitors of the bsn_align_v2
+ ----------------------------------------------------------------------------
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ FOR J IN 0 TO c_P_sq-1 LOOP -- bsn_monitor index
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+0, rd_data, tb_clk); --status bits
+ REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2))) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+1, rd_data, tb_clk); --bsn at sync
+ REPORT "bsn_at_sync = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+3, rd_data, tb_clk); --nof_sop
+ REPORT "nof_sop = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+4, rd_data, tb_clk); --nof_valid
+ REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+5, rd_data, tb_clk); --nof_err
+ REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ END LOOP;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 0, rd_data, tb_clk); --status bits
+ REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2))) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 1, rd_data, tb_clk); --bsn at sync
+ REPORT "bsn_at_sync = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 3, rd_data, tb_clk); --nof_sop
+ REPORT "nof_sop = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 4, rd_data, tb_clk); --nof_valid
+ REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 5, rd_data, tb_clk); --nof_err
+ REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ END LOOP;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 268c6556e12e77d2f213f9c46cf4878bfa480601..f4ed10f55222415fad473a503c8d649965e0bd58 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -26,7 +26,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
-
component qsys_lofar2_unb2b_sdp_station is
port (
avs_eth_0_clk_export : out std_logic; -- export
@@ -183,6 +182,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_bsn_monitor_input_reset_export : out std_logic; -- export
reg_bsn_monitor_input_write_export : out std_logic; -- export
reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_input_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bsn_align_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_output_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bsn_align_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
@@ -309,13 +322,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_hdr_dat_reset_export : out std_logic; -- export
reg_hdr_dat_write_export : out std_logic; -- export
reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_input_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bsn_align_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
reg_mmdp_ctrl_clk_export : out std_logic; -- export
reg_mmdp_ctrl_read_export : out std_logic; -- export
@@ -351,27 +357,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_nw_10gbe_mac_reset_export : out std_logic; -- export
reg_nw_10gbe_mac_write_export : out std_logic; -- export
reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_output_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bsn_align_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
reg_remu_clk_export : out std_logic; -- export
reg_remu_read_export : out std_logic; -- export
@@ -379,6 +364,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_remu_reset_export : out std_logic; -- export
reg_remu_write_export : out std_logic; -- export
reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
reg_ring_lane_info_xst_clk_export : out std_logic; -- export
reg_ring_lane_info_xst_read_export : out std_logic; -- export
@@ -393,13 +385,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_sdp_info_reset_export : out std_logic; -- export
reg_sdp_info_write_export : out std_logic; -- export
reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_si_address_export : out std_logic_vector(0 downto 0); -- export
reg_si_clk_export : out std_logic; -- export
reg_si_read_export : out std_logic; -- export
@@ -449,6 +434,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
reg_unb_pmbus_clk_export : out std_logic; -- export
reg_unb_pmbus_read_export : out std_logic; -- export
@@ -494,5 +493,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_sdp_station;
+
END qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg
index b095e8303dfc581d6f2993898cafa8e65e51103d..08c7824c437d1fcae6c1d3f7907c0545572638fe 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg
@@ -7,10 +7,10 @@ hdl_lib_include_ip =
ip_arria10_e2sg_mac_10g
ip_arria10_e2sg_pll_xgmii_mac_clocks
ip_arria10_e2sg_transceiver_pll_10g
-
ip_arria10_e2sg_phy_10gbase_r
-
+ ip_arria10_e2sg_phy_10gbase_r_3
ip_arria10_e2sg_transceiver_reset_controller_1
+ ip_arria10_e2sg_transceiver_reset_controller_3
synth_files =
src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index ec5d65eba9465d904dcb0458a376e63c1fbc79c6..a0a5c66397695c54b418046bfa02e5971d70db8e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -267,6 +267,8 @@ peripherals:
- peripheral_name: dp/dp_bsn_align_v2
peripheral_group: xsub
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- REG_BSN_ALIGN
@@ -314,7 +316,7 @@ peripherals:
parameter_overrides:
- { name: g_nof_err_counts, value: c_lane_nof_err_counts }
mm_port_names:
- - REG_DP_BLOCK_VALIDATE_ERR__XST
+ - REG_DP_BLOCK_VALIDATE_ERR_XST
- peripheral_name: dp/dp_block_validate_bsn_at_sync
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 7016252ff08451875beee19a353f70e245db59d9..d9a3aae9d961559f03fb666fa2ae7a64627c9a9e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -1962,6 +1962,76 @@
internal="reg_bsn_monitor_input.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_address"
+ internal="reg_bsn_monitor_v2_bsn_align_input.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_clk"
+ internal="reg_bsn_monitor_v2_bsn_align_input.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_read"
+ internal="reg_bsn_monitor_v2_bsn_align_input.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_readdata"
+ internal="reg_bsn_monitor_v2_bsn_align_input.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_reset"
+ internal="reg_bsn_monitor_v2_bsn_align_input.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_write"
+ internal="reg_bsn_monitor_v2_bsn_align_input.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_input_writedata"
+ internal="reg_bsn_monitor_v2_bsn_align_input.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_address"
+ internal="reg_bsn_monitor_v2_bsn_align_output.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_clk"
+ internal="reg_bsn_monitor_v2_bsn_align_output.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_read"
+ internal="reg_bsn_monitor_v2_bsn_align_output.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_readdata"
+ internal="reg_bsn_monitor_v2_bsn_align_output.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_reset"
+ internal="reg_bsn_monitor_v2_bsn_align_output.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_write"
+ internal="reg_bsn_monitor_v2_bsn_align_output.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bsn_align_output_writedata"
+ internal="reg_bsn_monitor_v2_bsn_align_output.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_monitor_v2_ring_rx_xst_address"
internal="reg_bsn_monitor_v2_ring_rx_xst.address"
@@ -2588,41 +2658,6 @@
internal="reg_hdr_dat.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_input_monitor_address"
- internal="reg_bsn_monitor_v2_bsn_align_input.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_clk"
- internal="reg_bsn_monitor_v2_bsn_align_input.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_read"
- internal="reg_bsn_monitor_v2_bsn_align_input.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_input.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_reset"
- internal="reg_bsn_monitor_v2_bsn_align_input.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_write"
- internal="reg_bsn_monitor_v2_bsn_align_input.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_input_monitor_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_input.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_mmdp_ctrl_address"
internal="reg_mmdp_ctrl.address"
@@ -2798,41 +2833,6 @@
internal="reg_nw_10gbe_mac.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_output_monitor_address"
- internal="reg_bsn_monitor_v2_bsn_align_output.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_clk"
- internal="reg_bsn_monitor_v2_bsn_align_output.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_read"
- internal="reg_bsn_monitor_v2_bsn_align_output.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_output.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_reset"
- internal="reg_bsn_monitor_v2_bsn_align_output.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_write"
- internal="reg_bsn_monitor_v2_bsn_align_output.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_output_monitor_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_output.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_remu_address"
internal="reg_remu.address"
@@ -84010,26 +84010,6 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
- <connection
- kind="avalon"
- version="19.4"
- start="cpu_0.data_master"
- end="reg_bsn_monitor_v2_bsn_align_input.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
<connection
kind="avalon"
version="19.4"
@@ -84230,6 +84210,26 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_bsn_align_input.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3400" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
<connection
kind="avalon"
version="19.4"
@@ -84602,11 +84602,6 @@
version="19.4"
start="clk_0.clk"
end="reg_bsn_align.system" />
- <connection
- kind="clock"
- version="19.4"
- start="clk_0.clk"
- end="reg_bsn_monitor_v2_bsn_align_input.system" />
<connection
kind="clock"
version="19.4"
@@ -84657,6 +84652,11 @@
version="19.4"
start="clk_0.clk"
end="reg_tr_10gbe_mac.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_bsn_align_input.system" />
<connection
kind="interrupt"
version="19.4"
@@ -84950,11 +84950,6 @@
version="19.4"
start="clk_0.clk_reset"
end="reg_bsn_align.system_reset" />
- <connection
- kind="reset"
- version="19.4"
- start="clk_0.clk_reset"
- end="reg_bsn_monitor_v2_bsn_align_input.system_reset" />
<connection
kind="reset"
version="19.4"
@@ -85005,6 +85000,11 @@
version="19.4"
start="clk_0.clk_reset"
end="reg_tr_10gbe_mac.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_bsn_align_input.system_reset" />
<connection
kind="reset"
version="19.4"
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
index dbf68d2cc0e74ba4c6526f668d8eba760de7d2e4..c7155b30c3787996f91e3793c5029e15d2805ccb 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
@@ -67,6 +67,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
@@ -85,13 +87,11 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_input_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_output_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
index 845272d5b0b1aa1daec3001ce24cd415d03fbf04..83a37e5186b0dd68b82312c8658604e384af128c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
@@ -75,6 +75,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
@@ -93,13 +95,11 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_input_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_output_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
index b8bcfa75fac41c4646fadd575f4b09aff4ce6a98..0870c853d90ff5b9de135cc31dfceebd5617ebef 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
@@ -74,6 +74,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
@@ -92,13 +94,11 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_input_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_output_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
index 04aa0d9e93571ce483849a705a0880019731bca7..afdba82f37fe3088050e343b0d4207ef55365188 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
@@ -71,6 +71,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
@@ -89,13 +91,11 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_input_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_output_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
index ba5fa68dac73cfb066f0248dc67b302ace59c18e..fa2e4069a35b7668c5aa238fa177916f2cce25b1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
@@ -74,6 +74,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
@@ -92,13 +94,11 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_input_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_output_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
index 3be51c67651ea845fc41708964b42191060a7387..9acb80183e38aae03dab40827f444e16a3a606b3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
@@ -71,6 +71,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
@@ -89,13 +91,11 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_input_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_output_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 4c28ed7ae94f201f4d55ee208c2ef84f83251ef8..d2e63d498c47ca03f3ce41709381e690b4e6a21b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -720,6 +720,7 @@ BEGIN
g_use_fsub => c_revision_select.use_fsub,
g_use_xsub => c_revision_select.use_xsub,
g_use_bf => c_revision_select.use_bf,
+ g_use_ring => c_revision_select.use_ring,
g_P_sq => c_revision_select.P_sq
)
PORT MAP (
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 90c717b14129275297f07bb519cccd1eb5628bbd..2c1fb0955b996d43260b2881e05e073de22aa31d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -479,5 +479,6 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2c_sdp_station;
+
END qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index acf78513cfbfc511eed89265f978d49568bd9d06..65ff3452ccc80afb6827e6aea81dbaed81cab3ef 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -52,6 +52,7 @@ ENTITY node_sdp_correlator IS
xst_udp_siso : IN t_dp_siso;
from_ri_sosi : IN t_dp_sosi := c_dp_sosi_rst;
to_ri_sosi : OUT t_dp_sosi;
+ bs_sosi : OUT t_dp_sosi;
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -106,7 +107,9 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL local_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL ring_mux_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL ring_mux_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL rx_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL dispatch_invert_sosi_arr : t_dp_sosi_arr(0 TO g_P_sq-1) := (OTHERS => c_dp_sosi_rst);
SIGNAL dispatch_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL crosslets_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -169,6 +172,10 @@ BEGIN
out_crosslets_info => crosslets_info
);
+
+ -- Use xsel_sosi as local bsn and sync reference since the sync
+ -- is generated by the bsn_sync_scheduler in sdp_crosslets_subband_select.
+ bs_sosi <= xsel_sosi;
---------------------------------------------------------------
-- Repack 32b to 64b
@@ -183,10 +190,11 @@ BEGIN
u_dp_repack_data_local : ENTITY dp_lib.dp_repack_data
GENERIC MAP (
- g_in_dat_w => c_data_w,
- g_in_nof_words => c_longword_w/c_data_w,
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 1
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => c_longword_w/c_data_w,
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 1,
+ g_pipeline_ready => TRUE -- Needed for src_in.ready to snk_out.ready.
)
PORT MAP (
rst => dp_rst,
@@ -213,7 +221,8 @@ BEGIN
remote_sosi => from_ri_sosi,
local_sosi => local_sosi,
- mux_sosi => ring_mux_sosi
+ mux_sosi => ring_mux_sosi,
+ mux_siso => ring_mux_siso
);
to_ri_sosi <= ring_mux_sosi;
@@ -223,16 +232,18 @@ BEGIN
---------------------------------------------------------------
u_dp_repack_data_rx : ENTITY dp_lib.dp_repack_data
GENERIC MAP (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 1,
- g_out_dat_w => c_data_w,
- g_out_nof_words => c_longword_w/c_data_w
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 1,
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => c_longword_w/c_data_w,
+ g_pipeline_ready => TRUE -- Needed for src_in.ready to snk_out.ready.
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => ring_mux_sosi,
+ snk_out => ring_mux_siso,
src_out => rx_sosi
);
@@ -243,15 +254,17 @@ BEGIN
GENERIC MAP (
g_mode => 0,
g_nof_output => g_P_sq,
- g_remove_channel_lo => FALSE
+ g_remove_channel_lo => FALSE,
+ g_sel_ctrl_invert => TRUE --TRUE when indexed (g_nof_input-1 DOWNTO 0)
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => rx_sosi,
- src_out_arr => dispatch_sosi_arr
+ src_out_arr => dispatch_invert_sosi_arr
);
+ dispatch_sosi_arr <= func_dp_stream_arr_reverse_range(dispatch_invert_sosi_arr);
---------------------------------------------------------------
-- dp_bsn_aligner_v2
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 71f21d3af762da9c2cb40f337554d1f3000899e5..1494eb112642c4e85e5401299cdf9c7dd2d97299 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -345,7 +345,7 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
CONSTANT c_use_dp_layer : BOOLEAN := TRUE;
- CONSTANT c_lane_packet_length : NATURAL := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size; -- = 48 longwords per packet, so the maximum data rate with a packetrate of 195312.5 and all 16 nodes combined = 16 * 48 / 1024 * 64 * 200M = 9.6 Gb/s
+ CONSTANT c_lane_packet_length : NATURAL := c_sdp_N_crosslets_max * c_sdp_S_pn / 2; -- = crosslet subband select block size devided by 2 as it is repacked from 32b to 64b.
CONSTANT c_err_bi : NATURAL := 0;
CONSTANT c_nof_err_counts : NATURAL := 8;
CONSTANT c_bsn_at_sync_check_channel : NATURAL := 1;
@@ -359,7 +359,7 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_qsfp_if_offset : NATURAL := 0; -- QSFP signals are indexed at c_nof_if * I.
CONSTANT c_ring_0_if_offset : NATURAL := 1; -- RING_0 signals are indexed at c_nof_if * I + 1.
CONSTANT c_ring_1_if_offset : NATURAL := 2; -- RING_1 signals are indexed at c_nof_if * I + 2.
- CONSTANT c_nof_mac : NATURAL := 3; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
+ CONSTANT c_nof_mac : NATURAL := 3; -- must match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
SIGNAL gn_index : NATURAL := 0;
SIGNAL this_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
@@ -405,6 +405,7 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL bs_sosi : t_dp_sosi;
SIGNAL xst_from_ri_sosi : t_dp_sosi;
SIGNAL xst_to_ri_sosi : t_dp_sosi;
@@ -635,6 +636,8 @@ BEGIN
from_ri_sosi => xst_from_ri_sosi,
to_ri_sosi => xst_to_ri_sosi,
+
+ bs_sosi => bs_sosi,
mm_rst => mm_rst,
mm_clk => mm_clk,
@@ -697,7 +700,7 @@ BEGIN
lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
- bs_sosi => fsub_sosi_arr(0), -- used for bsn and sync
+ bs_sosi => bs_sosi,
reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 2313b1f23bf3155653da5728c03d0de13e930238..bb68ec65424a5349d2a0a45874e7ce327c0f40c2 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -106,6 +106,26 @@ peripherals:
access_mode: RW
+ - peripheral_name: dp_bsn_align_v2 # pi_dp_bsn_align_v2.py
+ peripheral_description: "Align frames from multiple input streams."
+ parameters:
+ # Parameters of dp_bsn_align_v2.vhd
+ - { name: g_nof_streams, value: 2 }
+ mm_ports:
+ # MM port for dp_bsn_align_v2.vhd
+ - mm_port_name: REG_DP_BSN_ALIGN_V2
+ mm_port_type: REG
+ mm_port_span: 1 * MM_BUS_SIZE
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
+ fields:
+ - - field_name: enable
+ field_description: "Stream enable per stream via bits g_nof_streams-1 : 0. Bit value 0 disables the stream, 1 enables the stream. Disabled streams are not aligned."
+ address_offset: 0x0
+ mm_width: 1
+ access_mode: RW
+
+
- peripheral_name: dp_bsn_source # pi_dp_bsn_source.py
peripheral_description: "Block Sequence Number (BSN) source for timestamping blocks of data samples."
parameters:
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index 7de022f5ddf319ca778a479bd3eef82fe24e54fc..42e3ae8e6b817d4346abe9a6b7b565882ccb334e 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -170,6 +170,12 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
(OTHERS=>'0'),
(OTHERS=>(OTHERS=>'0')));
+ CONSTANT c_comb_rst : t_comb := (c_dp_sosi_rst,
+ (OTHERS=>'0'),
+ (OTHERS=>'0'),
+ (OTHERS=>'0'),
+ (OTHERS=>c_dp_sosi_rst));
+
-- State registers for p_comb
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
@@ -219,10 +225,11 @@ BEGIN
END IF;
END PROCESS;
- p_comb : PROCESS(r, in_sosi_arr_p, mm_copi, dp_copi, rd_cipo_arr, rd_sosi_arr)
+ p_comb : PROCESS(r, in_sosi_arr_p, mm_copi, dp_copi, rd_cipo_arr, rd_sosi_arr, stream_en_arr, node_index)
VARIABLE v : t_reg; -- State variable
VARIABLE w : t_comb; -- Local wires = memoryless auxiliary variables
BEGIN
+ w := c_comb_rst;
v := r; -- state signals
v.mm_sosi := func_dp_stream_reset_control(r.mm_sosi);
v.wr_copi_arr := RESET_MEM_COPI_CTRL(r.wr_copi_arr);
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index cd8c20ec66c1124a89b45a2f99b40819aabf776b..567febceb63d61ae93d9c3849dda19bab16a1cc6 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -251,6 +251,7 @@ BEGIN
-- No need to transfer eop counter across clock domains for single clock
ELSE
+ wr_eop_busy <= '0'; -- To prevent inferred latch.
IF snk_in.eop = '1' THEN
wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
ELSE
diff --git a/libraries/base/dp/src/vhdl/dp_repack_data.vhd b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
index 7d777a1eb84ae0581610d88a00bccaaa188151b6..d1c86bf258f14795eaa5ea49ddc9007a12fe1dc3 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
@@ -650,7 +650,7 @@ ENTITY dp_repack_data IS
g_out_dat_w : NATURAL;
g_out_nof_words : NATURAL;
g_out_symbol_w : NATURAL := 1; -- default 1 for src_out.empty in nof bits, else use power of 2
- g_pipeline_ready : BOOLEAN := FALSE
+ g_pipeline_ready : BOOLEAN := FALSE -- TRUE to pipeline ready from src_in to snk_out.
);
PORT (
rst : IN STD_LOGIC;
diff --git a/libraries/base/ring/src/vhdl/ring_tx.vhd b/libraries/base/ring/src/vhdl/ring_tx.vhd
index dc59d98b3b0d7aa5131f473d88180689ac28584a..742d0718311ea66c1282e681453b28cda147324a 100644
--- a/libraries/base/ring/src/vhdl/ring_tx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_tx.vhd
@@ -116,7 +116,7 @@ BEGIN
END GENERATE;
-- increase channel by 1, e.g. add 1 hop.
- p_hop: PROCESS(validated_sosi)
+ p_hop: PROCESS(validated_sosi, N_rn)
BEGIN
tx_sosi <= validated_sosi;
IF TO_UINT(validated_sosi.channel) >= TO_UINT(N_rn)-1 THEN