diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index f3e4e4b2d97fa980873117ab92453b46d3e4694e..6b6d9532aadc69e34cd7257fa1a3a0ba68fe97bc 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -27,7 +27,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE tech_mult_component_pkg IS
-----------------------------------------------------------------------------
- -- complex mult stratixiv ip component
+ -- Stratix IV components
-----------------------------------------------------------------------------
COMPONENT ip_stratixiv_complex_mult IS
@@ -44,9 +44,6 @@ PACKAGE tech_mult_component_pkg IS
result_real : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
- -----------------------------------------------------------------------------
- -- complex mult stratixiv rtl component
- -----------------------------------------------------------------------------
COMPONENT ip_stratixiv_complex_mult_rtl IS
GENERIC (
@@ -72,59 +69,6 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
- -----------------------------------------------------------------------------
- -- mult arria 10 ip component
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_mult IS
- GENERIC (
- g_in_a_w : POSITIVE := 18; -- Width of the data A port
- g_in_b_w : POSITIVE := 18; -- Width of the data B port
- g_out_p_w : POSITIVE := 36; -- Width of the result port
- g_nof_mult : POSITIVE := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
- g_pipeline_input : NATURAL := 1; -- 0 or 1
- g_pipeline_product : NATURAL := 1; -- 0 or 1
- g_pipeline_output : NATURAL := 1; -- >= 0
- g_representation : STRING := "SIGNED" -- or "UNSIGNED"
- );
- PORT (
- clk : IN STD_LOGIC;
- clken : IN STD_LOGIC := '1';
- in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
- in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
- out_p : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- mult arria 10 rtl component
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_mult_rtl IS
- GENERIC (
- g_in_a_w : POSITIVE := 18;
- g_in_b_w : POSITIVE := 18;
- g_out_p_w : POSITIVE := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
- g_nof_mult : POSITIVE := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
- g_pipeline_input : NATURAL := 1; -- 0 or 1
- g_pipeline_product : NATURAL := 1; -- 0 or 1
- g_pipeline_output : NATURAL := 1; -- >= 0
- g_representation : STRING := "SIGNED" -- or "UNSIGNED"
- );
- PORT (
- rst : IN STD_LOGIC;
- clk : IN STD_LOGIC;
- clken : IN STD_LOGIC := '1';
- in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
- in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
- out_p : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- mult stratixiv ip component
- -----------------------------------------------------------------------------
-
COMPONENT ip_stratixiv_mult IS
GENERIC (
g_in_a_w : POSITIVE := 18;
@@ -145,10 +89,6 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
- -----------------------------------------------------------------------------
- -- mult stratixiv rtl component
- -----------------------------------------------------------------------------
-
COMPONENT ip_stratixiv_mult_rtl IS
GENERIC (
g_in_a_w : POSITIVE := 18;
@@ -171,7 +111,7 @@ PACKAGE tech_mult_component_pkg IS
END COMPONENT;
-----------------------------------------------------------------------------
- -- arria10 ip component
+ -- Arria 10 components
-----------------------------------------------------------------------------
COMPONENT ip_arria10_complex_mult is
@@ -188,10 +128,6 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
- -----------------------------------------------------------------------------
- -- arria10 rtl component
- -----------------------------------------------------------------------------
-
COMPONENT ip_arria10_complex_mult_rtl IS
GENERIC (
g_in_a_w : POSITIVE := 18;
@@ -216,4 +152,45 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_mult IS
+ GENERIC (
+ g_in_a_w : POSITIVE := 18; -- Width of the data A port
+ g_in_b_w : POSITIVE := 18; -- Width of the data B port
+ g_out_p_w : POSITIVE := 36; -- Width of the result port
+ g_nof_mult : POSITIVE := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 1; -- 0 or 1
+ g_pipeline_output : NATURAL := 1; -- >= 0
+ g_representation : STRING := "SIGNED" -- or "UNSIGNED"
+ );
+ PORT (
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ out_p : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_mult_rtl IS
+ GENERIC (
+ g_in_a_w : POSITIVE := 18;
+ g_in_b_w : POSITIVE := 18;
+ g_out_p_w : POSITIVE := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+ g_nof_mult : POSITIVE := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 1; -- 0 or 1
+ g_pipeline_output : NATURAL := 1; -- >= 0
+ g_representation : STRING := "SIGNED" -- or "UNSIGNED"
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ out_p : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_mult_component_pkg;