From a26d62cf4f2be091199d4ac02aeb76cef9ccd71c Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 12 Feb 2015 13:17:08 +0000
Subject: [PATCH] Use MM reg size constants from diag_pkg.vhd.
---
libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd | 7 ++++---
libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd | 7 ++++---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index 881a2cd8c4..60d30d9ba3 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -71,6 +71,7 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE work.diag_pkg.ALL;
ENTITY mms_diag_rx_seq IS
GENERIC (
@@ -99,9 +100,9 @@ ARCHITECTURE str OF mms_diag_rx_seq IS
-- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 3,
+ adr_w => c_diag_seq_rx_reg_adr_w, -- = 2
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_rx_reg_nof_dat, -- = 3
init_sl => '0');
CONSTANT c_reg_slv_w : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 9e5c5e6a6b..995f573ed0 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -71,6 +71,7 @@ USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE work.diag_pkg.ALL;
ENTITY mms_diag_tx_seq IS
GENERIC (
@@ -100,9 +101,9 @@ ARCHITECTURE str OF mms_diag_tx_seq IS
-- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 3,
+ adr_w => c_diag_seq_tx_reg_adr_w, -- = 2
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_tx_reg_nof_dat, -- = 3
init_sl => '0');
CONSTANT c_reg_slv_w : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;
--
GitLab