diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index 881a2cd8c425f6b36e31d27336ebcdd63feaffcb..60d30d9ba39832b519995708e77f8e56e32f54ef 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -71,6 +71,7 @@ USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE work.diag_pkg.ALL;
 
 ENTITY mms_diag_rx_seq IS
   GENERIC (
@@ -99,9 +100,9 @@ ARCHITECTURE str OF mms_diag_rx_seq IS
 
   -- Define the actual size of the MM slave register
   CONSTANT c_mm_reg      : t_c_mem  := (latency  => 1,
-                                        adr_w    => 2,
-                                        dat_w    => c_word_w,       -- Use MM bus data width = c_word_w = 32 for all MM registers
-                                        nof_dat  => 3,
+                                        adr_w    => c_diag_seq_rx_reg_adr_w,    -- = 2
+                                        dat_w    => c_word_w,                   -- Use MM bus data width = c_word_w = 32 for all MM registers
+                                        nof_dat  => c_diag_seq_rx_reg_nof_dat,  -- = 3
                                         init_sl  => '0');
   
   CONSTANT c_reg_slv_w   : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 9e5c5e6a6bf0bd79347b080bc4d50c39ade4efdd..995f573ed0c2eff323cc4cb713e76aa25b30ba58 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -71,6 +71,7 @@ USE IEEE.std_logic_1164.ALL;
 USE common_lib.common_pkg.ALL; 
 USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE work.diag_pkg.ALL;
 
 ENTITY mms_diag_tx_seq IS
   GENERIC (
@@ -100,9 +101,9 @@ ARCHITECTURE str OF mms_diag_tx_seq IS
   
   -- Define the actual size of the MM slave register
   CONSTANT c_mm_reg      : t_c_mem  := (latency  => 1,
-                                        adr_w    => 2,
-                                        dat_w    => c_word_w,       -- Use MM bus data width = c_word_w = 32 for all MM registers
-                                        nof_dat  => 3,
+                                        adr_w    => c_diag_seq_tx_reg_adr_w,    -- = 2
+                                        dat_w    => c_word_w,                   -- Use MM bus data width = c_word_w = 32 for all MM registers
+                                        nof_dat  => c_diag_seq_tx_reg_nof_dat,  -- = 3
                                         init_sl  => '0');
 
   CONSTANT c_reg_slv_w   : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;