From a257ff6668889d8368549a8dbba2cf998797a3dc Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Wed, 18 Nov 2015 11:17:16 +0000
Subject: [PATCH] Changed stratix4 ip names to generic ip
---
.../tb/vhdl/tb_common_complex_mult.vhd | 121 +++++++++---------
.../common_mult/tb/vhdl/tb_common_mult.vhd | 92 ++++++-------
2 files changed, 106 insertions(+), 107 deletions(-)
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index 9535114734..c835646c87 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -50,48 +50,48 @@ END tb_common_complex_mult;
ARCHITECTURE tb OF tb_common_complex_mult IS
- CONSTANT clk_period : TIME := 10 ns;
- CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
-
- CONSTANT c_max : INTEGER := 2**(g_in_dat_w-1)-1;
- CONSTANT c_min : INTEGER := -2**(g_in_dat_w-1);
-
- CONSTANT c_technology : NATURAL := c_tech_select_default;
-
- SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL rst : STD_LOGIC;
- SIGNAL clk : STD_LOGIC := '0';
-
- SIGNAL random : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
-
- SIGNAL in_ar : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
- SIGNAL in_ai : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
- SIGNAL in_br : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
- SIGNAL in_bi : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
-
- SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val
- SIGNAL result_val_expected : STD_LOGIC;
- SIGNAL result_val_rtl : STD_LOGIC;
- SIGNAL result_val_stratix4 : STD_LOGIC;
-
- SIGNAL out_result_re : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- combinatorial result
- SIGNAL out_result_im : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined results
- SIGNAL result_re_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ CONSTANT clk_period : TIME := 10 ns;
+ CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
+
+ CONSTANT c_max : INTEGER := 2**(g_in_dat_w-1)-1;
+ CONSTANT c_min : INTEGER := -2**(g_in_dat_w-1);
+
+ CONSTANT c_technology : NATURAL := c_tech_select_default;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL clk : STD_LOGIC := '0';
+
+ SIGNAL random : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
+
+ SIGNAL in_ar : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+ SIGNAL in_ai : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+ SIGNAL in_br : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+ SIGNAL in_bi : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+
+ SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val
+ SIGNAL result_val_expected : STD_LOGIC;
+ SIGNAL result_val_rtl : STD_LOGIC;
+ SIGNAL result_val_ip : STD_LOGIC;
+
+ SIGNAL out_result_re : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- combinatorial result
+ SIGNAL out_result_im : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_re_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined results
+ SIGNAL result_re_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_re_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_im_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_im_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_im_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
BEGIN
clk <= (NOT clk) OR tb_end AFTER clk_period/2;
-
+
random <= func_common_random(random) WHEN rising_edge(clk);
-
+
in_val <= random(random'HIGH);
-
+
-- run -all
p_in_stimuli : PROCESS
BEGIN
@@ -108,7 +108,7 @@ BEGIN
FOR I IN 0 TO 9 LOOP
WAIT UNTIL rising_edge(clk);
END LOOP;
-
+
-- Some special combinations
in_ar <= TO_SVEC(2, g_in_dat_w);
in_ai <= TO_SVEC(4, g_in_dat_w);
@@ -140,11 +140,11 @@ BEGIN
in_br <= TO_SVEC(-c_max, g_in_dat_w);
in_bi <= TO_SVEC(-c_max, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
-
+
FOR I IN 0 TO 49 LOOP
WAIT UNTIL rising_edge(clk);
END LOOP;
-
+
-- All combinations
FOR I IN -c_max TO c_max LOOP
FOR J IN -c_max TO c_max LOOP
@@ -159,19 +159,19 @@ BEGIN
END LOOP;
END LOOP;
END LOOP;
-
+
FOR I IN 0 TO 49 LOOP
WAIT UNTIL rising_edge(clk);
END LOOP;
-
+
tb_end <= '1';
WAIT;
END PROCESS;
-
+
-- Expected combinatorial complex multiply out_result
out_result_re <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "RE", g_out_dat_w);
out_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", g_out_dat_w);
-
+
u_result_re : ENTITY common_lib.common_pipeline
GENERIC MAP (
g_representation => "SIGNED",
@@ -187,7 +187,7 @@ BEGIN
in_dat => out_result_re,
out_dat => result_re_expected
);
-
+
u_result_im : ENTITY common_lib.common_pipeline
GENERIC MAP (
g_representation => "SIGNED",
@@ -203,7 +203,7 @@ BEGIN
in_dat => out_result_im,
out_dat => result_im_expected
);
-
+
u_result_val_expected : ENTITY common_lib.common_pipeline_sl
GENERIC MAP (
g_pipeline => c_pipeline,
@@ -216,7 +216,7 @@ BEGIN
in_dat => in_val,
out_dat => result_val_expected
);
-
+
u_dut_rtl : ENTITY work.common_complex_mult
GENERIC MAP (
g_technology => c_technology,
@@ -243,8 +243,8 @@ BEGIN
out_pi => result_im_rtl,
out_val => result_val_rtl
);
-
- u_dut_stratix4 : ENTITY work.common_complex_mult
+
+ u_dut_ip : ENTITY work.common_complex_mult
GENERIC MAP (
g_technology => c_technology,
g_variant => "IP",
@@ -266,26 +266,25 @@ BEGIN
in_br => in_br,
in_bi => in_bi,
in_val => in_val,
- out_pr => result_re_stratix4,
- out_pi => result_im_stratix4,
- out_val => result_val_stratix4
+ out_pr => result_re_ip,
+ out_pi => result_im_ip,
+ out_val => result_val_ip
);
-
-
+
p_verify : PROCESS(rst, clk)
BEGIN
IF rst='0' THEN
IF rising_edge(clk) THEN
- ASSERT result_re_rtl = result_re_expected REPORT "Error: RE wrong RTL result" SEVERITY ERROR;
- ASSERT result_im_rtl = result_im_expected REPORT "Error: IM wrong RTL result" SEVERITY ERROR;
- ASSERT result_val_rtl = result_val_expected REPORT "Error: VAL wrong RTL result" SEVERITY ERROR;
-
- ASSERT result_re_stratix4 = result_re_expected REPORT "Error: RE wrong stratix4 result" SEVERITY ERROR;
- ASSERT result_im_stratix4 = result_im_expected REPORT "Error: IM wrong stratix4 result" SEVERITY ERROR;
- ASSERT result_val_stratix4 = result_val_expected REPORT "Error: VAL wrong stratix4 result" SEVERITY ERROR;
-
+ ASSERT result_re_rtl = result_re_expected REPORT "Error: RE wrong RTL result" SEVERITY ERROR;
+ ASSERT result_im_rtl = result_im_expected REPORT "Error: IM wrong RTL result" SEVERITY ERROR;
+ ASSERT result_val_rtl = result_val_expected REPORT "Error: VAL wrong RTL result" SEVERITY ERROR;
+
+ ASSERT result_re_ip = result_re_expected REPORT "Error: RE wrong IP result" SEVERITY ERROR;
+ ASSERT result_im_ip = result_im_expected REPORT "Error: IM wrong IP result" SEVERITY ERROR;
+ ASSERT result_val_ip = result_val_expected REPORT "Error: VAL wrong IP result" SEVERITY ERROR;
+
END IF;
END IF;
END PROCESS;
-
+
END tb;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
index a4fd43d7df..61dfb1ae23 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
@@ -50,11 +50,11 @@ ARCHITECTURE tb OF tb_common_mult IS
CONSTANT clk_period : TIME := 10 ns;
CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_output;
CONSTANT c_nof_mult : NATURAL := 2; -- fixed
-
+
CONSTANT c_max_p : INTEGER := 2**(g_in_dat_w-1)-1;
CONSTANT c_min : INTEGER := -c_max_p;
CONSTANT c_max_n : INTEGER := -2**(g_in_dat_w-1);
-
+
CONSTANT c_technology : NATURAL := c_tech_select_default;
FUNCTION func_sresult(in_a, in_b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
@@ -64,8 +64,8 @@ ARCHITECTURE tb OF tb_common_mult IS
VARIABLE v_result : SIGNED(c_res_w-1 DOWNTO 0);
BEGIN
-- Calculate expected result
- v_a := RESIZE_SVEC(in_a, g_in_dat_w);
- v_b := RESIZE_SVEC(in_b, g_in_dat_w);
+ v_a := RESIZE_SVEC(in_a, g_in_dat_w);
+ v_b := RESIZE_SVEC(in_b, g_in_dat_w);
v_result := RESIZE_NUM(SIGNED(v_a)*SIGNED(v_b), c_res_w);
RETURN RESIZE_SVEC(STD_LOGIC_VECTOR(v_result), g_out_dat_w); -- Truncate MSbits or sign extend MSBits
END;
@@ -77,30 +77,30 @@ ARCHITECTURE tb OF tb_common_mult IS
VARIABLE v_result : UNSIGNED(c_res_w-1 DOWNTO 0);
BEGIN
-- Calculate expected result
- v_a := RESIZE_UVEC(in_a, g_in_dat_w);
- v_b := RESIZE_UVEC(in_b, g_in_dat_w);
+ v_a := RESIZE_UVEC(in_a, g_in_dat_w);
+ v_b := RESIZE_UVEC(in_b, g_in_dat_w);
v_result := RESIZE_NUM(UNSIGNED(v_a)*UNSIGNED(v_b), c_res_w);
RETURN RESIZE_UVEC(STD_LOGIC_VECTOR(v_result), g_out_dat_w); -- Truncate MSbits or zero extend MSBits
END;
-
+
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '0';
SIGNAL tb_end : STD_LOGIC := '0';
-
+
-- Input signals
SIGNAL in_a : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_b : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_a_p : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_b_p : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
- -- Product signals
+ -- Product signals
SIGNAL sresult_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined expected result
SIGNAL sresult_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL sresult_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL sresult_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL uresult_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined expected result
SIGNAL uresult_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL uresult_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
-
+ SIGNAL uresult_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+
-- auxiliary signals
SIGNAL in_a_arr : STD_LOGIC_VECTOR(g_nof_mult*g_in_dat_w-1 DOWNTO 0);
SIGNAL in_b_arr : STD_LOGIC_VECTOR(g_nof_mult*g_in_dat_w-1 DOWNTO 0);
@@ -110,13 +110,13 @@ ARCHITECTURE tb OF tb_common_mult IS
SIGNAL uresult_arr_expected : STD_LOGIC_VECTOR(g_nof_mult*g_out_dat_w-1 DOWNTO 0);
SIGNAL sresult_arr_rtl : STD_LOGIC_VECTOR(g_nof_mult*g_out_dat_w-1 DOWNTO 0);
SIGNAL uresult_arr_rtl : STD_LOGIC_VECTOR(g_nof_mult*g_out_dat_w-1 DOWNTO 0);
- SIGNAL sresult_arr_stratix4 : STD_LOGIC_VECTOR(g_nof_mult*g_out_dat_w-1 DOWNTO 0);
- SIGNAL uresult_arr_stratix4 : STD_LOGIC_VECTOR(g_nof_mult*g_out_dat_w-1 DOWNTO 0);
-
+ SIGNAL sresult_arr_ip : STD_LOGIC_VECTOR(g_nof_mult*g_out_dat_w-1 DOWNTO 0);
+ SIGNAL uresult_arr_ip : STD_LOGIC_VECTOR(g_nof_mult*g_out_dat_w-1 DOWNTO 0);
+
BEGIN
clk <= NOT clk OR tb_end AFTER clk_period/2;
-
+
-- run 1 us
p_in_stimuli : PROCESS
BEGIN
@@ -126,7 +126,7 @@ BEGIN
proc_common_wait_some_cycles(clk, 10);
rst <= '0';
proc_common_wait_some_cycles(clk, 10);
-
+
-- Some special combinations
in_a <= TO_SVEC(2, g_in_dat_w);
in_b <= TO_SVEC(3, g_in_dat_w);
@@ -146,9 +146,9 @@ BEGIN
in_a <= TO_SVEC(c_max_n, g_in_dat_w); -- -p*(-p-1) = pp + p
in_b <= TO_SVEC(c_min, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
-
+
proc_common_wait_some_cycles(clk, 50);
-
+
-- All combinations
FOR I IN -2**(g_in_dat_w-1) TO 2**(g_in_dat_w-1)-1 LOOP
FOR J IN -2**(g_in_dat_w-1) TO 2**(g_in_dat_w-1)-1 LOOP
@@ -157,12 +157,12 @@ BEGIN
WAIT UNTIL rising_edge(clk);
END LOOP;
END LOOP;
-
+
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
WAIT;
END PROCESS;
-
+
-- pipeline inputs to ease comparison in the Wave window
u_in_a_pipeline : ENTITY common_lib.common_pipeline
GENERIC MAP (
@@ -179,7 +179,7 @@ BEGIN
in_dat => in_a,
out_dat => in_a_p
);
-
+
u_in_b_pipeline : ENTITY common_lib.common_pipeline
GENERIC MAP (
g_representation => "SIGNED",
@@ -195,7 +195,7 @@ BEGIN
in_dat => in_b,
out_dat => in_b_p
);
-
+
gen_wires : FOR I IN 0 TO g_nof_mult-1 GENERATE
-- use same input for all multipliers
in_a_arr((I+1)*g_in_dat_w-1 DOWNTO I*g_in_dat_w) <= in_a;
@@ -207,13 +207,13 @@ BEGIN
sresult_arr_expected((I+1)*g_out_dat_w-1 DOWNTO I*g_out_dat_w) <= sresult_expected;
uresult_arr_expected((I+1)*g_out_dat_w-1 DOWNTO I*g_out_dat_w) <= uresult_expected;
END GENERATE;
-
+
-- use mult(0) to observe result in Wave window
- sresult_rtl <= sresult_arr_rtl(g_out_dat_w-1 DOWNTO 0);
- uresult_rtl <= uresult_arr_rtl(g_out_dat_w-1 DOWNTO 0);
- sresult_stratix4 <= sresult_arr_stratix4(g_out_dat_w-1 DOWNTO 0);
- uresult_stratix4 <= uresult_arr_stratix4(g_out_dat_w-1 DOWNTO 0);
-
+ sresult_rtl <= sresult_arr_rtl(g_out_dat_w-1 DOWNTO 0);
+ uresult_rtl <= uresult_arr_rtl(g_out_dat_w-1 DOWNTO 0);
+ sresult_ip <= sresult_arr_ip(g_out_dat_w-1 DOWNTO 0);
+ uresult_ip <= uresult_arr_ip(g_out_dat_w-1 DOWNTO 0);
+
u_sresult : ENTITY common_lib.common_pipeline
GENERIC MAP (
g_representation => "SIGNED",
@@ -229,7 +229,7 @@ BEGIN
in_dat => out_sresult,
out_dat => sresult_expected
);
-
+
u_uresult : ENTITY common_lib.common_pipeline
GENERIC MAP (
g_representation => "UNSIGNED",
@@ -245,7 +245,7 @@ BEGIN
in_dat => out_uresult,
out_dat => uresult_expected
);
-
+
u_sdut_rtl : ENTITY work.common_mult
GENERIC MAP (
g_technology => c_technology,
@@ -266,8 +266,8 @@ BEGIN
in_a => in_a_arr,
in_b => in_b_arr,
out_p => sresult_arr_rtl
- );
-
+ );
+
u_udut_rtl : ENTITY work.common_mult
GENERIC MAP (
g_technology => c_technology,
@@ -288,9 +288,9 @@ BEGIN
in_a => in_a_arr,
in_b => in_b_arr,
out_p => uresult_arr_rtl
- );
-
- u_sdut_stratix4 : ENTITY work.common_mult
+ );
+
+ u_sdut_ip : ENTITY work.common_mult
GENERIC MAP (
g_technology => c_technology,
g_variant => "IP",
@@ -309,10 +309,10 @@ BEGIN
clken => '1',
in_a => in_a_arr,
in_b => in_b_arr,
- out_p => sresult_arr_stratix4
+ out_p => sresult_arr_ip
);
-
- u_udut_stratix4 : ENTITY work.common_mult
+
+ u_udut_ip : ENTITY work.common_mult
GENERIC MAP (
g_technology => c_technology,
g_variant => "IP",
@@ -331,20 +331,20 @@ BEGIN
clken => '1',
in_a => in_a_arr,
in_b => in_b_arr,
- out_p => uresult_arr_stratix4
+ out_p => uresult_arr_ip
);
-
+
p_verify : PROCESS(rst, clk)
BEGIN
IF rst='0' THEN
IF rising_edge(clk) THEN
-- verify all multipliers in parallel
- ASSERT sresult_arr_rtl = sresult_arr_expected REPORT "Error: wrong Signed RTL result" SEVERITY ERROR;
- ASSERT uresult_arr_rtl = uresult_arr_expected REPORT "Error: wrong Unsigned RTL result" SEVERITY ERROR;
- ASSERT sresult_arr_stratix4 = sresult_arr_expected REPORT "Error: wrong Signed stratix4 result" SEVERITY ERROR;
- ASSERT uresult_arr_stratix4 = uresult_arr_expected REPORT "Error: wrong Unsigned stratix4 result" SEVERITY ERROR;
+ ASSERT sresult_arr_rtl = sresult_arr_expected REPORT "Error: wrong Signed RTL result" SEVERITY ERROR;
+ ASSERT uresult_arr_rtl = uresult_arr_expected REPORT "Error: wrong Unsigned RTL result" SEVERITY ERROR;
+ ASSERT sresult_arr_ip = sresult_arr_expected REPORT "Error: wrong Signed IP result" SEVERITY ERROR;
+ ASSERT uresult_arr_ip = uresult_arr_expected REPORT "Error: wrong Unsigned IP result" SEVERITY ERROR;
END IF;
END IF;
END PROCESS;
-
+
END tb;
--
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