diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
index cc324b02be20e218e80fb36a349df2316361e4d6..de95f06df8c346c6d4cad59940d90493abf1f8fb 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
@@ -41,11 +41,11 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY ddrctrl_address_counter IS
GENERIC (
- g_tech_ddr : t_c_tech_ddr;
+ g_tech_ddr : t_c_tech_ddr;
g_sim_model : BOOLEAN := TRUE
);
PORT (
- clk : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi;
out_mosi : OUT t_mem_ctlr_mosi
@@ -55,11 +55,11 @@ END ddrctrl_address_counter;
ARCHITECTURE rtl OF ddrctrl_address_counter IS
- CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
- CONSTANT c_adr_w : NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); --27;
- CONSTANT c_max_adr: NATURAL := 2**(c_adr_w) - 1;
+ CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
+ CONSTANT c_adr_w : NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); --27;
+ CONSTANT c_max_adr : NATURAL := 2**(c_adr_w) - 1;
- SIGNAL s_adr : NATURAL range 0 to 2**(c_adr_w)-1 := 0;
+ SIGNAL s_adr : NATURAL range 0 to 2**(c_adr_w)-1 := 0;
BEGIN
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
index 1e6105a8f9db8f07013b01e0f3ebb29e2a7ac522..079a5d2144326a747c5536b0f0cca957143bc438 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
@@ -61,11 +61,15 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
BEGIN
- in_sosi.data(c_data_w - 1 DOWNTO 0) <= in_data(c_data_w - 1 DOWNTO 0);
- in_sosi.valid <= in_data_enable;
-
+ -- if these ASSERT's get uncommented u can see that modelsim does take a few itteration before the warning gets asserted. These asserts are also present in p_verify
+ --ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR; -- gives error if in_sosi and out_mosi do not match
+ --ASSERT in_sosi.valid = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
+ --ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) /= out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does match out_mosi.wrdata" SEVERITY WARNING; -- gives warning if in_sosi and out_mosi do match
+ --ASSERT in_sosi.valid /= out_mosi.wr REPORT "in_sosi.valid does match out_mosi.wr" SEVERITY WARNING;
+ in_sosi.data(c_data_w - 1 DOWNTO 0) <= in_data(c_data_w - 1 DOWNTO 0);
+ in_sosi.valid <= in_data_enable;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
@@ -81,15 +85,12 @@ BEGIN
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*10;
- ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "Wrong wrdata 1" SEVERITY ERROR;
- ASSERT in_sosi.valid = out_mosi.wr REPORT "Wrong wr 1" SEVERITY ERROR;
-
FOR I IN 0 TO 6 LOOP
- in_data_enable <= '1';
- in_data <= NOT in_data;
- ASSERT I = TO_UINT(out_mosi.address) REPORT "Wrong address 1" SEVERITY ERROR;
+ in_data_enable <= '1';
+ in_data <= NOT in_data;
+ ASSERT I = TO_UINT(out_mosi.address) REPORT "Wrong address, I = " & NATURAL'image(I) SEVERITY ERROR;
WAIT FOR c_clk_period*1;
- in_data_enable <= '0';
+ in_data_enable <= '0';
WAIT FOR c_clk_period*2;
END LOOP;
@@ -100,19 +101,30 @@ BEGIN
WAIT FOR c_clk_period*1;
FOR I IN 0 TO 20 LOOP
- ASSERT I = TO_UINT(out_mosi.address) OR I - c_max_adr = TO_UINT(out_mosi.address) REPORT "Wrong address, I = " & NATURAL'image(I) SEVERITY ERROR;
- in_data_enable <= '1';
- in_data <= NOT in_data;
+ ASSERT I = TO_UINT(out_mosi.address) OR I - c_max_adr = TO_UINT(out_mosi.address) REPORT "Wrong address, I = " & NATURAL'image(I) SEVERITY ERROR;
+ in_data_enable <= '1';
+ in_data <= NOT in_data;
WAIT FOR c_clk_period*1;
- in_data_enable <= '0';
+ in_data_enable <= '0';
WAIT FOR c_clk_period*2;
END LOOP;
WAIT FOR c_clk_period*20;
- tb_end <= '1';
-
+ tb_end <= '1';
WAIT;
+
+ END PROCESS;
+
+ p_verify : PROCESS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ IF rising_edge(clk) THEN
+ ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR; -- gives error if in_sosi and out_mosi do not match
+ ASSERT in_sosi.valid = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
+ --ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) /= out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does match out_mosi.wrdata" SEVERITY WARNING; -- gives warning if in_sosi and out_mosi do match
+ --ASSERT in_sosi.valid /= out_mosi.wr REPORT "in_sosi.valid does match out_mosi.wr" SEVERITY WARNING;
+ END IF;
END PROCESS;
u_address_counter : ENTITY work.ddrctrl_address_counter