diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 96e3c42900bd80357dc8c4f7ef22ca834fa67a6e..77501b43b2fd78bdc0690189682e352ae11ff8c6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -86,9 +86,9 @@ ENTITY node_adc_input_and_timing IS
     reg_bsn_monitor_input_miso     : OUT t_mem_miso;
 
     -- Data buffer for raw samples
-    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi := c_mem_mosi_rst;
     ram_diag_data_buf_jesd_miso    : OUT t_mem_miso;
-    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi := c_mem_mosi_rst;
     reg_diag_data_buf_jesd_miso    : OUT t_mem_miso;
 
     -- Data buffer for framed samples (variable depth)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
index 663aefa26a6996293774b50364c5429a2efc5a7d..81ed7b897acde801e0f918df397a0c1b13e115be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
@@ -19,6 +19,7 @@ synth_files =
     src/vhdl/lofar2_unb2b_sdp_station.vhd
     
 test_bench_files = 
+    tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
 
 regression_test_vhdl =
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index aa7cf53417e5b347abe994b5f08a323ae2d61e78..11c42ec5f03a957940d2fe69532d4d3f934c402e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -132,14 +132,14 @@ peripherals:
     parameter_overrides:
       - { name: g_nof_streams, value: c_S_pn }
     mm_port_names:
-      - REG_DIAG_WG
-      - RAM_DIAG_WG
+      - REG_WG
+      - RAM_WG
       
   - peripheral_name: aduh/aduh_mon_dc_power
     parameter_overrides:
       - { name: g_nof_streams, value: c_S_pn }
     mm_port_names:
-      - REG_ADUH_MON
+      - REG_ADUH_MONITOR
 
   # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
   #- peripheral_name: aduh/aduh_mon_data_buffer
@@ -198,7 +198,7 @@ peripherals:
   - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
     peripheral_group: sst
     mm_port_names:
-      - REG_STAT_HDR_INFO
+      - REG_STAT_HDR_DAT
 
   #############################################################################
   # BF = Beamformer (from node_sdp_beamformer.vhd)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
new file mode 100644
index 0000000000000000000000000000000000000000..ad15dfbfc13b5d828f6cf07ef1914e38f15f1bb4
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
@@ -0,0 +1,1439 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+  <spirit:vendor>ASTRON</spirit:vendor>
+  <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</spirit:library>
+  <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>address</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_address_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_clk_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>mem</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>writedata</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_writedata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>readdata</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_readdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>addressAlignment</spirit:name>
+          <spirit:displayName>Slave addressing</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>addressGroup</spirit:name>
+          <spirit:displayName>Address group</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>addressSpan</spirit:name>
+          <spirit:displayName>Address span</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>addressUnits</spirit:name>
+          <spirit:displayName>Address units</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>alwaysBurstMaxBurst</spirit:name>
+          <spirit:displayName>Always burst maximum burst</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>Associated clock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>Associated reset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bitsPerSymbol</spirit:name>
+          <spirit:displayName>Bits per symbol</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bridgedAddressOffset</spirit:name>
+          <spirit:displayName>Bridged Address Offset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bridgesToMaster</spirit:name>
+          <spirit:displayName>Bridges to master</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+          <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>burstcountUnits</spirit:name>
+          <spirit:displayName>Burstcount units</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>constantBurstBehavior</spirit:name>
+          <spirit:displayName>Constant burst behavior</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>explicitAddressSpan</spirit:name>
+          <spirit:displayName>Explicit address span</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>holdTime</spirit:name>
+          <spirit:displayName>Hold</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>interleaveBursts</spirit:name>
+          <spirit:displayName>Interleave bursts</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isBigEndian</spirit:name>
+          <spirit:displayName>Big endian</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isFlash</spirit:name>
+          <spirit:displayName>Flash memory</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isMemoryDevice</spirit:name>
+          <spirit:displayName>Memory device</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isNonVolatileStorage</spirit:name>
+          <spirit:displayName>Non-volatile storage</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>linewrapBursts</spirit:name>
+          <spirit:displayName>Linewrap bursts</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>maximumPendingReadTransactions</spirit:name>
+          <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>maximumPendingWriteTransactions</spirit:name>
+          <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>minimumReadLatency</spirit:name>
+          <spirit:displayName>minimumReadLatency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>minimumResponseLatency</spirit:name>
+          <spirit:displayName>Minimum response latency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>minimumUninterruptedRunLength</spirit:name>
+          <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>printableDevice</spirit:name>
+          <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>readLatency</spirit:name>
+          <spirit:displayName>Read latency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>readWaitStates</spirit:name>
+          <spirit:displayName>Read wait states</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>readWaitTime</spirit:name>
+          <spirit:displayName>Read wait</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>registerIncomingSignals</spirit:name>
+          <spirit:displayName>Register incoming signals</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>registerOutgoingSignals</spirit:name>
+          <spirit:displayName>Register outgoing signals</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>setupTime</spirit:name>
+          <spirit:displayName>Setup</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>timingUnits</spirit:name>
+          <spirit:displayName>Timing units</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>transparentBridge</spirit:name>
+          <spirit:displayName>Transparent bridge</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>waitrequestAllowance</spirit:name>
+          <spirit:displayName>Waitrequest allowance</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>wellBehavedWaitrequest</spirit:name>
+          <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>writeLatency</spirit:name>
+          <spirit:displayName>Write latency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>writeWaitStates</spirit:name>
+          <spirit:displayName>Write wait states</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>writeWaitTime</spirit:name>
+          <spirit:displayName>Write wait</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <altera:altera_assignments>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </altera:altera_assignments>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>read</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_read_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>readdata</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_readdata_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_reset_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>system</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>csi_system_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>clockRate</spirit:name>
+          <spirit:displayName>Clock rate</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>externallyDriven</spirit:name>
+          <spirit:displayName>Externally driven</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ptfSchematicName</spirit:name>
+          <spirit:displayName>PTF schematic name</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>system_reset</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>csi_system_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>Associated clock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>synchronousEdges</spirit:name>
+          <spirit:displayName>Synchronous edges</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>write</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_write_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>writedata</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_writedata_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>QUARTUS_SYNTH</spirit:name>
+        <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+        <spirit:modelName>avs_common_mm</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>csi_system_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>csi_system_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_address</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_write</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_writedata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_read</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_readdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_reset_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_clk_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_address_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_write_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_writedata_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_read_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_readdata_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:vendorExtensions>
+    <altera:entity_info>
+      <spirit:vendor>ASTRON</spirit:vendor>
+      <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</spirit:library>
+      <spirit:name>avs_common_mm</spirit:name>
+      <spirit:version>1.0</spirit:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>g_adr_w</spirit:name>
+          <spirit:displayName>g_adr_w</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>g_dat_w</spirit:name>
+          <spirit:displayName>g_dat_w</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+          <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>device</spirit:name>
+          <spirit:displayName>Device</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>deviceFamily</spirit:name>
+          <spirit:displayName>Device family</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>deviceSpeedGrade</spirit:name>
+          <spirit:displayName>Device Speed Grade</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>generationId</spirit:name>
+          <spirit:displayName>Generation Id</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bonusData</spirit:name>
+          <spirit:displayName>bonusData</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="bonusData">bonusData 
+{
+}
+</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>hideFromIPCatalog</spirit:name>
+          <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>lockedInterfaceDefinition</spirit:name>
+          <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>systemInfos</spirit:name>
+          <spirit:displayName>systemInfos</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+    <connPtSystemInfos>
+        <entry>
+            <key>mem</key>
+            <value>
+                <connectionPointName>mem</connectionPointName>
+                <suppliedSystemInfos/>
+                <consumedSystemInfos>
+                    <entry>
+                        <key>ADDRESS_MAP</key>
+                        <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                    </entry>
+                    <entry>
+                        <key>ADDRESS_WIDTH</key>
+                        <value>3</value>
+                    </entry>
+                    <entry>
+                        <key>MAX_SLAVE_DATA_WIDTH</key>
+                        <value>32</value>
+                    </entry>
+                </consumedSystemInfos>
+            </value>
+        </entry>
+        <entry>
+            <key>system</key>
+            <value>
+                <connectionPointName>system</connectionPointName>
+                <suppliedSystemInfos>
+                    <entry>
+                        <key>CLOCK_RATE</key>
+                        <value>100000000</value>
+                    </entry>
+                </suppliedSystemInfos>
+                <consumedSystemInfos/>
+            </value>
+        </entry>
+    </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
new file mode 100644
index 0000000000000000000000000000000000000000..9df979c5c333e41df185fc3c7e4c6baaa0c153c1
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+  <spirit:vendor>ASTRON</spirit:vendor>
+  <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</spirit:library>
+  <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>address</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_address_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_clk_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>mem</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>address</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_address</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>write</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_write</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>writedata</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_writedata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>read</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_read</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>readdata</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>avs_mem_readdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>addressAlignment</spirit:name>
+          <spirit:displayName>Slave addressing</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>addressGroup</spirit:name>
+          <spirit:displayName>Address group</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>addressSpan</spirit:name>
+          <spirit:displayName>Address span</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>addressUnits</spirit:name>
+          <spirit:displayName>Address units</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>alwaysBurstMaxBurst</spirit:name>
+          <spirit:displayName>Always burst maximum burst</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>Associated clock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>Associated reset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bitsPerSymbol</spirit:name>
+          <spirit:displayName>Bits per symbol</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bridgedAddressOffset</spirit:name>
+          <spirit:displayName>Bridged Address Offset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bridgesToMaster</spirit:name>
+          <spirit:displayName>Bridges to master</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+          <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>burstcountUnits</spirit:name>
+          <spirit:displayName>Burstcount units</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>constantBurstBehavior</spirit:name>
+          <spirit:displayName>Constant burst behavior</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>explicitAddressSpan</spirit:name>
+          <spirit:displayName>Explicit address span</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>holdTime</spirit:name>
+          <spirit:displayName>Hold</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>interleaveBursts</spirit:name>
+          <spirit:displayName>Interleave bursts</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isBigEndian</spirit:name>
+          <spirit:displayName>Big endian</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isFlash</spirit:name>
+          <spirit:displayName>Flash memory</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isMemoryDevice</spirit:name>
+          <spirit:displayName>Memory device</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>isNonVolatileStorage</spirit:name>
+          <spirit:displayName>Non-volatile storage</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>linewrapBursts</spirit:name>
+          <spirit:displayName>Linewrap bursts</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>maximumPendingReadTransactions</spirit:name>
+          <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>maximumPendingWriteTransactions</spirit:name>
+          <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>minimumReadLatency</spirit:name>
+          <spirit:displayName>minimumReadLatency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>minimumResponseLatency</spirit:name>
+          <spirit:displayName>Minimum response latency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>minimumUninterruptedRunLength</spirit:name>
+          <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>printableDevice</spirit:name>
+          <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>readLatency</spirit:name>
+          <spirit:displayName>Read latency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>readWaitStates</spirit:name>
+          <spirit:displayName>Read wait states</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>readWaitTime</spirit:name>
+          <spirit:displayName>Read wait</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>registerIncomingSignals</spirit:name>
+          <spirit:displayName>Register incoming signals</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>registerOutgoingSignals</spirit:name>
+          <spirit:displayName>Register outgoing signals</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>setupTime</spirit:name>
+          <spirit:displayName>Setup</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>timingUnits</spirit:name>
+          <spirit:displayName>Timing units</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>transparentBridge</spirit:name>
+          <spirit:displayName>Transparent bridge</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>waitrequestAllowance</spirit:name>
+          <spirit:displayName>Waitrequest allowance</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>wellBehavedWaitrequest</spirit:name>
+          <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>writeLatency</spirit:name>
+          <spirit:displayName>Write latency</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>writeWaitStates</spirit:name>
+          <spirit:displayName>Write wait states</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>writeWaitTime</spirit:name>
+          <spirit:displayName>Write wait</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <altera:altera_assignments>
+          <spirit:parameters>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+            </spirit:parameter>
+            <spirit:parameter>
+              <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+            </spirit:parameter>
+          </spirit:parameters>
+        </altera:altera_assignments>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>read</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_read_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>readdata</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_readdata_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_reset_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>system</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>csi_system_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>clockRate</spirit:name>
+          <spirit:displayName>Clock rate</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>externallyDriven</spirit:name>
+          <spirit:displayName>Externally driven</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ptfSchematicName</spirit:name>
+          <spirit:displayName>PTF schematic name</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>system_reset</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>csi_system_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>Associated clock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>synchronousEdges</spirit:name>
+          <spirit:displayName>Synchronous edges</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>write</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_write_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>writedata</spirit:name>
+      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+      <spirit:slave></spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>export</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>coe_writedata_export</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>associatedClock</spirit:name>
+          <spirit:displayName>associatedClock</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>associatedReset</spirit:name>
+          <spirit:displayName>associatedReset</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>prSafe</spirit:name>
+          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>QUARTUS_SYNTH</spirit:name>
+        <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+        <spirit:modelName>avs_common_mm</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>csi_system_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>csi_system_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_address</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>5</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_write</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_writedata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_read</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>avs_mem_readdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_reset_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_clk_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_address_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>5</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_write_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_writedata_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_read_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>coe_readdata_export</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left>0</spirit:left>
+            <spirit:right>31</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:vendorExtensions>
+    <altera:entity_info>
+      <spirit:vendor>ASTRON</spirit:vendor>
+      <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</spirit:library>
+      <spirit:name>avs_common_mm</spirit:name>
+      <spirit:version>1.0</spirit:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>g_adr_w</spirit:name>
+          <spirit:displayName>g_adr_w</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>g_dat_w</spirit:name>
+          <spirit:displayName>g_dat_w</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+          <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>device</spirit:name>
+          <spirit:displayName>Device</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>deviceFamily</spirit:name>
+          <spirit:displayName>Device family</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>deviceSpeedGrade</spirit:name>
+          <spirit:displayName>Device Speed Grade</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>generationId</spirit:name>
+          <spirit:displayName>Generation Id</spirit:displayName>
+          <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>bonusData</spirit:name>
+          <spirit:displayName>bonusData</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="bonusData">bonusData 
+{
+}
+</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>hideFromIPCatalog</spirit:name>
+          <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+          <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>lockedInterfaceDefinition</spirit:name>
+          <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>6</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>6</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>256</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>systemInfos</spirit:name>
+          <spirit:displayName>systemInfos</spirit:displayName>
+          <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+    <connPtSystemInfos>
+        <entry>
+            <key>mem</key>
+            <value>
+                <connectionPointName>mem</connectionPointName>
+                <suppliedSystemInfos/>
+                <consumedSystemInfos>
+                    <entry>
+                        <key>ADDRESS_MAP</key>
+                        <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                    </entry>
+                    <entry>
+                        <key>ADDRESS_WIDTH</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>MAX_SLAVE_DATA_WIDTH</key>
+                        <value>32</value>
+                    </entry>
+                </consumedSystemInfos>
+            </value>
+        </entry>
+        <entry>
+            <key>system</key>
+            <value>
+                <connectionPointName>system</connectionPointName>
+                <suppliedSystemInfos>
+                    <entry>
+                        <key>CLOCK_RATE</key>
+                        <value>100000000</value>
+                    </entry>
+                </suppliedSystemInfos>
+                <consumedSystemInfos/>
+            </value>
+        </entry>
+    </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index b66b1b6e96d92f0f3619d4f10e0d1bc49df3f665..07e80d91aaa70391fc56c9247be7338cedc0d471 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -99,7 +99,7 @@
    {
       datum baseAddress
       {
-         value = "13672";
+         value = "13936";
          type = "String";
       }
    }
@@ -144,7 +144,7 @@
    {
       datum baseAddress
       {
-         value = "12296";
+         value = "13856";
          type = "String";
       }
    }
@@ -165,7 +165,7 @@
    {
       datum baseAddress
       {
-         value = "13664";
+         value = "13928";
          type = "String";
       }
    }
@@ -362,7 +362,7 @@
    {
       datum baseAddress
       {
-         value = "12544";
+         value = "12800";
          type = "String";
       }
    }
@@ -378,7 +378,7 @@
    {
       datum baseAddress
       {
-         value = "13584";
+         value = "13840";
          type = "String";
       }
    }
@@ -410,7 +410,7 @@
    {
       datum baseAddress
       {
-         value = "13616";
+         value = "13880";
          type = "String";
       }
    }
@@ -426,7 +426,7 @@
    {
       datum baseAddress
       {
-         value = "13440";
+         value = "13696";
          type = "String";
       }
    }
@@ -458,7 +458,7 @@
    {
       datum baseAddress
       {
-         value = "13608";
+         value = "13872";
          type = "String";
       }
    }
@@ -490,7 +490,7 @@
    {
       datum baseAddress
       {
-         value = "13568";
+         value = "13824";
          type = "String";
       }
    }
@@ -511,7 +511,7 @@
    {
       datum baseAddress
       {
-         value = "13656";
+         value = "13920";
          type = "String";
       }
    }
@@ -532,7 +532,7 @@
    {
       datum baseAddress
       {
-         value = "13648";
+         value = "13912";
          type = "String";
       }
    }
@@ -553,7 +553,7 @@
    {
       datum baseAddress
       {
-         value = "13504";
+         value = "13760";
          type = "String";
       }
    }
@@ -569,7 +569,7 @@
    {
       datum baseAddress
       {
-         value = "13472";
+         value = "13728";
          type = "String";
       }
    }
@@ -590,7 +590,7 @@
    {
       datum baseAddress
       {
-         value = "13376";
+         value = "13632";
          type = "String";
       }
    }
@@ -627,7 +627,7 @@
    {
       datum baseAddress
       {
-         value = "13640";
+         value = "13904";
          type = "String";
       }
    }
@@ -648,7 +648,7 @@
    {
       datum baseAddress
       {
-         value = "13632";
+         value = "13896";
          type = "String";
       }
    }
@@ -664,7 +664,7 @@
    {
       datum baseAddress
       {
-         value = "13600";
+         value = "13864";
          type = "String";
       }
    }
@@ -701,7 +701,7 @@
    {
       datum baseAddress
       {
-         value = "13536";
+         value = "13792";
          type = "String";
       }
    }
@@ -717,7 +717,7 @@
    {
       datum baseAddress
       {
-         value = "13312";
+         value = "13568";
          type = "String";
       }
    }
@@ -733,7 +733,39 @@
    {
       datum baseAddress
       {
-         value = "13624";
+         value = "13888";
+         type = "String";
+      }
+   }
+   element reg_stat_enable
+   {
+      datum _sortIndex
+      {
+         value = "47";
+         type = "int";
+      }
+   }
+   element reg_stat_enable.mem
+   {
+      datum baseAddress
+      {
+         value = "12296";
+         type = "String";
+      }
+   }
+   element reg_stat_hdr_dat
+   {
+      datum _sortIndex
+      {
+         value = "48";
+         type = "int";
+      }
+   }
+   element reg_stat_hdr_dat.mem
+   {
+      datum baseAddress
+      {
+         value = "256";
          type = "String";
       }
    }
@@ -749,7 +781,7 @@
    {
       datum baseAddress
       {
-         value = "12800";
+         value = "13056";
          type = "String";
       }
    }
@@ -765,7 +797,7 @@
    {
       datum baseAddress
       {
-         value = "13056";
+         value = "13312";
          type = "String";
       }
    }
@@ -807,7 +839,7 @@
    {
       datum baseAddress
       {
-         value = "256";
+         value = "12544";
          type = "String";
       }
    }
@@ -2176,6 +2208,76 @@
    internal="reg_si.writedata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_stat_enable_address"
+   internal="reg_stat_enable.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_enable_clk"
+   internal="reg_stat_enable.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_enable_read"
+   internal="reg_stat_enable.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_enable_readdata"
+   internal="reg_stat_enable.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_enable_reset"
+   internal="reg_stat_enable.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_enable_write"
+   internal="reg_stat_enable.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_enable_writedata"
+   internal="reg_stat_enable.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_hdr_dat_address"
+   internal="reg_stat_hdr_dat.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_hdr_dat_clk"
+   internal="reg_stat_hdr_dat.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_hdr_dat_read"
+   internal="reg_stat_hdr_dat.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_hdr_dat_readdata"
+   internal="reg_stat_hdr_dat.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_hdr_dat_reset"
+   internal="reg_stat_hdr_dat.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_hdr_dat_write"
+   internal="reg_stat_hdr_dat.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_stat_hdr_dat_writedata"
+   internal="reg_stat_hdr_dat.writedata"
+   type="conduit"
+   dir="end" />
  <interface
    name="reg_unb_pmbus_address"
    internal="reg_unb_pmbus.address"
@@ -4203,20 +4305,12 @@
                 <isStart>true</isStart>
                 <ports>
                     <port>
-                        <name>debug_mem_slave_debugaccess_to_roms</name>
-                        <role>debugaccess</role>
+                        <name>d_address</name>
+                        <role>address</role>
                         <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>d_waitrequest</name>
-                        <role>waitrequest</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <width>24</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
                         <name>d_byteenable</name>
@@ -4227,17 +4321,25 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>d_address</name>
-                        <role>address</role>
+                        <name>d_read</name>
+                        <role>read</role>
                         <direction>Output</direction>
-                        <width>24</width>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>d_readdata</name>
+                        <role>readdata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>d_read</name>
-                        <role>read</role>
-                        <direction>Output</direction>
+                        <name>d_waitrequest</name>
+                        <role>waitrequest</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -4259,12 +4361,12 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>d_readdata</name>
-                        <role>readdata</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <name>debug_mem_slave_debugaccess_to_roms</name>
+                        <role>debugaccess</role>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -4428,14 +4530,6 @@
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
-                    <port>
-                        <name>debug_mem_slave_read</name>
-                        <role>read</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
                     <port>
                         <name>debug_mem_slave_byteenable</name>
                         <role>byteenable</role>
@@ -4445,16 +4539,16 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>debug_mem_slave_waitrequest</name>
-                        <role>waitrequest</role>
-                        <direction>Output</direction>
+                        <name>debug_mem_slave_debugaccess</name>
+                        <role>debugaccess</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>debug_mem_slave_write</name>
-                        <role>write</role>
+                        <name>debug_mem_slave_read</name>
+                        <role>read</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
@@ -4469,8 +4563,16 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>debug_mem_slave_debugaccess</name>
-                        <role>debugaccess</role>
+                        <name>debug_mem_slave_waitrequest</name>
+                        <role>waitrequest</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_write</name>
+                        <role>write</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
@@ -4723,14 +4825,6 @@
                 <type>avalon</type>
                 <isStart>true</isStart>
                 <ports>
-                    <port>
-                        <name>i_read</name>
-                        <role>read</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
                     <port>
                         <name>i_address</name>
                         <role>address</role>
@@ -4740,9 +4834,9 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>i_waitrequest</name>
-                        <role>waitrequest</role>
-                        <direction>Input</direction>
+                        <name>i_read</name>
+                        <role>read</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -4755,6 +4849,14 @@
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
+                    <port>
+                        <name>i_waitrequest</name>
+                        <role>waitrequest</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
                 </ports>
                 <assignments>
                     <assignmentValueMap/>
@@ -4946,16 +5048,16 @@
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>reset_req</name>
-                        <role>reset_req</role>
+                        <name>reset_n</name>
+                        <role>reset_n</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>reset_n</name>
-                        <role>reset_n</role>
+                        <name>reset_req</name>
+                        <role>reset_req</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
@@ -5295,7 +5397,7 @@
                     <consumedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x3480' end='0x34A0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_stat_enable.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3200' end='0x3300' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x3300' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x3500' end='0x3540' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x3540' end='0x3580' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x3580' end='0x35A0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x35A0' end='0x35C0' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x35C0' end='0x35E0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x35E0' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x3600' end='0x3610' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x3610' end='0x3620' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3620' end='0x3628' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x3628' end='0x3630' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x3630' end='0x3638' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x3638' end='0x3640' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x3640' end='0x3648' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3648' end='0x3650' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x3650' end='0x3658' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3658' end='0x3660' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3660' end='0x3668' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3668' end='0x3670' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3670' end='0x3678' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
@@ -11600,37 +11702,1269 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="ram_fil_coefs"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>14</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>14</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>65536</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>system_reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>16</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="ram_scrap"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>9</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>9</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>2048</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>system_reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>11</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_fil_coefs"
+   name="ram_ss_ss_wide"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -12216,37 +13550,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_scrap"
+   name="ram_st_bst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -12262,7 +13596,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>9</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -12326,7 +13660,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>9</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -12395,7 +13729,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>2048</value>
+                            <value>16384</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -12801,11 +14135,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>11</value>
+                            <value>14</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12832,37 +14166,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_ss_ss_wide"
+   name="ram_st_sst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -13448,37 +14782,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_st_bst"
+   name="ram_wg"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -13494,7 +14828,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>12</width>
+                        <width>14</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -13558,7 +14892,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>12</width>
+                        <width>14</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -13627,7 +14961,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16384</value>
+                            <value>65536</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -14033,11 +15367,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>14</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14064,37 +15398,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_st_sst"
+   name="reg_aduh_monitor"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -14110,7 +15444,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>14</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -14174,7 +15508,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>14</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -14243,7 +15577,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>65536</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -14649,11 +15983,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>16</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14680,37 +16014,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_wg"
+   name="reg_bf_scale"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -14726,7 +16060,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>14</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -14790,7 +16124,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>14</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -14859,7 +16193,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>65536</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -15265,11 +16599,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>16</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15296,37 +16630,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_aduh_monitor"
+   name="reg_bsn_monitor_input"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -15342,7 +16676,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>6</width>
+                        <width>8</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -15406,7 +16740,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>6</width>
+                        <width>8</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -15475,7 +16809,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>256</value>
+                            <value>1024</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -15881,11 +17215,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>8</value>
+                            <value>10</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15912,37 +17246,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bf_scale"
+   name="reg_bsn_scheduler"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -15958,7 +17292,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -16022,7 +17356,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -16091,7 +17425,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -16497,11 +17831,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16528,37 +17862,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_monitor_input"
+   name="reg_bsn_source_v2"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -16574,7 +17908,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>8</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -16638,7 +17972,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>8</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -16707,7 +18041,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>1024</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -17113,11 +18447,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>10</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17144,37 +18478,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_scheduler"
+   name="reg_diag_data_buffer_bsn"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -17190,7 +18524,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17254,7 +18588,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17323,7 +18657,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>128</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -17729,11 +19063,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>7</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17760,37 +19094,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_source_v2"
+   name="reg_dp_selector"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -17806,7 +19140,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17870,7 +19204,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17939,7 +19273,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -18345,11 +19679,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18376,37 +19710,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_diag_data_buffer_bsn"
+   name="reg_dp_shiftram"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -18992,37 +20326,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_selector"
+   name="reg_dp_xonoff"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -19038,7 +20372,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19102,7 +20436,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19171,7 +20505,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -19577,11 +20911,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19608,37 +20942,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_shiftram"
+   name="reg_dpmm_ctrl"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -19654,7 +20988,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>5</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19718,7 +21052,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>5</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19787,7 +21121,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>128</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -20193,11 +21527,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>7</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20224,37 +21558,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_xonoff"
+   name="reg_dpmm_data"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -20270,7 +21604,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -20334,7 +21668,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -20403,7 +21737,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -20809,11 +22143,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20840,37 +22174,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_ctrl"
+   name="reg_epcs"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -20886,7 +22220,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -20950,7 +22284,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -21019,7 +22353,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -21425,11 +22759,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21456,37 +22790,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_data"
+   name="reg_fpga_temp_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -21502,7 +22836,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -21566,7 +22900,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -21635,7 +22969,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -22041,11 +23375,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22072,37 +23406,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_epcs"
+   name="reg_fpga_voltage_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -22118,7 +23452,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22182,7 +23516,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22251,7 +23585,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>64</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -22657,11 +23991,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>6</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22688,37 +24022,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_temp_sens"
+   name="reg_hdr_dat"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -22734,7 +24068,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>7</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22798,7 +24132,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>7</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22867,7 +24201,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>512</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -23273,11 +24607,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>9</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23304,37 +24638,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_voltage_sens"
+   name="reg_mmdp_ctrl"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -23350,7 +24684,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23414,7 +24748,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23483,7 +24817,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -23889,11 +25223,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23920,37 +25254,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_hdr_dat"
+   name="reg_mmdp_data"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -23966,7 +25300,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>7</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -24030,7 +25364,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>7</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -24099,7 +25433,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>512</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -24505,11 +25839,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>9</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24536,37 +25870,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_ctrl"
+   name="reg_nw_10gbe_eth10g"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -25152,37 +26486,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_data"
+   name="reg_nw_10gbe_mac"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -25198,7 +26532,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>13</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -25262,7 +26596,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>13</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -25331,7 +26665,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32768</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -25737,11 +27071,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>15</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25768,37 +27102,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_nw_10gbe_eth10g"
+   name="reg_remu"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -25814,7 +27148,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -25878,7 +27212,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -25947,7 +27281,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -26353,11 +27687,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26384,37 +27718,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_nw_10gbe_mac"
+   name="reg_sdp_info"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -26430,7 +27764,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>13</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -26494,7 +27828,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>13</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -26563,7 +27897,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32768</value>
+                            <value>64</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -26969,11 +28303,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>15</value>
+                            <value>6</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27000,37 +28334,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_remu"
+   name="reg_si"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -27046,7 +28380,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -27110,7 +28444,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -27179,7 +28513,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -27585,11 +28919,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27616,37 +28950,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_sdp_info"
+   name="reg_stat_enable"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -27662,7 +28996,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -27726,7 +29060,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -27795,7 +29129,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -28201,11 +29535,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28232,37 +29566,37 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_si"
+   name="reg_stat_hdr_dat"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -28278,7 +29612,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -28342,7 +29676,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -28411,7 +29745,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -28817,11 +30151,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28848,30 +30182,30 @@
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
@@ -32686,7 +34020,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="jtag_uart_0.avalon_jtag_slave">
-  <parameter name="baseAddress" value="0x3568" />
+  <parameter name="baseAddress" value="0x3670" />
  </connection>
  <connection
    kind="avalon"
@@ -32700,7 +34034,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_unb_sens.mem">
-  <parameter name="baseAddress" value="0x3300" />
+  <parameter name="baseAddress" value="0x3400" />
  </connection>
  <connection
    kind="avalon"
@@ -32721,7 +34055,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="pio_pps.mem">
-  <parameter name="baseAddress" value="0x3560" />
+  <parameter name="baseAddress" value="0x3668" />
  </connection>
  <connection
    kind="avalon"
@@ -32735,63 +34069,63 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_remu.mem">
-  <parameter name="baseAddress" value="0x34e0" />
+  <parameter name="baseAddress" value="0x35e0" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_epcs.mem">
-  <parameter name="baseAddress" value="0x34c0" />
+  <parameter name="baseAddress" value="0x35c0" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_dpmm_ctrl.mem">
-  <parameter name="baseAddress" value="0x3558" />
+  <parameter name="baseAddress" value="0x3660" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_dpmm_data.mem">
-  <parameter name="baseAddress" value="0x3550" />
+  <parameter name="baseAddress" value="0x3658" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_mmdp_ctrl.mem">
-  <parameter name="baseAddress" value="0x3548" />
+  <parameter name="baseAddress" value="0x3650" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_mmdp_data.mem">
-  <parameter name="baseAddress" value="0x3540" />
+  <parameter name="baseAddress" value="0x3648" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_fpga_temp_sens.mem">
-  <parameter name="baseAddress" value="0x34a0" />
+  <parameter name="baseAddress" value="0x35a0" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_unb_pmbus.mem">
-  <parameter name="baseAddress" value="0x3200" />
+  <parameter name="baseAddress" value="0x3300" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_fpga_voltage_sens.mem">
-  <parameter name="baseAddress" value="0x3440" />
+  <parameter name="baseAddress" value="0x3540" />
  </connection>
  <connection
    kind="avalon"
@@ -32805,7 +34139,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_si.mem">
-  <parameter name="baseAddress" value="0x3538" />
+  <parameter name="baseAddress" value="0x3640" />
  </connection>
  <connection
    kind="avalon"
@@ -32826,7 +34160,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_aduh_monitor.mem">
-  <parameter name="baseAddress" value="0x3100" />
+  <parameter name="baseAddress" value="0x3200" />
  </connection>
  <connection
    kind="avalon"
@@ -32847,21 +34181,21 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_bsn_scheduler.mem">
-  <parameter name="baseAddress" value="0x3530" />
+  <parameter name="baseAddress" value="0x3638" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_bsn_source_v2.mem">
-  <parameter name="baseAddress" value="0x3480" />
+  <parameter name="baseAddress" value="0x3580" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_wg.mem">
-  <parameter name="baseAddress" value="0x0100" />
+  <parameter name="baseAddress" value="0x3100" />
  </connection>
  <connection
    kind="avalon"
@@ -32882,7 +34216,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_dp_selector.mem">
-  <parameter name="baseAddress" value="0x3528" />
+  <parameter name="baseAddress" value="0x3630" />
  </connection>
  <connection
    kind="avalon"
@@ -32910,7 +34244,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_bf_scale.mem">
-  <parameter name="baseAddress" value="0x3510" />
+  <parameter name="baseAddress" value="0x3610" />
  </connection>
  <connection
    kind="avalon"
@@ -32924,7 +34258,7 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_dp_xonoff.mem">
-  <parameter name="baseAddress" value="0x3500" />
+  <parameter name="baseAddress" value="0x3600" />
  </connection>
  <connection
    kind="avalon"
@@ -32938,14 +34272,14 @@
    version="18.0"
    start="cpu_0.data_master"
    end="reg_sdp_info.mem">
-  <parameter name="baseAddress" value="0x3400" />
+  <parameter name="baseAddress" value="0x3500" />
  </connection>
  <connection
    kind="avalon"
    version="18.0"
    start="cpu_0.data_master"
    end="reg_nw_10gbe_eth10g.mem">
-  <parameter name="baseAddress" value="0x3520" />
+  <parameter name="baseAddress" value="0x3628" />
  </connection>
  <connection
    kind="avalon"
@@ -32973,8 +34307,22 @@
    version="18.0"
    start="cpu_0.data_master"
    end="pio_jesd_ctrl.mem">
+  <parameter name="baseAddress" value="0x3620" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu_0.data_master"
+   end="reg_stat_enable.mem">
   <parameter name="baseAddress" value="0x3008" />
  </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu_0.data_master"
+   end="reg_stat_hdr_dat.mem">
+  <parameter name="baseAddress" value="0x0100" />
+ </connection>
  <connection
    kind="avalon"
    version="18.0"
@@ -33197,6 +34545,16 @@
    version="18.0"
    start="clk_0.clk"
    end="pio_jesd_ctrl.system" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="clk_0.clk"
+   end="reg_stat_enable.system" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="clk_0.clk"
+   end="reg_stat_hdr_dat.system" />
  <connection
    kind="interrupt"
    version="18.0"
@@ -33438,6 +34796,16 @@
    version="18.0"
    start="clk_0.clk_reset"
    end="pio_jesd_ctrl.system_reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="clk_0.clk_reset"
+   end="reg_stat_enable.system_reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="clk_0.clk_reset"
+   end="reg_stat_hdr_dat.system_reset" />
  <connection
    kind="reset"
    version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 70df4b5df7277eb49c1f646442805263adc76b0b..8649140b3dbb843965d243a317c5ed9cbc11c9c5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -89,5 +89,7 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 9d999569781b9844f2a354f238a0930e40ea98b1..9cd3020ab65b38f54454836d232aebf5f3580a20 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -95,5 +95,7 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index bbdd8b6c5416dc4d088a12432b3ef9486c385931..f6fd854b56e7198a2197d8b247e73d66084324e8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -94,5 +94,7 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index 1a467b6b499c9fa611d9feab9baf1cfdf113c68d..71bdc1825f2cf5903367fa66df58739c4da2b886 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -112,6 +112,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
   CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
   CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
   CONSTANT c_mm_file_ram_st_sst           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+  CONSTANT c_mm_file_reg_stat_enable      : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+  CONSTANT c_mm_file_reg_stat_hdr_info    : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
 
   -- Tb
   SIGNAL tb_end              : STD_LOGIC := '0';
@@ -287,6 +289,11 @@ BEGIN
                             "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3,   -- this is the wait until condition
                             c_sdp_T_sub, tb_clk);
 
+    ----------------------------------------------------------------------------
+    -- Offload enable
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+
     ---------------------------------------------------------------------------
     -- Read subband statistics
     ---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 0e2c058d57ea520fe9bf7991b49e1bb95df5e83a..57018b560bec906485bd5e61760b449c99308278 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -26,7 +26,7 @@
 --   Unb2b version for lab testing
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -41,6 +41,8 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE wpfb_lib.wpfb_pkg.ALL;
 USE lofar2_sdp_lib.sdp_pkg.ALL;
 USE work.lofar2_unb2b_sdp_station_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
 
 ENTITY lofar2_unb2b_sdp_station IS
   GENERIC (
@@ -55,7 +57,7 @@ ENTITY lofar2_unb2b_sdp_station IS
     g_revision_id            : STRING  := "";  -- revision ID     -- set by QSF
     g_factory_image          : BOOLEAN := FALSE;
     g_protect_addr_range     : BOOLEAN := FALSE;
-    g_wpfb                   : t_wpfb := c_sdp_wpfb_subbands;
+    g_wpfb                   : t_wpfb  := c_sdp_wpfb_subbands;
     g_bsn_nof_clk_per_sync   : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M, overide for short simulation 
     g_scope_selected_subband : NATURAL := 0
   );
@@ -132,11 +134,14 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
   CONSTANT c_addr_w_reg_hdr_dat    : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w)); 
   CONSTANT c_addr_w_reg_dp_xonoff  : NATURAL := 1; 
   CONSTANT c_addr_w_ram_st_bst     : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+  
+  -- 
+  CONSTANT c_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
 
   -- Read only sdp_info values
   CONSTANT c_f_adc     : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
   CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
- 
+  
   SIGNAL gn_id    : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
   SIGNAL gn_index : NATURAL := 0;
 
@@ -328,6 +333,21 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
   SIGNAL ram_st_bst_mosi_arr        : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
   SIGNAL ram_st_bst_miso_arr        : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
 
+  ----------------------------------------------
+  -- SST 
+  ----------------------------------------------
+  -- Statistics Enable
+  SIGNAL reg_stat_enable_mosi       : t_mem_mosi;
+  SIGNAL reg_stat_enable_miso       : t_mem_miso;
+  
+  -- Statistics header info  
+  SIGNAL reg_stat_hdr_dat_mosi      : t_mem_mosi;
+  SIGNAL reg_stat_hdr_dat_miso      : t_mem_miso;
+
+  -- Statistics
+  SIGNAL udp_tx_sosi_arr            : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL udp_tx_siso_arr            : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);  
+
   ----------------------------------------------
   -- 10 GbE 
   ----------------------------------------------
@@ -394,21 +414,23 @@ BEGIN
   -----------------------------------------------------------------------------
   u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
   GENERIC MAP (
-    g_sim                => g_sim,
-    g_technology         => g_technology,
-    g_design_name        => g_design_name,
-    g_design_note        => g_design_note,
-    g_stamp_date         => g_stamp_date,
-    g_stamp_time         => g_stamp_time, 
-    g_revision_id        => g_revision_id, 
-    g_fw_version         => c_fw_version,
-    g_mm_clk_freq        => c_mm_clk_freq,
-    g_eth_clk_freq       => c_unb2b_board_eth_clk_freq_125M,
-    g_aux                => c_unb2b_board_aux,
-    g_factory_image      => g_factory_image,
-    g_protect_addr_range => g_protect_addr_range,
-    g_dp_clk_freq        => c_unb2b_board_ext_clk_freq_200M,
-    g_dp_clk_use_pll     => FALSE
+    g_sim                     => g_sim,
+    g_technology              => g_technology,
+    g_design_name             => g_design_name,
+    g_design_note             => g_design_note,
+    g_stamp_date              => g_stamp_date,
+    g_stamp_time              => g_stamp_time, 
+    g_revision_id             => g_revision_id, 
+    g_fw_version              => c_fw_version,
+    g_mm_clk_freq             => c_mm_clk_freq,
+    g_eth_clk_freq            => c_unb2b_board_eth_clk_freq_125M,
+    g_aux                     => c_unb2b_board_aux,
+    g_factory_image           => g_factory_image,
+    g_protect_addr_range      => g_protect_addr_range,
+    g_dp_clk_freq             => c_unb2b_board_ext_clk_freq_200M,
+    g_dp_clk_use_pll          => FALSE,
+    g_udp_offload             => TRUE,
+    g_udp_offload_nof_streams => c_eth_nof_udp_ports
   )
   PORT MAP (
     -- Clock an reset signals
@@ -490,6 +512,10 @@ BEGIN
     eth1g_ram_mosi           => eth1g_ram_mosi,
     eth1g_ram_miso           => eth1g_ram_miso,
  
+    -- eth1g UDP streaming
+    udp_tx_sosi_arr          => udp_tx_sosi_arr,
+    udp_tx_siso_arr          => udp_tx_siso_arr,
+
     ram_scrap_mosi           => ram_scrap_mosi,
     ram_scrap_miso           => ram_scrap_miso,
    
@@ -535,42 +561,42 @@ BEGIN
     pout_wdi                 => pout_wdi,
 
     -- mm interfaces for control
-    reg_wdi_mosi             => reg_wdi_mosi,
-    reg_wdi_miso             => reg_wdi_miso,
-    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
-    reg_unb_system_info_miso => reg_unb_system_info_miso,
-    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
-    rom_unb_system_info_miso => rom_unb_system_info_miso, 
-    reg_unb_sens_mosi        => reg_unb_sens_mosi,
-    reg_unb_sens_miso        => reg_unb_sens_miso, 
-    reg_unb_pmbus_mosi       => reg_unb_pmbus_mosi,
-    reg_unb_pmbus_miso       => reg_unb_pmbus_miso,
-    reg_fpga_temp_sens_mosi  => reg_fpga_temp_sens_mosi,
-    reg_fpga_temp_sens_miso  => reg_fpga_temp_sens_miso,
+    reg_wdi_mosi                => reg_wdi_mosi,
+    reg_wdi_miso                => reg_wdi_miso,
+    reg_unb_system_info_mosi    => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso    => reg_unb_system_info_miso,
+    rom_unb_system_info_mosi    => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso    => rom_unb_system_info_miso, 
+    reg_unb_sens_mosi           => reg_unb_sens_mosi,
+    reg_unb_sens_miso           => reg_unb_sens_miso, 
+    reg_unb_pmbus_mosi          => reg_unb_pmbus_mosi,
+    reg_unb_pmbus_miso          => reg_unb_pmbus_miso,
+    reg_fpga_temp_sens_mosi     => reg_fpga_temp_sens_mosi,
+    reg_fpga_temp_sens_miso     => reg_fpga_temp_sens_miso,
     reg_fpga_voltage_sens_mosi  => reg_fpga_voltage_sens_mosi,
     reg_fpga_voltage_sens_miso  => reg_fpga_voltage_sens_miso,
-    reg_ppsh_mosi            => reg_ppsh_mosi,
-    reg_ppsh_miso            => reg_ppsh_miso, 
-    eth1g_mm_rst             => eth1g_mm_rst,
-    eth1g_tse_mosi           => eth1g_tse_mosi,
-    eth1g_tse_miso           => eth1g_tse_miso,
-    eth1g_reg_mosi           => eth1g_reg_mosi,
-    eth1g_reg_miso           => eth1g_reg_miso,
-    eth1g_reg_interrupt      => eth1g_reg_interrupt,
-    eth1g_ram_mosi           => eth1g_ram_mosi,
-    eth1g_ram_miso           => eth1g_ram_miso,
-    reg_dpmm_data_mosi       => reg_dpmm_data_mosi,
-    reg_dpmm_data_miso       => reg_dpmm_data_miso,
-    reg_dpmm_ctrl_mosi       => reg_dpmm_ctrl_mosi,
-    reg_dpmm_ctrl_miso       => reg_dpmm_ctrl_miso,
-    reg_mmdp_data_mosi       => reg_mmdp_data_mosi,
-    reg_mmdp_data_miso       => reg_mmdp_data_miso,
-    reg_mmdp_ctrl_mosi       => reg_mmdp_ctrl_mosi,
-    reg_mmdp_ctrl_miso       => reg_mmdp_ctrl_miso,
-    reg_epcs_mosi            => reg_epcs_mosi,
-    reg_epcs_miso            => reg_epcs_miso,
-    reg_remu_mosi            => reg_remu_mosi,
-    reg_remu_miso            => reg_remu_miso,
+    reg_ppsh_mosi               => reg_ppsh_mosi,
+    reg_ppsh_miso               => reg_ppsh_miso, 
+    eth1g_mm_rst                => eth1g_mm_rst,
+    eth1g_tse_mosi              => eth1g_tse_mosi,
+    eth1g_tse_miso              => eth1g_tse_miso,
+    eth1g_reg_mosi              => eth1g_reg_mosi,
+    eth1g_reg_miso              => eth1g_reg_miso,
+    eth1g_reg_interrupt         => eth1g_reg_interrupt,
+    eth1g_ram_mosi              => eth1g_ram_mosi,
+    eth1g_ram_miso              => eth1g_ram_miso,
+    reg_dpmm_data_mosi          => reg_dpmm_data_mosi,
+    reg_dpmm_data_miso          => reg_dpmm_data_miso,
+    reg_dpmm_ctrl_mosi          => reg_dpmm_ctrl_mosi,
+    reg_dpmm_ctrl_miso          => reg_dpmm_ctrl_miso,
+    reg_mmdp_data_mosi          => reg_mmdp_data_mosi,
+    reg_mmdp_data_miso          => reg_mmdp_data_miso,
+    reg_mmdp_ctrl_mosi          => reg_mmdp_ctrl_mosi,
+    reg_mmdp_ctrl_miso          => reg_mmdp_ctrl_miso,
+    reg_epcs_mosi               => reg_epcs_mosi,
+    reg_epcs_miso               => reg_epcs_miso,
+    reg_remu_mosi               => reg_remu_mosi,
+    reg_remu_miso               => reg_remu_miso,
 
     -- mm buses for signal flow blocks
     -- Jesd ip status/control
@@ -625,7 +651,11 @@ BEGIN
     reg_nw_10GbE_eth10g_mosi    => reg_nw_10GbE_eth10g_mosi,   
     reg_nw_10GbE_eth10g_miso    => reg_nw_10GbE_eth10g_miso,   
     ram_scrap_mosi              => ram_scrap_mosi,
-    ram_scrap_miso              => ram_scrap_miso   
+    ram_scrap_miso              => ram_scrap_miso,
+    reg_stat_enable_mosi        => reg_stat_enable_mosi,
+    reg_stat_enable_miso        => reg_stat_enable_miso,
+    reg_stat_hdr_dat_mosi       => reg_stat_hdr_dat_mosi,
+    reg_stat_hdr_dat_miso       => reg_stat_hdr_dat_miso   
   );
 
   -----------------------------------------------------------------------------
@@ -637,6 +667,7 @@ BEGIN
   cep_eth_src_mac  <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
   cep_ip_src_addr  <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
   cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+  
   stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
   stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
   sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
@@ -732,6 +763,9 @@ BEGIN
       in_sosi_arr        => ait_sosi_arr,    
       pfb_sosi_arr       => pfb_sosi_arr,
       fsub_sosi_arr      => fsub_sosi_arr,
+
+      sst_udp_sosi       => udp_tx_sosi_arr(0),
+      sst_udp_siso       => udp_tx_siso_arr(0),
                                               
       mm_rst             => mm_rst, 
       mm_clk             => mm_clk, 
@@ -746,6 +780,11 @@ BEGIN
       ram_gains_miso     => ram_equalizer_gains_miso,     
       reg_selector_mosi  => reg_dp_selector_mosi,  
       reg_selector_miso  => reg_dp_selector_miso,
+
+      reg_enable_mosi    => reg_stat_enable_mosi,
+      reg_enable_miso    => reg_stat_enable_miso,
+      reg_hdr_dat_mosi   => reg_stat_hdr_dat_mosi,
+      reg_hdr_dat_miso   => reg_stat_hdr_dat_miso,
   
       sdp_info           => sdp_info,
       gn_id              => gn_id,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 41c51dd2529fdc9432f5d82e6a22de87d5acf6a7..077878a6f2043bfc5e1f4b95e62d81c22324b73a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -182,6 +182,14 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
    ram_st_bst_mosi                : OUT t_mem_mosi;
    ram_st_bst_miso                : IN  t_mem_miso;
 
+   -- Subband Statistics (SST)
+   reg_stat_enable_mosi           : OUT t_mem_mosi;
+   reg_stat_enable_miso           : IN  t_mem_miso;
+
+   -- Statistics header info
+   reg_stat_hdr_dat_mosi          : OUT t_mem_mosi;
+   reg_stat_hdr_dat_miso          : IN  t_mem_miso;
+
    -- 10 GbE mac
    reg_nw_10GbE_mac_mosi          : OUT t_mem_mosi;
    reg_nw_10GbE_mac_miso          : IN  t_mem_miso;
@@ -306,6 +314,12 @@ BEGIN
 
     u_mm_file_ram_st_bst             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
                                               PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+    
+    u_mm_file_reg_stat_enable        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
+                                               PORT MAP(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
+
+    u_mm_file_reg_stat_hdr_info      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
+                                               PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
 
     u_mm_file_reg_nw_10GbE_mac       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
                                               PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
@@ -659,6 +673,22 @@ BEGIN
       ram_st_bst_read_export                    => ram_st_bst_mosi.rd,
       ram_st_bst_readdata_export                => ram_st_bst_miso.rddata(c_word_w-1 DOWNTO 0),
 
+      reg_stat_enable_clk_export                => OPEN,
+      reg_stat_enable_reset_export              => OPEN,
+      reg_stat_enable_address_export            => reg_stat_enable_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+      reg_stat_enable_write_export              => reg_stat_enable_mosi.wr,
+      reg_stat_enable_writedata_export          => reg_stat_enable_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_stat_enable_read_export               => reg_stat_enable_mosi.rd,
+      reg_stat_enable_readdata_export           => reg_stat_enable_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_stat_hdr_dat_clk_export                => OPEN,
+      reg_stat_hdr_dat_reset_export              => OPEN,
+      reg_stat_hdr_dat_address_export            => reg_stat_hdr_dat_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+      reg_stat_hdr_dat_write_export              => reg_stat_hdr_dat_mosi.wr,
+      reg_stat_hdr_dat_writedata_export          => reg_stat_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_stat_hdr_dat_read_export               => reg_stat_hdr_dat_mosi.rd,
+      reg_stat_hdr_dat_readdata_export           => reg_stat_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+
       reg_nw_10GbE_mac_clk_export               => OPEN,
       reg_nw_10GbE_mac_reset_export             => OPEN,
       reg_nw_10GbE_mac_address_export           => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 1f8d495b0b7dea61db86c6642e138995248ca9c7..c6d2fa51f9c0dcf50fa2f17a8ce31d35ebc9680a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -287,6 +287,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
             reg_sdp_info_reset_export                 : out std_logic;                                        -- export
             reg_sdp_info_write_export                 : out std_logic;                                        -- export
             reg_sdp_info_writedata_export             : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_enable_address_export            : out std_logic_vector(0 downto 0);                     -- export
+            reg_stat_enable_clk_export                : out std_logic;                                        -- export
+            reg_stat_enable_read_export               : out std_logic;                                        -- export
+            reg_stat_enable_readdata_export           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_enable_reset_export              : out std_logic;                                        -- export
+            reg_stat_enable_write_export              : out std_logic;                                        -- export
+            reg_stat_enable_writedata_export          : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_hdr_dat_address_export           : out std_logic_vector(5 downto 0);                     -- export
+            reg_stat_hdr_dat_clk_export               : out std_logic;                                        -- export
+            reg_stat_hdr_dat_read_export              : out std_logic;                                        -- export
+            reg_stat_hdr_dat_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_hdr_dat_reset_export             : out std_logic;                                        -- export
+            reg_stat_hdr_dat_write_export             : out std_logic;                                        -- export
+            reg_stat_hdr_dat_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
             reg_si_address_export                     : out std_logic_vector(0 downto 0);                     -- export
             reg_si_clk_export                         : out std_logic;                                        -- export
             reg_si_read_export                        : out std_logic;                                        -- export
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b39be046643051f7c1745c1ae6afb85c680caec1
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -0,0 +1,259 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Test statistics offload with "ethernet packet statistics" in wave window only
+-- Usage:
+--   > as 7    # default
+--   > as 12   # for detailed debugging
+--   > run -a  
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station IS
+END tb_lofar2_unb2b_sdp_station;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
+
+  CONSTANT c_sim                          : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr                       : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr                      : NATURAL := 0;
+  CONSTANT c_id                           : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version                      : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+
+  CONSTANT c_eth_clk_period               : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period               : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period           : TIME := 5 ns;
+  CONSTANT c_pps_period                   : NATURAL := 1000;
+
+  CONSTANT c_tb_clk_period                : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+  CONSTANT c_nof_block_per_pps           : NATURAL := 16;
+  CONSTANT c_wpfb_sim                     : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_pps);
+   
+  -- WG
+  CONSTANT c_full_scale_ampl              : REAL := REAL(2**(18-1) - 1);  -- = full scale of WG
+  CONSTANT c_bsn_start_wg                 : NATURAL := 2;  -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+  CONSTANT c_ampl_sp_0                    : NATURAL := 2**(c_sdp_W_adc-1) / 2;  -- in number of lsb
+  CONSTANT c_wg_subband_freq_unit         : REAL := c_diag_wg_freq_unit / REAL(c_sdp_N_fft);  -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+  CONSTANT c_wg_freq_offset               : REAL := 0.0 / 11.0; -- in freq_unit
+  CONSTANT c_subband_sp_0                 : REAL := 102.0;  -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+  CONSTANT c_wg_ampl_lsb                  : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
+
+-- . 1GbE output
+  CONSTANT c_eth_check_nof_packets        : NATURAL := 4512;  -- received packets in 2 sync periods
+  CONSTANT c_eth_runtime_timeout          : TIME := 100 ms;  -- factor 2 margin
+  
+  -- MM  
+  CONSTANT c_mm_file_reg_bsn_source_v2    : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+  CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+  CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+
+  -- Tb
+  SIGNAL tb_end               : STD_LOGIC := '0';
+  SIGNAL sim_done             : STD_LOGIC := '0';
+  SIGNAL eth_done             : STD_LOGIC := '0';
+  SIGNAL verify_done          : STD_LOGIC := '0';
+  SIGNAL tb_clk               : STD_LOGIC := '0';
+
+  -- WG
+  SIGNAL current_bsn_wg       : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+  -- DUT
+  SIGNAL ext_clk              : STD_LOGIC := '0';
+  SIGNAL pps                  : STD_LOGIC := '0';
+  SIGNAL ext_pps              : STD_LOGIC := '0';
+  SIGNAL pps_rst              : STD_LOGIC := '0';
+
+  SIGNAL WDI                  : STD_LOGIC;
+  SIGNAL INTA                 : STD_LOGIC;
+  SIGNAL INTB                 : STD_LOGIC;
+
+  SIGNAL eth_clk              : STD_LOGIC := '0';
+  SIGNAL eth_txp              : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp              : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl             : STD_LOGIC;
+  SIGNAL sens_sda             : STD_LOGIC;
+  SIGNAL pmbus_scl            : STD_LOGIC;
+  SIGNAL pmbus_sda            : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL JESD204B_REFCLK      : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref      : STD_LOGIC;
+  SIGNAL jesd204b_sync_n      : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+  -- System setup
+  ext_clk <= (NOT ext_clk) OR tb_end AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= (NOT eth_clk) OR tb_end AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl  <= 'H';  -- pull up
+  sens_sda  <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  -- External PPS
+  proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+  ext_pps <= pps;
+
+  -- >> DUT <<
+  u_lofar_unb2b_sdp_station : ENTITY work.lofar2_unb2b_sdp_station
+  GENERIC MAP (
+    g_design_name            => "lofar2_unb2b_sdp_station_bf",
+    g_design_note            => "",
+    g_sim                    => c_sim,
+    g_sim_unb_nr             => c_unb_nr,
+    g_sim_node_nr            => c_node_nr,
+    g_wpfb                   => c_wpfb_sim,
+    g_scope_selected_subband => NATURAL(c_subband_sp_0)
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK                  => ext_clk,
+    PPS                  => pps,
+    WDI                  => WDI,
+    INTA                 => INTA,
+    INTB                 => INTB,
+
+    -- Others
+    VERSION              => c_version,
+    ID                   => c_id,
+    TESTIO               => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC              => sens_scl,
+    SENS_SD              => sens_sda,
+
+    PMBUS_SC             => pmbus_scl,
+    PMBUS_SD             => pmbus_sda,
+    PMBUS_ALERT          => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK              => eth_clk,
+    ETH_SGIN             => eth_rxp,
+    ETH_SGOUT            => eth_txp,
+
+    -- LEDs
+    QSFP_LED             => open,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK      => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF      => jesd204b_sysref,
+    JESD204B_SYNC_N      => jesd204b_sync_n
+  );
+
+  ---------------------------------------------------------------------------------------------------------------------
+  -- Stimuli
+  --   MM slave accesses via file IO
+  tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2;    -- Testbench MM clock
+  
+  p_mm_stimuli : PROCESS
+    CONSTANT c_mm_file_reg_stat_enable   : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+    CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
+    VARIABLE v_bsn                       : NATURAL;
+  BEGIN
+    -- Wait for DUT power up after reset
+    WAIT FOR 1 us;
+    
+    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+    -- Enable BS
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                   0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                   1, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_block_per_pps, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,        16#00000003#, tb_clk);  -- Enable BS at PPS
+    
+    -- Enable WG
+    --   0 : mode[7:0]           --> off=0, calc=1, repeat=2, single=3)
+    --       nof_samples[31:16]  --> <= c_ram_wg_size=1024
+    --   1 : phase[15:0]
+    --   2 : freq[30:0]
+    --   3 : ampl[16:0]
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0,                                                      1024 * 2**16 + 1, tb_clk);  -- nof_samples, mode calc
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1,                                 INTEGER(  0.0 * c_diag_wg_phase_unit), tb_clk);  -- phase offset in degrees
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);  -- freq
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3,                            INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk);  -- ampl
+
+    -- Read current BSN
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+    proc_common_wait_some_cycles(tb_clk, 1);
+    
+    -- Write scheduler BSN to trigger start of WG at next block
+    v_bsn := TO_UINT(current_bsn_wg) + 2;
+    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+    v_bsn := c_bsn_start_wg;
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);  -- first write low then high part
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,     0, tb_clk);  -- assume v_bsn < 2**31-1
+    
+    -- Wait for ADUH monitor to have filled with WG data
+    WAIT FOR c_sdp_T_sub * c_sdp_N_taps;
+    WAIT FOR c_sdp_T_sub * 2;
+
+    -- Offload enable
+    mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+    
+    -- End Simulation
+    proc_common_wait_until_high(ext_clk, eth_done);
+    proc_common_wait_some_cycles(ext_clk, 100);
+    proc_common_stop_simulation(TRUE, ext_clk, eth_done, tb_end);
+    WAIT;
+  END PROCESS;
+
+  -- >> Verify proper DUT output using Ethernet packet statistics <<
+  u_eth_statistics : ENTITY eth_lib.eth_statistics
+    GENERIC MAP (
+      g_runtime_nof_packets => c_eth_check_nof_packets,
+      g_runtime_timeout     => c_eth_runtime_timeout,
+      g_check_nof_valid     => TRUE,
+      g_check_nof_valid_ref => c_eth_check_nof_packets
+    )
+  PORT MAP (  
+    eth_serial_in => eth_txp(0),
+    tb_end        => eth_done
+  );
+
+END tb;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index a33fdb59910caf81e2b261cb293cb73906a3e8e6..0fd293bdaecec068cf4ad23c34e40b8ecb346354 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -51,7 +51,7 @@ ENTITY node_sdp_filterbank IS
     g_sim                    : BOOLEAN := FALSE;
     g_wpfb                   : t_wpfb := c_sdp_wpfb_subbands;
     g_scope_selected_subband : NATURAL := 0;
-    g_offload_time           : NATURAL := 0    
+    g_offload_time           : NATURAL := c_sdp_offload_time
   );
   PORT (
     dp_clk        : IN  STD_LOGIC;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index c8eefd48bd2723d3051e9ba45e48ce576924b872..1485e648eb28cfc11cd3a93743023ebd75e006f7 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -110,6 +110,9 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_marker_bst : NATURAL := 66;  -- = 0x42 = 'B'
   CONSTANT c_sdp_marker_xst : NATURAL := 88;  -- = 0x58 = 'X'
 
+  CONSTANT c_sdp_offload_time : NATURAL := 13000;  -- from wave window 62855nS / 5nS = 12571 cycles.
+ 
+
   -- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1, 
   -- therefore these parameters are not explicitly used in calculation of derived constants
   -- LTS 2020_11_23:
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 82c7be74fc12eae88d8e61b88c1843ead9bf6b09..7808805c0d52a92590aca9d9d7f24d1dc04bce1d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -44,7 +44,7 @@ USE work.sdp_pkg.ALL;
 ENTITY sdp_statistics_offload IS
   GENERIC (
     g_statistics_type : STRING  := "SST";
-    g_offload_time    : NATURAL := 13000;  -- from wave window 62855nS / 5nS = 12571 cycles.
+    g_offload_time    : NATURAL := c_sdp_offload_time;
     g_beamset_id      : NATURAL := 0
   );
   PORT (