From a17c84043fb9d42595546eebe8c2da908cd3437d Mon Sep 17 00:00:00 2001 From: Daniel van der Schuur <schuur@astron.nl> Date: Wed, 11 Mar 2015 13:17:04 +0000 Subject: [PATCH] -Set c_inter_channel_delay; -Added comment block on the above. --- .../src/vhdl/apertif_unb1_correlator.vhd | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd index ba75d73d53..8778b15f9e 100644 --- a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd +++ b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd @@ -130,11 +130,17 @@ ARCHITECTURE str OF apertif_unb1_correlator IS CONSTANT c_complex_data_w : NATURAL := 8; CONSTANT c_conjugate : BOOLEAN := TRUE; CONSTANT c_nof_channels : NATURAL := 64; - CONSTANT c_integration_period : NATURAL := sel_a_b(g_sim, 0, 12208); + CONSTANT c_integration_period : NATURAL := sel_a_b(g_sim, 0, 12207); CONSTANT c_nof_visibilities : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2; - -- . With no inter channel output delay, channels are output back-to-back, creating a short full valid burst 64 channels (12.8 Gbps). - -- We need to set an appropriate number of inter-channel delay cycles to even out the correlator output duty cycle. - CONSTANT c_inter_channel_delay : NATURAL := 0; + -- . Inter Channel Delay: + -- . With no inter channel output delay, channels are output back-to-back, creating a short full valid burst of 64 channels (12.8 Gbps burst, 158Mbps on average). + -- We need to set an appropriate number of inter-channel delay cycles for a constant visibility buffer output rate. + -- . The total accumulator output rate = (150 streams*200MHz / 12207) = 8192.021 channels/sec (157Mbps) + -- . 8192 channels/sec = 128 * 64 channels * 300 visibilities + -- . No inter channel delay: 128 * (19200 valid cycles + 1543300 invalid cycles =) 1562500 cycles/sec = 200M cycles/sec + -- . With inter channel delay: 128 * 64 channels * (300 valid cycles + 24114 invalid cycles =) 24414 cycles/sec = 199.999.488 cycles/sec (less than 200M so we're fast enough) + CONSTANT c_inter_channel_delay : NATURAL := sel_a_b(g_sim, 4400, 24114); -- ^^^^^--- 24414= 2*integration period. + -- 4400=~5.5x faster than 157Mbps = 860Mbps burst for sim (but still 157Mbps on average) -- WPFB CONSTANT c_wpfb_wb_factor : NATURAL := 1; -- = default 1, wideband factor -- GitLab