diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 191577e824056e530783ed46a88fcb65a9133d2b..675928d71b20adb802983c10a889f8e7f26ce3eb 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -54,18 +54,18 @@ ENTITY node_sdp_correlator IS
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
- reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_sync_insert_v2_miso : OUT t_mem_miso;
- reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso;
- reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso;
- reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_enable_miso : OUT t_mem_miso;
- reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_hdr_dat_miso : OUT t_mem_miso;
+ reg_dp_bsn_sync_scheduler_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_bsn_sync_scheduler_miso : OUT t_mem_miso;
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso;
+ reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso;
+ reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_miso : OUT t_mem_miso;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -77,9 +77,6 @@ END node_sdp_correlator;
ARCHITECTURE str OF node_sdp_correlator IS
- CONSTANT c_nof_blk_per_sync_max : NATURAL := c_sdp_xst_nof_blk_per_sync_max;
- CONSTANT c_nof_blk_per_sync_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min;
-
CONSTANT c_nof_masters : POSITIVE := 2;
-- crosslet statistics offload
@@ -91,14 +88,18 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
- SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_bsn_sync_scheduler_snk_in : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL dp_bsn_sync_scheduler_src_out : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
- SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
+ SIGNAL dp_bsn_sync_scheduler_out_start : STD_LOGIC;
+ SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
-- Requantize 18b to 16b
@@ -126,27 +127,41 @@ BEGIN
END GENERATE;
---------------------------------------------------------------
- -- dp_sync_insert_v2
+ -- mmp_dp_bsn_sync_scheduler
---------------------------------------------------------------
- u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
+ dp_bsn_sync_scheduler_snk_in <= quant_sosi_arr(0);
+ p_bsn_sync : PROCESS(dp_bsn_sync_scheduler_src_out)
+ BEGIN
+ xin_sosi_arr <= quant_sosi_arr;
+ FOR I IN 0 TO c_sdp_P_pfb-1 LOOP
+ xin_sosi_arr(I).sop <= dp_bsn_sync_scheduler_src_out.sop;
+ xin_sosi_arr(I).eop <= dp_bsn_sync_scheduler_src_out.eop;
+ xin_sosi_arr(I).valid <= dp_bsn_sync_scheduler_src_out.valid;
+ xin_sosi_arr(I).sync <= dp_bsn_sync_scheduler_src_out.sync;
+ END LOOP;
+ END PROCESS;
+
+ u_mmp_dp_bsn_sync_scheduler : ENTITY dp_lib.mmp_dp_bsn_sync_scheduler
GENERIC MAP (
- g_nof_streams => c_sdp_P_pfb,
- g_nof_blk_per_sync => c_nof_blk_per_sync_max,
- g_nof_blk_per_sync_min => c_nof_blk_per_sync_min
+ g_block_size => c_sdp_N_fft,
+ g_ctrl_interval_size_min => c_sdp_xst_nof_blk_per_sync_min
)
PORT MAP (
dp_rst => dp_rst,
dp_clk => dp_clk,
mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_bsn_sync_scheduler_mosi,
+ reg_miso => reg_dp_bsn_sync_scheduler_miso,
- reg_mosi => reg_dp_sync_insert_v2_mosi,
- reg_miso => reg_dp_sync_insert_v2_miso,
+ in_sosi => dp_bsn_sync_scheduler_snk_in,
+ out_sosi => dp_bsn_sync_scheduler_src_out,
+
+ out_start => dp_bsn_sync_scheduler_out_start
- in_sosi_arr => quant_sosi_arr,
- out_sosi_arr => xin_sosi_arr
);
-
+
---------------------------------------------------------------
-- Crosslet Subband Select
---------------------------------------------------------------
@@ -170,6 +185,7 @@ BEGIN
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ start_trigger => dp_bsn_sync_scheduler_out_start,
out_crosslets_info => crosslets_info
);
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 842fa3175e688d1c4048b4417abd2a526e9e6579..f6d791cbd082ace1b76eb2d7022e3e1b889a596c 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -62,8 +62,9 @@ USE work.dp_stream_pkg.ALL;
ENTITY mmp_dp_bsn_sync_scheduler IS
GENERIC (
- g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256 -- = number of data valid per BSN block, must be >= 2
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 19530 -- Minimum interval size to use if MM write interval size is set too small.
);
PORT (
-- Clocks and reset
@@ -126,7 +127,8 @@ BEGIN
-- Register mapping
-- . Write
wr_ctrl_enable <= reg_wr( 0);
- ctrl_interval_size <= TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w));
+ ctrl_interval_size <= TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w)) WHEN
+ g_ctrl_interval_size_min < TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w)) ELSE g_ctrl_interval_size_min;
wr_start_bsn_64( c_word_w-1 DOWNTO 0) <= reg_wr( 3*c_word_w-1 DOWNTO 2*c_word_w); -- low word
wr_start_bsn_64(2*c_word_w-1 DOWNTO 1*c_word_w) <= reg_wr( 4*c_word_w-1 DOWNTO 3*c_word_w); -- high word