From a11818621e2d5449da5c0896fc3d0db067560ae1 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Mon, 22 Sep 2014 13:00:04 +0000 Subject: [PATCH] List of HDL libraries for the Arria10 FPGA technology. --- tools/quartus/hdl_libraries_ip_arria10.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 tools/quartus/hdl_libraries_ip_arria10.txt diff --git a/tools/quartus/hdl_libraries_ip_arria10.txt b/tools/quartus/hdl_libraries_ip_arria10.txt new file mode 100644 index 0000000000..b242a52ea2 --- /dev/null +++ b/tools/quartus/hdl_libraries_ip_arria10.txt @@ -0,0 +1,19 @@ +# VHDL +lpm = $MODEL_TECH_ALTERA_LIB/vhdl_libs/lpm +sgate = $MODEL_TECH_ALTERA_LIB/vhdl_libs/sgate +altera = $MODEL_TECH_ALTERA_LIB/vhdl_libs/altera +altera_mf = $MODEL_TECH_ALTERA_LIB/vhdl_libs/altera_mf +altera_lnsim = $MODEL_TECH_ALTERA_LIB/vhdl_libs/altera_lnsim +twentynm = $MODEL_TECH_ALTERA_LIB/vhdl_libs/twentynm +twentynm_hip = $MODEL_TECH_ALTERA_LIB/vhdl_libs/twentynm_hip +twentynm_hssi = $MODEL_TECH_ALTERA_LIB/vhdl_libs/twentynm_hssi + +# Verilog +lpm_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/lpm_ver +sgate_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/sgate_ver +altera_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/altera_ver +altera_mf_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/altera_mf_ver +altera_lnsim_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/altera_lnsim_ver +twentynm_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/twentynm_ver +twentynm_hip_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/twentynm_hip_ver +twentynm_hssi_ver = $MODEL_TECH_ALTERA_LIB/verilog_libs/twentynm_hssi_ver -- GitLab