diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 9053cdec41f7f8190a5cc6e1d4fa4159588f78d8..938f041e0b925aa9ef56ecc28289525872810002 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -305,12 +305,18 @@ BEGIN
           PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
     u_mm_file_reg_diag_data_buf  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
           PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
+    u_mm_file_ram_diag_data_buf  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
+          PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
     u_mm_file_reg_diag_bg  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
           PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+    u_mm_file_ram_diag_bg  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+          PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
     u_mm_file_reg_diagnostics  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
           PORT MAP(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
     u_mm_file_reg_tr_nonbonded  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
           PORT MAP(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+    u_mm_file_ram_mesh_diag_data_buf  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_MESH_DIAG_DATA_BUF")
+          PORT MAP(mm_rst, mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso );
     u_mm_file_reg_bsn_monitor  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
           PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
     ----------------------------------------------------------------------------