diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index 7287678951e0c44bf960b14cd0e09e7afd4e3489..53bf6710ae420869381a7494d22f2f548aff9c5f 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -60,6 +60,7 @@ PACKAGE tech_ddr_pkg IS
END RECORD;
FUNCTION func_tech_sel_ddr(g_technology : NATURAL; g_ddr3, g_ddr4 : t_c_tech_ddr) RETURN t_c_tech_ddr; -- Select DDR3 or DDR4 dependent on the technology
+ FUNCTION func_tech_sel_ddr(g_sel : BOOLEAN; a, b : t_c_tech_ddr) RETURN t_c_tech_ddr; -- Select DDR dependent on the boolean
FUNCTION func_tech_ddr_dq_address_w( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR address width for the DQ data at the PHY mts rate
FUNCTION func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR address width for the controller data at the by rsl=4 reduced rate
@@ -69,12 +70,25 @@ PACKAGE tech_ddr_pkg IS
-- a a
-- name mts master rank a row col ba dq dqs dm dbi bg ck cke cs cs_w odt term rsl rsl_w cqd burst burst_w
CONSTANT c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, TRUE, "DUAL ", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- maximum ranges for record field definitions
+
+ CONSTANT c_tech_ddr3_sim_8k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 1, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ CONSTANT c_tech_ddr3_sim_16k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 2, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ CONSTANT c_tech_ddr3_sim_128k : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 5, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ CONSTANT c_tech_ddr3_sim_1m : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 10, 8, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+
CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_single_rank_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 1, 1, 0, 1, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_single_rank_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 1, 1, 0, 1, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- maximum ranges for record field definitions
+
+ CONSTANT c_tech_ddr4_sim_4k : t_c_tech_ddr := ("DDR4", 800, TRUE, "DUAL ", 10, 1, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ CONSTANT c_tech_ddr4_sim_8k : t_c_tech_ddr := ("DDR4", 800, TRUE, "DUAL ", 10, 2, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ CONSTANT c_tech_ddr4_sim_16k : t_c_tech_ddr := ("DDR4", 800, TRUE, "DUAL ", 10, 3, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ CONSTANT c_tech_ddr4_sim_128k : t_c_tech_ddr := ("DDR4", 800, TRUE, "DUAL ", 10, 6, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ CONSTANT c_tech_ddr4_sim_1m : t_c_tech_ddr := ("DDR4", 800, TRUE, "DUAL ", 10, 9, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+
CONSTANT c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7);
-- PHY in, inout and out signal records
@@ -168,6 +182,11 @@ PACKAGE BODY tech_ddr_pkg IS
END CASE;
END;
+ FUNCTION func_tech_sel_ddr(g_sel : BOOLEAN; a, b : t_c_tech_ddr) RETURN t_c_tech_ddr IS
+ BEGIN
+ IF g_sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
+ END;
+
FUNCTION func_tech_ddr_dq_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
BEGIN
IF c_ddr.name="DDR3" THEN RETURN c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w; END IF; -- PHY address
@@ -181,9 +200,7 @@ PACKAGE BODY tech_ddr_pkg IS
END;
FUNCTION func_tech_ddr_ctlr_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
- CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
BEGIN
--- if c_ddr.name="DDR4" THEN RETURN 32; END IF; -- FIXME: temporary fix from Leon to fix quartus width error in /home/hiemstra/svn/UniBoard_FP7/RadioHDL/trunk/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd Line=153
RETURN c_ddr.dq_w*c_ddr.rsl; -- CTLR data
END;
@@ -194,7 +211,11 @@ PACKAGE BODY tech_ddr_pkg IS
CONSTANT c_module_nof_bytes_w : NATURAL := c_dq_address_w + c_dq_nof_bytes_w;
CONSTANT c_1GB_w : NATURAL := 30;
BEGIN
- RETURN 2**(c_module_nof_bytes_w-c_1GB_w);
+ IF c_module_nof_bytes_w < c_1GB_w THEN
+ RETURN 0;
+ ELSE
+ RETURN 2**(c_module_nof_bytes_w-c_1GB_w);
+ END IF;
END;
END tech_ddr_pkg;