From a06818263378ce3b4cfdacd4c540f2ef8bad9fdd Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 19 Nov 2014 13:44:13 +0000
Subject: [PATCH] Renamed trc_rst into tr_rst. Use '_arr' for tech_xaui ports.
---
libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd | 47 +++++++++++------------
1 file changed, 23 insertions(+), 24 deletions(-)
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
index 6d666c0660..44bbd24903 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
@@ -100,7 +100,7 @@ ARCHITECTURE str OF tr_xaui IS
SIGNAL i_rx_rst : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
SIGNAL i_tx_rst : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
- SIGNAL trc_rst : STD_LOGIC;
+ SIGNAL tr_rst : STD_LOGIC;
SIGNAL i_rx_clk : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
--XGMII data and control combined:
@@ -160,30 +160,29 @@ BEGIN
g_nof_xaui => g_nof_xaui
)
PORT MAP (
- tr_clk => tr_clk,
- trc_rst => trc_rst,
+ tr_clk => tr_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- cal_rec_clk => cal_rec_clk,
+ cal_rec_clk => cal_rec_clk,
- tx_clk => tx_clk,
- rx_clk => i_rx_clk,
+ tx_clk_arr => tx_clk,
+ rx_clk_arr => i_rx_clk,
- crc_rx_ready => crc_rx_ready,
- crc_tx_ready => crc_tx_ready,
+ crc_rx_ready_arr => crc_rx_ready,
+ crc_tx_ready_arr => crc_tx_ready,
- a_rx_channelaligned => a_rx_channelaligned,
+ a_rx_channelaligned_arr => a_rx_channelaligned,
- xgmii_tx_dc => xgmii_tx_dc,
- xgmii_rx_dc => xgmii_rx_dc,
+ xgmii_tx_dc_arr => xgmii_tx_dc,
+ xgmii_rx_dc_arr => xgmii_rx_dc,
- xaui_rx => xaui_rx,
- xaui_tx => xaui_tx,
+ xaui_rx_arr => xaui_rx,
+ xaui_tx_arr => xaui_tx,
- xaui_mosi => xaui_mosi,
- xaui_miso => xaui_miso
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso
);
END GENERATE;
@@ -195,7 +194,7 @@ BEGIN
)
PORT MAP (
tr_clk => tr_clk,
- trc_rst => trc_rst,
+ tr_rst => tr_rst,
cal_rec_clk => cal_rec_clk,
@@ -218,7 +217,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Clock and reset generation
-----------------------------------------------------------------------------
- u_areset_trc_rst : ENTITY common_lib.common_areset
+ u_areset_tr_rst : ENTITY common_lib.common_areset
GENERIC MAP(
g_rst_level => '1',
g_delay_len => 4
@@ -226,7 +225,7 @@ BEGIN
PORT MAP(
clk => tr_clk,
in_rst => '0',
- out_rst => trc_rst
+ out_rst => tr_rst
);
gen_nof_xaui : FOR i IN g_nof_xaui-1 DOWNTO 0 GENERATE
@@ -338,7 +337,7 @@ BEGIN
PORT MAP (
gs_sim => g_sim,
- rst => trc_rst,
+ rst => tr_rst,
clk => tr_clk,
mdio_en_evt => mdio_en_evt(i),
@@ -363,7 +362,7 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- mdio_rst => trc_rst,
+ mdio_rst => tr_rst,
mdio_clk => tr_clk,
sla_in => mdio_mosi_arr(i),
@@ -391,7 +390,7 @@ BEGIN
g_mdio_post_rst_cycles => 250000
)
PORT MAP (
- rst => trc_rst,
+ rst => tr_rst,
clk => tr_clk,
mdio_rst => ctlr_mdio_rst(i),
@@ -420,7 +419,7 @@ BEGIN
g_mdio_post_rst_cycles => 250000
)
PORT MAP (
- rst => trc_rst,
+ rst => tr_rst,
clk => tr_clk,
mdio_rst => ctlr_mdio_rst(i),
--
GitLab