diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 483d9968983f1978dfc20c426639d7d875cac575..509125ec50daa4d37b6adc61a299461cad233b20 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -23,6 +23,7 @@ parameters:
- { name: c_V_sample_delay, value: 4096 }
- { name: c_V_si_db_large, value: 131072 }
- { name: c_V_si_db, value: 1024 }
+ - { name: c_V_si_histogram, value: 512 }
- { name: c_W_fir_coef, value: 16 }
- { name: c_W_subband, value: 18 }
- { name: c_P_pfb, value: c_S_pn / c_Q_fft } # = 6
@@ -141,7 +142,15 @@ peripherals:
mm_port_names:
- REG_WG
- RAM_WG
-
+
+ - peripheral_name: st/st_histogram
+ parameter_overrides:
+ - { name: g_nof_instances, value: c_S_pn }
+ - { name: g_nof_bins, value: c_V_si_histogram }
+ - { name: g_nof_data_per_sync, value: c_nof_clk_per_pps}
+ mm_port_names:
+ - RAM_ST_HISTOGRAM
+
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
@@ -214,14 +223,10 @@ peripherals:
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
- - peripheral_name: dp/dp_bsn_scheduler
+ - peripheral_name: dp/dp_bsn_sync_scheduler
peripheral_group: xsub
mm_port_names:
- - REG_BSN_SCHEDULER_XSUB
-
- - peripheral_name: dp/dp_sync_insert_v2
- mm_port_names:
- - REG_DP_SYNC_INSERT_V2
+ - REG_BSN_SYNC_SCHEDULER_XSUB
- peripheral_name: st/st_xst_for_sdp
parameter_overrides:
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
index dca487687ea75fb0a4b6f8d7a0eb4c0f7d709756..f0239e54ab205cd43041c62ddad0f2a0cd40dcf0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -18,511 +18,521 @@ number_of_columns = 13
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
-# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
-# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
- ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
- PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
- - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
- - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
- - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
- - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
- - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
- - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
- - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
- - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
- - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
- - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
- REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
- RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
- AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
- AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
- - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
- - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
- - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
- - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
- - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
- - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x0001c000 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x0001c001 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x0001c002 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x0001c003 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x0001c004 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x0001c005 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x0001c006 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x0001c007 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x0001c008 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x0001c009 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x0001c00a 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x0001c00b 1 RW uint32 b[15:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
- - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - 256
- - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
- - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
- - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x00030001 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x00030002 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x00030003 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - - 1024
- REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x00044000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x00044001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004a001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x0004a002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_statistics_per_packet 0x0004a003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_bytes_per_statistic 0x0004a004 1 RW uint32 b[7:0] - - -
- - - - - sdp_nof_signal_inputs 0x0004a005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x0004a006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_sst_signal_input_index 0x0004a006 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_sst_reserved 0x0004a006 1 RW uint32 b[31:8] - - -
- - - - - sdp_integration_interval 0x0004a007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x0004a008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0004a00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0004a00c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004a00d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004a00e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004a00f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0004a010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0004a011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0004a012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0004a013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0004a014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0004a015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0004a016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0004a017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0004a018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0004a019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0004a01a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004a01b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004a01c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004a01d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004a01e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004a01f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0004a020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0004a021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0004a022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0004a023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0004a024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0004a025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0004a026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0004a027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004a028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0004a029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004a02a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0004a02b 1 RW uint32 b[15:0] - - -
- REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x0004c000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004c001 - - - b[31:0] b[63:32] - -
- REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0004e000 1 RW uint32 b[31:0] - - -
- RAM_ST_XSQ 1 9 RAM data 0x00050000 144 RW cint64_ir b[31:0] b[31:0] - 1028
- - - - - - 0x00050001 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00058000 15 RW uint32 b[31:0] - - -
- - - - - step 0x0005800f 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x0005a000 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x0005c000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005c001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x0005c002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x0005c003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x0005c004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x0005c005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x0005c006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_xst_signal_input_b_index 0x0005c006 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_xst_signal_input_a_index 0x0005c006 1 RW uint32 b[15:8] - - -
- - - - - sdp_data_id_xst_subband_index 0x0005c006 1 RW uint32 b[24:16] - - -
- - - - - sdp_data_id_xst_reserved 0x0005c006 1 RW uint32 b[31:25] - - -
- - - - - sdp_integration_interval 0x0005c007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x0005c008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x0005c009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0005c00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0005c00b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0005c00c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0005c00d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0005c00e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0005c00f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0005c010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0005c011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0005c012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0005c013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0005c014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0005c015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0005c016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0005c017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0005c018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0005c019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0005c01a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0005c01b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0005c01c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0005c01d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0005c01e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0005c01f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0005c020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0005c021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0005c022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0005c023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0005c024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0005c025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0005c026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0005c027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005c028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0005c029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005c02a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0005c02b 1 RW uint32 b[15:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0005e000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00064000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x0006c000 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x0006c001 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x0006e000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x0006e001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x0006e002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x0006e003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x0006e004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x0006e005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x0006e006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x0006e007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006e008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x0006e009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0006e00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0006e00b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0006e00c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0006e00d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0006e00e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0006e00f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0006e010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0006e011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0006e012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0006e013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0006e014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0006e015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0006e016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0006e017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0006e018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0006e019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0006e01a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0006e01b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0006e01c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0006e01d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0006e01e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0006e01f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0006e020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0006e021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0006e022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0006e023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0006e024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0006e025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0006e026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006e027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0006e028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006e029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00070000 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x00072000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x00072001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x00074000 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00076000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00076001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00076002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00076003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00076004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00076005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00076006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00076006 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00076006 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00076007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00076008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00076009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0007600a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0007600b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0007600c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0007600d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0007600e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0007600f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00076010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00076011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00076012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00076013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00076014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00076015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00076016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00076017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00076018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00076019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0007601a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0007601b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0007601c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0007601d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0007601e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0007601f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00076020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00076021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00076022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00076023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00076024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00076025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00076026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00076027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00076028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00076029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0007602a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0007602b 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00078000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x00078001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00078002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00078040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00078080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000780c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000780c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000780c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000780c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00078100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00078140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00078800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00078801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00078802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00078803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00078804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00078805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00078806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00078807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00078808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00078809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0007880a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0007880b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00078818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00078c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00078c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00078c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00078c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00078c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00078c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00078c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00078c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00078c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00078c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00078c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00078c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00078c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00078c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00078c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00078c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00078c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00078c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00078c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00078c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00078c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00078c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00078c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00078c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00078c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00078c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00078c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00078c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00078c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00078c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00078c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00078c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00079001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00079040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00079080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000790c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000790c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00079100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00079140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00079141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00079142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00079180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00079181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00079182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00079183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00079184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00079185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00079186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00079187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00079190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00079191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00079192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00079193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00079194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00079195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00079196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00079197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000791a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00079200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00079201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00079202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00079801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00079c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00079c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00079c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00079c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00079c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00079c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00079c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00079c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00079c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00079c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00079c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00079c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00079c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00079c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00079c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00079c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00079c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00079c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00079c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00079c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00079c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00079c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00079c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00079c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00079c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00079c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00079c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00079c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00079c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00079c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00079c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00079c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0007a000 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x0007a000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x0007a000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x0001c000 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0001c001 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0001c002 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0001c003 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0001c004 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0001c005 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0001c006 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0001c007 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0001c008 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0001c009 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0001c00a 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0001c00b 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - 256
+ - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
+ RAM_ST_HISTOGRAM 1 12 RAM data 0x00030000 512 RW uint32 b[31:0] b[27:0] - 512
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00032000 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x00032001 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00032002 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00032003 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00034000 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00034001 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
+ REG_SI 1 1 REG enable 0x0003c000 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00040000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00044000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x00046000 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00048000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x00048001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x0004c000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004e000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004e001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0004e002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x0004e003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x0004e004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x0004e005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0004e006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x0004e006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x0004e006 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x0004e007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0004e008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0004e009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0004e00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0004e00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0004e00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004e00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004e00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004e00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004e010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0004e011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0004e012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0004e013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0004e014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0004e015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0004e016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0004e017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0004e018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0004e019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004e01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004e01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004e01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004e01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004e01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004e01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004e020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0004e021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0004e022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0004e023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0004e024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0004e025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0004e026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0004e027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004e028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0004e029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004e02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0004e02b 1 RW uint32 b[15:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00050000 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x00050001 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x00050002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00050003 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x00050004 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00050005 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x00050006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00050007 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x00050008 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x00050009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005000a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0005000b 1 RO uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 9 RAM data 0x00054000 144 RW cint64_ir b[31:0] b[31:0] - 1024
+ - - - - - 0x00054001 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00058000 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0005800f 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x0005a000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x0005c000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005c001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x0005c002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x0005c003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x0005c004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x0005c005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0005c006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_xst_signal_input_b_index 0x0005c006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_xst_signal_input_a_index 0x0005c006 1 RW uint32 b[15:8] - - -
+ - - - - sdp_data_id_xst_subband_index 0x0005c006 1 RW uint32 b[24:16] - - -
+ - - - - sdp_data_id_xst_reserved 0x0005c006 1 RW uint32 b[31:25] - - -
+ - - - - sdp_integration_interval 0x0005c007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0005c008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0005c009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0005c00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0005c00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0005c00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0005c00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0005c00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0005c00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0005c010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0005c011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0005c012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0005c013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0005c014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0005c015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0005c016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0005c017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0005c018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0005c019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0005c01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0005c01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0005c01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0005c01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0005c01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0005c01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0005c020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0005c021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0005c022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0005c023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0005c024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0005c025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0005c026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0005c027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005c028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0005c029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005c02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0005c02b 1 RW uint32 b[15:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0005e000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00064000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x0006c000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x0006c001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x0006e000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0006e001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0006e002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x0006e003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x0006e004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x0006e005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x0006e006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x0006e007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006e008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x0006e009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0006e00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0006e00b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0006e00c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0006e00d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0006e00e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0006e00f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0006e010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0006e011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0006e012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0006e013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0006e014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0006e015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0006e016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0006e017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0006e018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0006e019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0006e01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0006e01b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0006e01c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0006e01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0006e01e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0006e01f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0006e020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0006e021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0006e022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0006e023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0006e024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0006e025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0006e026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006e027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0006e028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006e029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00070000 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00072000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x00072001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x00074000 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00076000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00076001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00076002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00076003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00076004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00076005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00076006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00076006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00076006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00076007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00076008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00076009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0007600a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0007600b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0007600c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0007600d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0007600e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0007600f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00076010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00076011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00076012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00076013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00076014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00076015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00076016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00076017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00076018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00076019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0007601a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0007601b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0007601c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0007601d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0007601e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0007601f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00076020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00076021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00076022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00076023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00076024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00076025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00076026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00076027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00076028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00076029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0007602a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0007602b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00078000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00078001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00078002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00078040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00078080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000780c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000780c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000780c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000780c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00078100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00078140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00078800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00078801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00078802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00078803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00078804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00078805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00078806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00078807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00078808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00078809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0007880a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0007880b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00078818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00078c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00078c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00078c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00078c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00078c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00078c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00078c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00078c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00078c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00078c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00078c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00078c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00078c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00078c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00078c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00078c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00078c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00078c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00078c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00078c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00078c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00078c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00078c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00078c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00078c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00078c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00078c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00078c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00078c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00078c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00078c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00078c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00079001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00079040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00079080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000790c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000790c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00079100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00079140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00079141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00079142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00079180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00079181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00079182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00079183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00079184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00079185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00079186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00079187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00079190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00079191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00079192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00079193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00079194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00079195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00079196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00079197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000791a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00079200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00079201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00079202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00079801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00079c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00079c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00079c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00079c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00079c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00079c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00079c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00079c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00079c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00079c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00079c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00079c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00079c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00079c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00079c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00079c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00079c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00079c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00079c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00079c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00079c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00079c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00079c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00079c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00079c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00079c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00079c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00079c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00079c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00079c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00079c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00079c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0007a000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0007a000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0007a000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
index bf8da8d17ff91054e84c11791953f980112008f7..bea7b3e1fda3b7297dc06601b7ba20ee2898fcbb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -18,511 +18,521 @@ number_of_columns = 13
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
-# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
-# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
- ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
- PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
- - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
- - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
- - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
- - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
- - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
- - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
- - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
- - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
- - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
- - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
- REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x0002d038 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0002d020 6 RO uint32 b[31:0] - - -
- RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
- AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
- AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x0002d074 1 RO uint32 b[29:0] - - -
- - - - - stable 0x0002d074 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x0002d074 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x0002d075 1 RW uint32 b[27:0] - - -
- - - - - edge 0x0002d075 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x0002d076 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x0002d040 1 WO uint32 b[23:0] - - -
- - - - - rden 0x0002d041 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x0002d042 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x0002d043 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x0002d044 1 WO uint32 b[0:0] - - -
- - - - - busy 0x0002d045 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x0002d046 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002d072 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x0002d070 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002d06e 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x0002d06f 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x0002d06c 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x0002d048 1 WO uint32 b[31:0] - - -
- - - - - param 0x0002d049 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x0002d04a 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x0002d04b 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x0002d04c 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x0002d04d 1 WO uint32 b[23:0] - - -
- - - - - busy 0x0002d04e 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x0002d010 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x0002d011 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x0002d012 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x0002d013 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x0002d014 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x0002d015 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x0002d016 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x0002d017 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x0002d018 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x0002d019 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x0002d01a 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x0002d01b 1 RW uint32 b[15:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x0002d062 1 RW uint32 b[30:0] - - -
- - - - - reset 0x0002d062 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_dll_ctrl 0x0002c014 1 RW uint32 b[16:0] - - 256
- - - - - rx_syncn_sysref_ctrl 0x0002c015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x0002c015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x0002c015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x0002c015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x0002c018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x0002c019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x0002c020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x0002c020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x0002c021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x0002c022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x0002c023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x0002c025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x0002c025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x0002c025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x0002c025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x0002c026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x0002c026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x0002c026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x0002c026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x0002c026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x0002c026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x0002c026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x0002c026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0002c03c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0002c03d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0002c03e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0002c03f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x0002d030 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x0002d030 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x0002d031 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x0002d032 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002d033 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x0002d034 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0002d068 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002d069 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x00000d00 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x00000d00 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00000d01 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00000d02 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00000d03 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d40 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x00000d41 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x00000d42 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x00000d43 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024
- REG_SI 1 1 REG enable 0x0002d06a 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x0002d066 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x00028000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x00028001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x0002d060 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_statistics_per_packet 0x00000c43 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_bytes_per_statistic 0x00000c44 1 RW uint32 b[7:0] - - -
- - - - - sdp_nof_signal_inputs 0x00000c45 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000c46 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_sst_signal_input_index 0x00000c46 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_sst_reserved 0x00000c46 1 RW uint32 b[31:8] - - -
- - - - - sdp_integration_interval 0x00000c47 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x00000c4f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000c50 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000c51 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000c52 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000c53 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000c54 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000c55 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000c56 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000c57 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000c58 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000c59 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00000c5a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x00000c5b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x00000c5c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x00000c5d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x00000c5e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x00000c5f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000c60 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000c61 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000c62 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000c63 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000c64 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000c65 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000c66 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000c67 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c68 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
- REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x0002d05c 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002d05d - - - b[31:0] b[63:32] - -
- REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0002d05e 1 RW uint32 b[31:0] - - -
- RAM_ST_XSQ 1 9 RAM data 0x00018000 144 RW cint64_ir b[31:0] b[31:0] - 1028
- - - - - - 0x00018001 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x0002d000 15 RW uint32 b[31:0] - - -
- - - - - step 0x0002d00f 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x00000c02 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00000043 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00000044 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00000045 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000046 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_xst_signal_input_b_index 0x00000046 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_xst_signal_input_a_index 0x00000046 1 RW uint32 b[15:8] - - -
- - - - - sdp_data_id_xst_subband_index 0x00000046 1 RW uint32 b[24:16] - - -
- - - - - sdp_data_id_xst_reserved 0x00000046 1 RW uint32 b[31:25] - - -
- - - - - sdp_integration_interval 0x00000047 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0000004f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000050 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000051 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000052 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000053 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000054 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000055 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000056 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000057 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000058 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000059 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0000005a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0000005b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0000005c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0000005d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0000005e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0000005f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000060 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000061 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000062 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000063 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000064 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000065 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000066 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000067 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000068 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x0002d058 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x0002d059 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00000c83 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00000c84 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00000c85 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00000c86 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00000c87 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c88 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x00000c8a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x00000c8b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x00000c8c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x00000c8d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x00000c8e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000c8f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000c90 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000c91 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000c92 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000c93 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000c94 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000c95 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000c96 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000c97 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000c98 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00000c99 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x00000c9a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x00000c9b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x00000c9c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x00000c9d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x00000c9e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000c9f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000ca0 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000ca1 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000ca2 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000ca3 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000ca4 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000ca5 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000ca6 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000ca7 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000ca8 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000ca9 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x0002d054 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x0002d050 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00000081 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00000082 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00000083 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00000084 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00000085 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000086 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00000086 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00000086 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00000087 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000088 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0000008a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0000008b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0000008c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0000008d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0000008e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0000008f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000090 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000091 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000092 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000093 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000094 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000095 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000096 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000097 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000098 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000099 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0000009a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0000009b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0000009c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0000009d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0000009e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0000009f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x000000a0 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x000000a1 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x000000a2 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x000000a3 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x000000a4 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x000000a5 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x000000a6 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x000000a7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000000a8 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x000000a9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000000aa - - - b[15:0] b[47:32] - -
- - - - - word_align 0x000000ab 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00002000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x00002001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00002002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00002040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00002080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000020c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000020c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000020c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000020c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00002100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00002140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00002800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00002801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00002802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00002803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00002804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00002805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00002806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00002807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00002808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00002809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0000280a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0000280b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00002818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00002c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00002c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00002c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00002c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00002c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00002c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00002c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00002c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00002c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00002c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00002c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00002c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00002c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00002c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00002c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00002c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00002c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00002c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00002c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00002c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00002c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00002c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00002c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00002c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00002c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00002c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00002c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00002c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00002c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00002c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00002c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00003001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00003040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00003080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000030c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000030c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00003100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00003140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00003141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00003142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00003180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00003181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00003182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00003183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00003184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00003185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00003186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00003187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00003190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00003191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00003192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00003193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00003194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00003195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00003196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00003197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000031a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00003200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00003201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00003202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00003801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00003c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00003c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00003c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00003c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00003c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00003c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00003c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00003c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00003c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00003c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00003c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00003c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00003c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00003c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00003c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00003c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00003c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00003c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00003c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00003c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00003c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00003c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00003c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00003c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00003c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00003c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00003c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00003c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00003c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00003c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00003c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0002d064 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x0002d064 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x0002d064 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0002f048 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0002f030 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x0002f06c 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x0002f06c 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x0002f06c 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x0002f06d 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x0002f06d 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0002f06e 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x0002f050 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x0002f051 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x0002f052 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x0002f053 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x0002f054 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x0002f055 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x0002f056 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002f082 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x0002f080 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002f07e 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0002f07f 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x0002f07c 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0002f058 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0002f059 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0002f05a 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0002f05b 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0002f05c 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0002f05d 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0002f05e 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x0002f020 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0002f021 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0002f022 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0002f023 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0002f024 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0002f025 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0002f026 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0002f027 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0002f028 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0002f029 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0002f02a 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0002f02b 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0002f072 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0002f072 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_dll_ctrl 0x0002e014 1 RW uint32 b[16:0] - - 256
+ - - - - rx_syncn_sysref_ctrl 0x0002e015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x0002e015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x0002e015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x0002e015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x0002e018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x0002e019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x0002e020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x0002e020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x0002e021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x0002e022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x0002e023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x0002e025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x0002e025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x0002e025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x0002e025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x0002e026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x0002e026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x0002e026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x0002e026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x0002e026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x0002e026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x0002e026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x0002e026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002e03c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002e03d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002e03e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002e03f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x0002f040 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x0002f040 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x0002f041 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x0002f042 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002f043 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x0002f044 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0002f078 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002f079 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00000d00 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00000d00 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00000d01 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00000d02 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00000d03 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024
+ RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d40 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x00000d41 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00000d42 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d43 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024
+ REG_SI 1 1 REG enable 0x0002f07a 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x0002c000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x0002f076 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00028000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x00028001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x0002f070 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x00000c43 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x00000c44 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x00000c45 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000c46 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x00000c46 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x00000c46 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x00000c47 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c4f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c50 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c51 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c52 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c53 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c54 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c55 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c56 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c57 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c58 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c59 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c5a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c5b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c5c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c5d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c5e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c5f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000c60 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000c61 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000c62 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000c63 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000c64 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000c65 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000c66 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000c67 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c68 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x0002f000 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x0002f001 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x0002f002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002f003 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x0002f004 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002f005 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x0002f006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002f007 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x0002f008 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x0002f009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002f00a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0002f00b 1 RO uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 9 RAM data 0x00018000 144 RW cint64_ir b[31:0] b[31:0] - 1024
+ - - - - - 0x00018001 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x0002f010 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0002f01f 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x00000c02 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000043 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000044 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000045 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000046 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_xst_signal_input_b_index 0x00000046 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_xst_signal_input_a_index 0x00000046 1 RW uint32 b[15:8] - - -
+ - - - - sdp_data_id_xst_subband_index 0x00000046 1 RW uint32 b[24:16] - - -
+ - - - - sdp_data_id_xst_reserved 0x00000046 1 RW uint32 b[31:25] - - -
+ - - - - sdp_integration_interval 0x00000047 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000004f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000050 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000051 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000052 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000053 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000054 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000055 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000056 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000057 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000058 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000059 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0000005a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000005b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000005c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000005d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000005e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000005f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000060 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000061 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000062 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000063 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000064 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000065 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000066 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000067 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000068 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x0002f068 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x0002f069 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00000c83 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00000c84 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00000c85 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00000c86 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00000c87 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c88 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x00000c8a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x00000c8b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c8c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c8d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c8e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c8f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c90 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c91 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c92 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c93 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c94 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c95 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c96 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c97 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c98 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c99 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c9a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c9b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c9c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c9d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c9e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000c9f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000ca0 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000ca1 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000ca2 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000ca3 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000ca4 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000ca5 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000ca6 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000ca7 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000ca8 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000ca9 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0002f064 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x0002f060 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000081 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000082 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000083 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000084 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000085 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000086 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00000086 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00000086 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00000087 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000088 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0000008a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0000008b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0000008c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000008d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000008e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000008f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000090 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000091 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000092 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000093 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000094 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000095 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000096 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000097 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000098 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000099 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0000009a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000009b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000009c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000009d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000009e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000009f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x000000a0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x000000a1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x000000a2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x000000a3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x000000a4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x000000a5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x000000a6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x000000a7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000a8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x000000a9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000aa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x000000ab 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00006040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00006080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000060c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000060c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000060c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000060c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00006100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00006140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00006800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00006801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00006802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00006803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00006804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00006805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00006806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00006807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00006808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00006809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0000680a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0000680b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00006818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00006c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00006c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00006c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00006c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00006c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00006c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00006c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00006c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00006c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00006c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00006c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00006c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00006c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00006c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00006c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00006c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00006c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00006c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00006c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00006c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00006c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00006c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00006c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00006c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00006c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00006c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00006c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00006c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00006c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00006c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00006c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00007001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00007040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00007080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000070c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000070c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00007100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00007140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00007141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00007142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00007180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00007181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00007182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00007183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00007184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00007185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00007186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00007187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00007190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00007191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00007192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00007193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00007194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00007195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00007196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00007197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000071a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00007200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00007201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00007202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00007801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00007c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00007c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00007c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00007c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00007c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00007c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00007c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00007c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00007c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00007c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00007c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00007c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00007c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00007c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00007c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00007c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00007c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00007c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00007c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00007c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00007c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00007c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00007c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00007c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00007c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00007c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00007c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00007c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00007c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00007c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0002f074 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0002f074 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0002f074 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index c106dec2035631034d3a53d837eee2ac874e7c52..5ebf7fc59cf7c62788b277e3550eb49a528bfb26 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xBC000' end='0xBC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xBC040' end='0xBC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xBC080' end='0xBC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xBC0C0' end='0xBC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xBC100' end='0xBC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xBC120' end='0xBC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xBC140' end='0xBC160' datawidth='32' /><slave name='reg_remu.mem' start='0xBC160' end='0xBC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xBC180' end='0xBC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xBC190' end='0xBC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xBC1A0' end='0xBC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xBC1B0' end='0xBC1C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xBC1C0' end='0xBC1C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xBC1C8' end='0xBC1D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xBC1D0' end='0xBC1D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xBC1D8' end='0xBC1E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xBC1E0' end='0xBC1E8' datawidth='32' /><slave name='reg_si.mem' start='0xBC1E8' end='0xBC1F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xBC1F0' end='0xBC1F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC1F8' end='0xBC200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC200' end='0xBC208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC208' end='0xBC210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC210' end='0xBC218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xBC000' end='0xBC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xBC040' end='0xBC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xBC080' end='0xBC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xBC0C0' end='0xBC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xBC100' end='0xBC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xBC120' end='0xBC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xBC140' end='0xBC160' datawidth='32' /><slave name='reg_remu.mem' start='0xBC160' end='0xBC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xBC180' end='0xBC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xBC190' end='0xBC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xBC1A0' end='0xBC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xBC1B0' end='0xBC1C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xBC1C0' end='0xBC1C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xBC1C8' end='0xBC1D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xBC1D0' end='0xBC1D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xBC1D8' end='0xBC1E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xBC1E0' end='0xBC1E8' datawidth='32' /><slave name='reg_si.mem' start='0xBC1E8' end='0xBC1F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xBC1F0' end='0xBC1F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC1F8' end='0xBC200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC200' end='0xBC208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC208' end='0xBC210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC210' end='0xBC218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
index e41248d531721555270335dfb2bf93e7bbd6817e..9589b266b6bdb253288c026f85f5788db8c1c308 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,6 +605,10 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>12</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -697,6 +701,10 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>12</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -766,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -775,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">13</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -838,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -902,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -971,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1366,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1398,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_histogram.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
similarity index 96%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
index a523d8af9523229c23c36c2005b7d4231b7e137d..0980bf5700a86bc8295e098702dd601769575e0f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,6 +605,10 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -697,6 +701,10 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -766,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -775,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -838,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -902,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -971,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1366,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1398,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index d6f321e7ef38e0d597aceea0693177e2c39b7e8e..f5eeb361be880d8c3a74f8e7048713272ea6d137 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "720896";
+ value = "753664";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "737760";
+ value = "770576";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "737688";
+ value = "770504";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "737648";
+ value = "770480";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "720896";
type = "String";
}
}
@@ -318,6 +318,22 @@
type = "String";
}
}
+ element ram_st_histogram
+ {
+ datum _sortIndex
+ {
+ value = "56";
+ type = "int";
+ }
+ }
+ element ram_st_histogram.mem
+ {
+ datum baseAddress
+ {
+ value = "32768";
+ type = "String";
+ }
+ }
element ram_st_sst
{
datum _sortIndex
@@ -338,7 +354,7 @@
{
datum _sortIndex
{
- value = "54";
+ value = "52";
type = "int";
}
}
@@ -394,7 +410,7 @@
{
datum baseAddress
{
- value = "737632";
+ value = "770464";
type = "String";
}
}
@@ -426,39 +442,39 @@
{
datum baseAddress
{
- value = "737712";
+ value = "770528";
type = "String";
}
}
- element reg_bsn_scheduler_xsub
+ element reg_bsn_source_v2
{
datum _sortIndex
{
- value = "53";
+ value = "24";
type = "int";
}
}
- element reg_bsn_scheduler_xsub.mem
+ element reg_bsn_source_v2.mem
{
datum baseAddress
{
- value = "737664";
+ value = "770304";
type = "String";
}
}
- element reg_bsn_source_v2
+ element reg_bsn_sync_scheduler_xsub
{
datum _sortIndex
{
- value = "24";
+ value = "55";
type = "int";
}
}
- element reg_bsn_source_v2.mem
+ element reg_bsn_sync_scheduler_xsub.mem
{
datum baseAddress
{
- value = "737472";
+ value = "770048";
type = "String";
}
}
@@ -466,7 +482,7 @@
{
datum _sortIndex
{
- value = "52";
+ value = "51";
type = "int";
}
}
@@ -474,7 +490,7 @@
{
datum baseAddress
{
- value = "737280";
+ value = "770112";
type = "String";
}
}
@@ -506,7 +522,7 @@
{
datum baseAddress
{
- value = "737704";
+ value = "770520";
type = "String";
}
}
@@ -526,22 +542,6 @@
type = "String";
}
}
- element reg_dp_sync_insert_v2
- {
- datum _sortIndex
- {
- value = "51";
- type = "int";
- }
- }
- element reg_dp_sync_insert_v2.mem
- {
- datum baseAddress
- {
- value = "737672";
- type = "String";
- }
- }
element reg_dp_xonoff
{
datum _sortIndex
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "737616";
+ value = "770448";
type = "String";
}
}
@@ -575,7 +575,7 @@
{
datum baseAddress
{
- value = "737752";
+ value = "770568";
type = "String";
}
}
@@ -596,7 +596,7 @@
{
datum baseAddress
{
- value = "737744";
+ value = "770560";
type = "String";
}
}
@@ -617,7 +617,7 @@
{
datum baseAddress
{
- value = "737536";
+ value = "770368";
type = "String";
}
}
@@ -633,7 +633,7 @@
{
datum baseAddress
{
- value = "737504";
+ value = "770336";
type = "String";
}
}
@@ -654,7 +654,7 @@
{
datum baseAddress
{
- value = "737408";
+ value = "770240";
type = "String";
}
}
@@ -691,7 +691,7 @@
{
datum baseAddress
{
- value = "737736";
+ value = "770552";
type = "String";
}
}
@@ -712,7 +712,7 @@
{
datum baseAddress
{
- value = "737728";
+ value = "770544";
type = "String";
}
}
@@ -728,7 +728,7 @@
{
datum baseAddress
{
- value = "737696";
+ value = "770512";
type = "String";
}
}
@@ -744,7 +744,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "98304";
type = "String";
}
}
@@ -765,7 +765,7 @@
{
datum baseAddress
{
- value = "737568";
+ value = "770400";
type = "String";
}
}
@@ -781,7 +781,7 @@
{
datum baseAddress
{
- value = "737344";
+ value = "770176";
type = "String";
}
}
@@ -797,7 +797,7 @@
{
datum baseAddress
{
- value = "737720";
+ value = "770536";
type = "String";
}
}
@@ -813,7 +813,7 @@
{
datum baseAddress
{
- value = "737600";
+ value = "770432";
type = "String";
}
}
@@ -829,7 +829,7 @@
{
datum baseAddress
{
- value = "737680";
+ value = "770496";
type = "String";
}
}
@@ -837,7 +837,7 @@
{
datum _sortIndex
{
- value = "55";
+ value = "53";
type = "int";
}
}
@@ -885,7 +885,7 @@
{
datum _sortIndex
{
- value = "56";
+ value = "54";
type = "int";
}
}
@@ -1536,6 +1536,41 @@
internal="ram_st_bst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="ram_st_histogram_address"
+ internal="ram_st_histogram.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_clk"
+ internal="ram_st_histogram.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_read"
+ internal="ram_st_histogram.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_readdata"
+ internal="ram_st_histogram.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_reset"
+ internal="ram_st_histogram.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_write"
+ internal="ram_st_histogram.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_writedata"
+ internal="ram_st_histogram.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="ram_st_sst_address"
internal="ram_st_sst.address"
@@ -1766,73 +1801,73 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_address"
- internal="reg_bsn_scheduler_xsub.address"
+ name="reg_bsn_source_v2_address"
+ internal="reg_bsn_source_v2.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_clk"
- internal="reg_bsn_scheduler_xsub.clk"
+ name="reg_bsn_source_v2_clk"
+ internal="reg_bsn_source_v2.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_read"
- internal="reg_bsn_scheduler_xsub.read"
+ name="reg_bsn_source_v2_read"
+ internal="reg_bsn_source_v2.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_readdata"
- internal="reg_bsn_scheduler_xsub.readdata"
+ name="reg_bsn_source_v2_readdata"
+ internal="reg_bsn_source_v2.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_reset"
- internal="reg_bsn_scheduler_xsub.reset"
+ name="reg_bsn_source_v2_reset"
+ internal="reg_bsn_source_v2.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_write"
- internal="reg_bsn_scheduler_xsub.write"
+ name="reg_bsn_source_v2_write"
+ internal="reg_bsn_source_v2.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_writedata"
- internal="reg_bsn_scheduler_xsub.writedata"
+ name="reg_bsn_source_v2_writedata"
+ internal="reg_bsn_source_v2.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_address"
- internal="reg_bsn_source_v2.address"
+ name="reg_bsn_sync_scheduler_xsub_address"
+ internal="reg_bsn_sync_scheduler_xsub.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_clk"
- internal="reg_bsn_source_v2.clk"
+ name="reg_bsn_sync_scheduler_xsub_clk"
+ internal="reg_bsn_sync_scheduler_xsub.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_read"
- internal="reg_bsn_source_v2.read"
+ name="reg_bsn_sync_scheduler_xsub_read"
+ internal="reg_bsn_sync_scheduler_xsub.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_readdata"
- internal="reg_bsn_source_v2.readdata"
+ name="reg_bsn_sync_scheduler_xsub_readdata"
+ internal="reg_bsn_sync_scheduler_xsub.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_reset"
- internal="reg_bsn_source_v2.reset"
+ name="reg_bsn_sync_scheduler_xsub_reset"
+ internal="reg_bsn_sync_scheduler_xsub.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_write"
- internal="reg_bsn_source_v2.write"
+ name="reg_bsn_sync_scheduler_xsub_write"
+ internal="reg_bsn_sync_scheduler_xsub.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_writedata"
- internal="reg_bsn_source_v2.writedata"
+ name="reg_bsn_sync_scheduler_xsub_writedata"
+ internal="reg_bsn_sync_scheduler_xsub.writedata"
type="conduit"
dir="end" />
<interface
@@ -1975,41 +2010,6 @@
internal="reg_dp_shiftram.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_address"
- internal="reg_dp_sync_insert_v2.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_clk"
- internal="reg_dp_sync_insert_v2.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_read"
- internal="reg_dp_sync_insert_v2.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_readdata"
- internal="reg_dp_sync_insert_v2.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_reset"
- internal="reg_dp_sync_insert_v2.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_write"
- internal="reg_dp_sync_insert_v2.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_writedata"
- internal="reg_dp_sync_insert_v2.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_dp_xonoff_address"
internal="reg_dp_xonoff.address"
@@ -5805,7 +5805,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='pio_pps.mem' start='0xB4170' end='0xB4180' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_si.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41E0' end='0xB41E8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xBC000' end='0xBC040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xBC040' end='0xBC080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xBC080' end='0xBC0C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xBC0C0' end='0xBC100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xBC100' end='0xBC120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xBC120' end='0xBC140' datawidth='32' /><slave name='reg_epcs.mem' start='0xBC140' end='0xBC160' datawidth='32' /><slave name='reg_remu.mem' start='0xBC160' end='0xBC180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xBC180' end='0xBC190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xBC190' end='0xBC1A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xBC1A0' end='0xBC1B0' datawidth='32' /><slave name='pio_pps.mem' start='0xBC1B0' end='0xBC1C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xBC1C0' end='0xBC1C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xBC1C8' end='0xBC1D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xBC1D0' end='0xBC1D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xBC1D8' end='0xBC1E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xBC1E0' end='0xBC1E8' datawidth='32' /><slave name='reg_si.mem' start='0xBC1E8' end='0xBC1F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xBC1F0' end='0xBC1F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC1F8' end='0xBC200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC200' end='0xBC208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC208' end='0xBC210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC210' end='0xBC218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -14604,7 +14604,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="ram_st_histogram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14620,7 +14620,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14684,7 +14684,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14753,7 +14753,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15159,11 +15159,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15190,37 +15190,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_xsq"
+ name="ram_st_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15806,37 +15806,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="ram_st_xsq"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16422,37 +16422,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16468,7 +16468,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16532,7 +16532,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16601,7 +16601,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17007,11 +17007,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17038,37 +17038,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17084,7 +17084,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17148,7 +17148,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17217,7 +17217,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17623,11 +17623,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17654,37 +17654,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17700,7 +17700,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17764,7 +17764,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17833,7 +17833,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18239,11 +18239,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18270,37 +18270,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18316,7 +18316,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18380,7 +18380,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18449,7 +18449,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18855,11 +18855,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18886,37 +18886,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler_xsub"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19502,30 +19502,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -20148,7 +20148,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_bsn_sync_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20734,37 +20734,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20780,7 +20780,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20844,7 +20844,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20913,7 +20913,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21319,11 +21319,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21350,37 +21350,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21396,7 +21396,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21460,7 +21460,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21529,7 +21529,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21935,11 +21935,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21966,37 +21966,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22012,7 +22012,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22076,7 +22076,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22145,7 +22145,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22551,11 +22551,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22582,37 +22582,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_sync_insert_v2"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22628,7 +22628,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22692,7 +22692,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22761,7 +22761,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23167,11 +23167,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23198,30 +23198,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -39356,7 +39356,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000b41e0" />
+ <parameter name="baseAddress" value="0x000bc210" />
</connection>
<connection
kind="avalon"
@@ -39391,7 +39391,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000b4170" />
+ <parameter name="baseAddress" value="0x000bc1b0" />
</connection>
<connection
kind="avalon"
@@ -39405,49 +39405,49 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x000b4120" />
+ <parameter name="baseAddress" value="0x000bc160" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x000b4100" />
+ <parameter name="baseAddress" value="0x000bc140" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000b41d8" />
+ <parameter name="baseAddress" value="0x000bc208" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000b41d0" />
+ <parameter name="baseAddress" value="0x000bc200" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000b41c8" />
+ <parameter name="baseAddress" value="0x000bc1f8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000b41c0" />
+ <parameter name="baseAddress" value="0x000bc1f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x000b40e0" />
+ <parameter name="baseAddress" value="0x000bc120" />
</connection>
<connection
kind="avalon"
@@ -39461,7 +39461,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x000b4080" />
+ <parameter name="baseAddress" value="0x000bc0c0" />
</connection>
<connection
kind="avalon"
@@ -39475,7 +39475,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000b41b8" />
+ <parameter name="baseAddress" value="0x000bc1e8" />
</connection>
<connection
kind="avalon"
@@ -39517,14 +39517,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000b41b0" />
+ <parameter name="baseAddress" value="0x000bc1e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x000b40c0" />
+ <parameter name="baseAddress" value="0x000bc100" />
</connection>
<connection
kind="avalon"
@@ -39545,21 +39545,21 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x000b0000" />
+ <parameter name="baseAddress" value="0x000b8000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000b41a8" />
+ <parameter name="baseAddress" value="0x000bc1d8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x000b0000" />
</connection>
<connection
kind="avalon"
@@ -39580,7 +39580,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x000b4160" />
+ <parameter name="baseAddress" value="0x000bc1a0" />
</connection>
<connection
kind="avalon"
@@ -39594,7 +39594,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x000b4150" />
+ <parameter name="baseAddress" value="0x000bc190" />
</connection>
<connection
kind="avalon"
@@ -39608,21 +39608,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x000b4040" />
+ <parameter name="baseAddress" value="0x000bc080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000b41a0" />
+ <parameter name="baseAddress" value="0x000bc1d0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00018000" />
</connection>
<connection
kind="avalon"
@@ -39643,14 +39643,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000b4198" />
+ <parameter name="baseAddress" value="0x000bc1c8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000b4190" />
+ <parameter name="baseAddress" value="0x000bc1c0" />
</connection>
<connection
kind="avalon"
@@ -39664,7 +39664,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x000b4140" />
+ <parameter name="baseAddress" value="0x000bc180" />
</connection>
<connection
kind="avalon"
@@ -39677,43 +39677,43 @@
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_dp_sync_insert_v2.mem">
- <parameter name="baseAddress" value="0x000b4188" />
+ end="reg_crosslets_info.mem">
+ <parameter name="baseAddress" value="0x000bc040" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x000b4000" />
+ end="ram_st_xsq.mem">
+ <parameter name="baseAddress" value="0x00060000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_bsn_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x000b4180" />
+ end="reg_stat_enable_xst.mem">
+ <parameter name="baseAddress" value="0x3008" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="ram_st_xsq.mem">
- <parameter name="baseAddress" value="0x00060000" />
+ end="reg_stat_hdr_dat_xst.mem">
+ <parameter name="baseAddress" value="0x0100" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_enable_xst.mem">
- <parameter name="baseAddress" value="0x3008" />
+ end="reg_bsn_sync_scheduler_xsub.mem">
+ <parameter name="baseAddress" value="0x000bc000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_hdr_dat_xst.mem">
- <parameter name="baseAddress" value="0x0100" />
+ end="ram_st_histogram.mem">
+ <parameter name="baseAddress" value="0x8000" />
</connection>
<connection
kind="avalon"
@@ -39961,28 +39961,28 @@
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_dp_sync_insert_v2.system" />
+ end="reg_crosslets_info.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_st_xsq.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_crosslets_info.system" />
+ end="reg_stat_enable_xst.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_bsn_scheduler_xsub.system" />
- <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_st_xsq.system" />
+ end="reg_stat_hdr_dat_xst.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_enable_xst.system" />
+ end="reg_bsn_sync_scheduler_xsub.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_hdr_dat_xst.system" />
+ end="ram_st_histogram.system" />
<connection
kind="interrupt"
version="18.0"
@@ -40248,32 +40248,32 @@
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_dp_sync_insert_v2.system_reset" />
+ end="reg_crosslets_info.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_crosslets_info.system_reset" />
+ end="ram_st_xsq.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_bsn_scheduler_xsub.system_reset" />
+ end="reg_stat_enable_xst.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="ram_st_xsq.system_reset" />
+ end="reg_stat_hdr_dat_xst.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_enable_xst.system_reset" />
+ end="reg_bsn_sync_scheduler_xsub.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_hdr_dat_xst.system_reset" />
+ end="ram_st_histogram.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 405d49e9badd42bf2729bb8c3dc0dbd827c7ff9e..f36f2cc65cfeefa831d61658599d2ee41550219f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -59,6 +59,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
@@ -66,7 +67,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -74,7 +75,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 30a3e73e3ff354cc93a870658dbc35883a503d5d..3390c4ce2e915beb415c474bb2cc26791980e18a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -67,6 +67,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
@@ -74,7 +75,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -82,7 +83,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index 95e95a5df0cdd580a9596813c5dc43147b572de1..c26430cca8f28cf5da9c0c199670dd48382c21b6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -66,6 +66,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
@@ -73,7 +74,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -81,7 +82,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index ef1bd83f987c514f911651c6752052c0fb215fe6..11ba0e50633755c40968d46b363c344c6cb45749 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -89,7 +89,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
-- WG
CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/1; -- in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
index 55e0af625cc4394681a6002faa68592fc2d60209..bdcb9fdfac3e39477e4dc1480e96126282c6fa21 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -63,6 +63,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
@@ -70,7 +71,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -78,7 +79,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index c15743f6c693c88222d3f2db2d8659e9ab9c2653..48c90eb869b2e85ff23b2fe086665e44666cd49b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -66,6 +66,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
@@ -73,7 +74,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -81,7 +82,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index a8e0635b63a96c82458a3f1efcd46c679643a3af..e38b78de43927f210ac0adc716159bb7b180f974 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -81,7 +81,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
-
+ CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync;
+
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
@@ -106,13 +107,13 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
-- MM
- CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
- CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
- CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
- CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
- CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
- CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
- CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+ CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
+ CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
+ CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
@@ -285,8 +286,10 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-- bsn_scheduler_xsub
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
-- Wait for enough WG data and start of sync interval
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index a3a44d2dc0893d3abfd2d7b6f3c4b426ca1fb190..fc24b687fddfaee847726ec8b8e5690f254aa374 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -74,11 +74,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+ CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync;
-- MM
- CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
- CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
- CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
+ CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
@@ -218,9 +219,10 @@ BEGIN
----------------------------------------------------------------------------
-- Enable xsub
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, 1, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
----------------------------------------------------------------------------
-- Offload enable
----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 36bda1b4a0f7ccb59831c8fee5b23f0573f6d8d4..2f8f0c9f3fc0490a3af9074fe6dd40600443bc4f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -238,6 +238,10 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
+ -- ST Histogram
+ SIGNAL ram_st_histogram_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_histogram_miso : t_mem_miso := c_mem_miso_rst;
+
-- Aduh statistics monitor
SIGNAL reg_aduh_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
@@ -274,17 +278,13 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
----------------------------------------------
-- XSUB
----------------------------------------------
- -- dp_sync_insert_v2
- SIGNAL reg_dp_sync_insert_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_sync_insert_v2_miso : t_mem_miso := c_mem_miso_rst;
-
-- crosslets_info
SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
- SIGNAL reg_bsn_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
-- st_xsq
SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -596,6 +596,8 @@ BEGIN
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_st_histogram_mosi => ram_st_histogram_mosi,
+ ram_st_histogram_miso => ram_st_histogram_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
ram_st_sst_mosi => ram_st_sst_mosi,
@@ -640,12 +642,10 @@ BEGIN
reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso
);
@@ -719,6 +719,8 @@ BEGIN
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_st_histogram_mosi => ram_st_histogram_mosi,
+ ram_st_histogram_miso => ram_st_histogram_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
@@ -739,12 +741,10 @@ BEGIN
reg_sdp_info_miso => reg_sdp_info_miso,
-- XSUB
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index e0ec6e62de04ecc0ccf238b673762acbd6f07454..a5002af9f73741ef85cdc67d2e19b1da323838f4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -130,6 +130,10 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
reg_diag_data_buf_bsn_miso : IN t_mem_miso;
+ -- ST Histogram
+ ram_st_histogram_mosi : OUT t_mem_mosi;
+ ram_st_histogram_miso : IN t_mem_miso;
+
-- Aduh
reg_aduh_monitor_mosi : OUT t_mem_mosi;
reg_aduh_monitor_miso : IN t_mem_miso;
@@ -206,17 +210,13 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
- -- dp_sync_insert_v2
- reg_dp_sync_insert_v2_mosi : OUT t_mem_mosi;
- reg_dp_sync_insert_v2_miso : IN t_mem_miso;
-
-- crosslets_info
reg_crosslets_info_mosi : OUT t_mem_mosi;
reg_crosslets_info_miso : IN t_mem_miso;
- -- bsn_scheduler_xsub
- reg_bsn_scheduler_xsub_mosi : OUT t_mem_mosi;
- reg_bsn_scheduler_xsub_miso : IN t_mem_miso;
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
+ reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
-- st_xsq (XST)
ram_st_xsq_mosi : OUT t_mem_mosi;
@@ -308,6 +308,9 @@ BEGIN
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ u_mm_file_ram_st_histogram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
+ PORT MAP(mm_rst, mm_clk, ram_st_histogram_mosi, ram_st_histogram_miso );
+
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
@@ -365,14 +368,11 @@ BEGIN
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
- u_mm_file_reg_dp_sync_insert_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SYNC_INSERT_V2")
- PORT MAP(mm_rst, mm_clk, reg_dp_sync_insert_v2_mosi, reg_dp_sync_insert_v2_miso);
-
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
- u_mm_file_reg_bsn_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_xsub_mosi, reg_bsn_scheduler_xsub_miso);
+ u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
@@ -606,7 +606,6 @@ BEGIN
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
@@ -623,6 +622,14 @@ BEGIN
reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_clk_export => OPEN,
+ ram_st_histogram_reset_export => OPEN,
+ ram_st_histogram_address_export => ram_st_histogram_mosi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
+ ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_aduh_monitor_reset_export => OPEN,
reg_aduh_monitor_clk_export => OPEN,
reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
@@ -775,14 +782,6 @@ BEGIN
reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_clk_export => OPEN,
- reg_dp_sync_insert_v2_reset_export => OPEN,
- reg_dp_sync_insert_v2_address_export => reg_dp_sync_insert_v2_mosi.address(c_sdp_reg_dp_sync_insert_v2_addr_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_write_export => reg_dp_sync_insert_v2_mosi.wr,
- reg_dp_sync_insert_v2_writedata_export => reg_dp_sync_insert_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_read_export => reg_dp_sync_insert_v2_mosi.rd,
- reg_dp_sync_insert_v2_readdata_export => reg_dp_sync_insert_v2_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
@@ -791,13 +790,13 @@ BEGIN
reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_clk_export => OPEN,
- reg_bsn_scheduler_xsub_reset_export => OPEN,
- reg_bsn_scheduler_xsub_address_export => reg_bsn_scheduler_xsub_mosi.address(c_sdp_reg_bsn_scheduler_xsub_addr_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_write_export => reg_bsn_scheduler_xsub_mosi.wr,
- reg_bsn_scheduler_xsub_writedata_export => reg_bsn_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_read_export => reg_bsn_scheduler_xsub_mosi.rd,
- reg_bsn_scheduler_xsub_readdata_export => reg_bsn_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 181b0649ce2ec4ba52ea38891fdbb873192a6a20..43cfd5dfa11f988ffadde1d9878cb641e9b44a55 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -91,6 +91,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
ram_equalizer_gains_clk_export : out std_logic; -- export
ram_equalizer_gains_read_export : out std_logic; -- export
@@ -329,13 +336,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_sync_insert_v2_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_sync_insert_v2_clk_export : out std_logic; -- export
- reg_dp_sync_insert_v2_read_export : out std_logic; -- export
- reg_dp_sync_insert_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_sync_insert_v2_reset_export : out std_logic; -- export
- reg_dp_sync_insert_v2_write_export : out std_logic; -- export
- reg_dp_sync_insert_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
reg_crosslets_info_clk_export : out std_logic; -- export
reg_crosslets_info_read_export : out std_logic; -- export
@@ -343,13 +343,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_crosslets_info_reset_export : out std_logic; -- export
reg_crosslets_info_write_export : out std_logic; -- export
reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_xsub_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_st_xsq_address_export : out std_logic_vector(13 downto 0); -- export
ram_st_xsq_clk_export : out std_logic; -- export
ram_st_xsq_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index a4db59cf5630f2f88b8e75935bffdf75d9109243..87ad9f4aa4f1d2d7fa917a208257c13f546f0779 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -26,7 +26,7 @@
-- Contains all the signal processing blocks to receive and time the ADC input data
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
-LIBRARY IEEE, common_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -85,6 +85,10 @@ ENTITY node_sdp_adc_input_and_timing IS
reg_diag_data_buf_bsn_mosi : IN t_mem_mosi;
reg_diag_data_buf_bsn_miso : OUT t_mem_miso;
+ -- ST Histogram
+ ram_st_histogram_mosi : IN t_mem_mosi;
+ ram_st_histogram_miso : OUT t_mem_miso;
+
-- Aduh (statistics) monitor
reg_aduh_monitor_mosi : IN t_mem_mosi;
reg_aduh_monitor_miso : OUT t_mem_miso;
@@ -442,6 +446,32 @@ BEGIN
in_sync => st_sosi_arr(0).sync
);
+ -----------------------------------------------------------------------------
+ -- ST Histogram
+ -----------------------------------------------------------------------------
+
+ u_st_histogram : ENTITY st_lib.mmp_st_histogram
+ GENERIC MAP (
+ g_nof_instances => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_nof_bins => c_sdp_V_si_histogram,
+ g_nof_data_per_sync => 10**6 * c_sdp_f_adc_MHz
+ )
+ PORT MAP (
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_copi => ram_st_histogram_mosi,
+ ram_cipo => ram_st_histogram_miso,
+
+ snk_in_arr => st_sosi_arr
+ );
+
+
+
+
-----------------------------------------------------------------------------
-- Output Stage
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 191577e824056e530783ed46a88fcb65a9133d2b..4e578e7da26853edc548e0ea26fa1247d5e1d7dc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -54,18 +54,16 @@ ENTITY node_sdp_correlator IS
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
- reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_sync_insert_v2_miso : OUT t_mem_miso;
- reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso;
- reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso;
- reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_enable_miso : OUT t_mem_miso;
- reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_hdr_dat_miso : OUT t_mem_miso;
+ reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso;
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso;
+ reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_miso : OUT t_mem_miso;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -77,9 +75,6 @@ END node_sdp_correlator;
ARCHITECTURE str OF node_sdp_correlator IS
- CONSTANT c_nof_blk_per_sync_max : NATURAL := c_sdp_xst_nof_blk_per_sync_max;
- CONSTANT c_nof_blk_per_sync_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min;
-
CONSTANT c_nof_masters : POSITIVE := 2;
-- crosslet statistics offload
@@ -91,14 +86,14 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
- SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_bsn_sync_scheduler_src_out : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
- SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
+ SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
-- Requantize 18b to 16b
@@ -125,28 +120,6 @@ BEGIN
);
END GENERATE;
- ---------------------------------------------------------------
- -- dp_sync_insert_v2
- ---------------------------------------------------------------
- u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
- GENERIC MAP (
- g_nof_streams => c_sdp_P_pfb,
- g_nof_blk_per_sync => c_nof_blk_per_sync_max,
- g_nof_blk_per_sync_min => c_nof_blk_per_sync_min
- )
- PORT MAP (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_sync_insert_v2_mosi,
- reg_miso => reg_dp_sync_insert_v2_miso,
-
- in_sosi_arr => quant_sosi_arr,
- out_sosi_arr => xin_sosi_arr
- );
-
---------------------------------------------------------------
-- Crosslet Subband Select
---------------------------------------------------------------
@@ -158,7 +131,7 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- in_sosi_arr => xin_sosi_arr,
+ in_sosi_arr => quant_sosi_arr,
out_sosi => xsel_sosi,
mm_rst => mm_rst,
@@ -166,10 +139,10 @@ BEGIN
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
-
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
+
out_crosslets_info => crosslets_info
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 826d47e29b25e8ac3b2f7f6e336999536647d7de..0af185f5fbff6ab24243bfb6a028d45f6ad296ed 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -41,7 +41,8 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_crosslets_subband_select IS
GENERIC (
- g_N_crosslets : NATURAL := c_sdp_N_crosslets
+ g_N_crosslets : NATURAL := c_sdp_N_crosslets;
+ g_ctrl_interval_size_min : NATURAL := c_sdp_xst_nof_clk_per_sync_min
);
PORT (
dp_clk : IN STD_LOGIC;
@@ -56,8 +57,8 @@ ENTITY sdp_crosslets_subband_select IS
reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
- reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
@@ -96,6 +97,7 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
SIGNAL col_select_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL row_select_slv : STD_LOGIC_VECTOR(c_row_select_slv_w-1 DOWNTO 0);
+ SIGNAL dp_bsn_sync_scheduler_src_out_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL col_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL row_sosi : t_dp_sosi;
@@ -104,27 +106,27 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
BEGIN
---------------------------------------------------------------
- -- BSN scheduler
+ -- BSN sync scheduler
---------------------------------------------------------------
- u_bsn_scheduler : ENTITY dp_lib.mms_dp_bsn_scheduler
+ u_mmp_dp_bsn_sync_scheduler_arr : ENTITY dp_lib.mmp_dp_bsn_sync_scheduler_arr
GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_bsn_w => c_dp_stream_bsn_w
+ g_nof_streams => c_sdp_P_pfb,
+ g_block_size => c_sdp_N_fft,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
)
PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_miso => reg_bsn_scheduler_xsub_miso,
+ reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_miso => reg_bsn_sync_scheduler_xsub_miso,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
- snk_in => in_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => start_trigger
+ out_start => start_trigger
);
---------------------------------------------------------------
@@ -161,7 +163,7 @@ BEGIN
END IF;
END PROCESS;
- p_comb_crosslets_control : PROCESS(r, start_trigger, crosslets_info_reg, in_sosi_arr, col_select_miso)
+ p_comb_crosslets_control : PROCESS(r, start_trigger, crosslets_info_reg, dp_bsn_sync_scheduler_src_out_arr, col_select_miso)
VARIABLE v : t_crosslets_control_reg;
-- Use extra variable to simplify col_select_mosi address selection.
-- Also using v_offsets instead of v.offsets to clearly indicate we do not only use this variable on the left side but also on the right side of assignments.
@@ -178,7 +180,8 @@ BEGIN
v.row_index := 0;
v.col_index := 0;
v.sync_detected := '0'; -- set sync_detected to 0 in the case that a sync has been detected before the initial start_trigger.
- -- start_trigger is active on the eop so we can immediatly reset the offsets/step such that they are used in the next packet.
+
+ -- start_trigger is active on the sync so we can immediatly reset the offsets/step such that they are used in the next packet.
-- It is up to the user to schedule the start trigger on a BSN that coincides with a sync interval if that is desired.
v.step := TO_UINT(crosslets_info_reg(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w));
FOR I IN 0 TO g_N_crosslets-1 LOOP
@@ -186,21 +189,18 @@ BEGIN
END LOOP;
END IF;
- IF in_sosi_arr(0).sync = '1' THEN
+ -- Do not set sync_detected if start_trigger = 1 because the first sync interval after (re)start
+ -- already has set the indices for the first interval and we do not want to increase them with the step.
+ IF dp_bsn_sync_scheduler_src_out_arr(0).sync = '1' AND start_trigger = '0' THEN
v.sync_detected := '1';
END IF;
IF r.started = '1' THEN -- Once started r.started remains active.
-- add step to offsets
- IF in_sosi_arr(0).eop = '1' AND r.sync_detected = '1' THEN -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select
+ IF dp_bsn_sync_scheduler_src_out_arr(0).eop = '1' AND r.sync_detected = '1' THEN -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select
v.sync_detected := '0';
FOR I IN 0 TO g_N_crosslets-1 LOOP
- IF start_trigger = '1' THEN
- -- Using the crosslets_info_reg directly instead of r.step when start trigger coincides with the current eop as step can have a new value.
- v_offsets(I) := r.offsets(I) + TO_UINT(crosslets_info_reg(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w));
- ELSE
- v_offsets(I) := r.offsets(I) + r.step;
- END IF;
+ v_offsets(I) := r.offsets(I) + r.step;
END LOOP;
END IF;
@@ -265,7 +265,7 @@ BEGIN
col_select_miso => col_select_miso,
-- Streaming
- input_sosi_arr => in_sosi_arr,
+ input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
output_sosi_arr => col_sosi_arr
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 1fd2d2c1e333e3104de5eef5c38b77fe25b05fc5..dfdb732de1ba6f91a47525f6e54f6097e10648aa 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -84,6 +84,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_V_sample_delay : NATURAL := 4096;
CONSTANT c_sdp_V_si_db : NATURAL := 1024;
CONSTANT c_sdp_V_si_db_large : NATURAL := 131072;
+ CONSTANT c_sdp_V_si_histogram : NATURAL := 512;
CONSTANT c_sdp_W_adc : NATURAL := 14;
CONSTANT c_sdp_W_adc_jesd : NATURAL := 16;
CONSTANT c_sdp_W_beamlet : NATURAL := 8;
@@ -287,17 +288,18 @@ PACKAGE sdp_pkg is
-- AIT MM address widths
- CONSTANT c_sdp_jesd204b_addr_w : NATURAL := 8 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_jesd204b_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 8;
CONSTANT c_sdp_jesd_ctrl_addr_w : NATURAL := 1;
CONSTANT c_sdp_reg_bsn_monitor_input_addr_w : NATURAL := 8;
- CONSTANT c_sdp_reg_wg_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_ram_wg_addr_w : NATURAL := 10 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_reg_dp_shiftram_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_reg_wg_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 2;
+ CONSTANT c_sdp_ram_wg_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 10;
+ CONSTANT c_sdp_reg_dp_shiftram_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 1;
CONSTANT c_sdp_reg_bsn_source_v2_addr_w : NATURAL := 3;
CONSTANT c_sdp_reg_bsn_scheduler_addr_w : NATURAL := 1;
- CONSTANT c_sdp_ram_diag_data_buf_bsn_addr_w : NATURAL := ceil_log2(c_sdp_S_pn*c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
- CONSTANT c_sdp_reg_diag_data_buf_bsn_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_reg_aduh_monitor_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_ram_diag_data_buf_bsn_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
+ CONSTANT c_sdp_reg_diag_data_buf_bsn_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 1;
+ CONSTANT c_sdp_ram_st_histogram_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_histogram);
+ CONSTANT c_sdp_reg_aduh_monitor_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 2;
-- FSUB MM address widths
CONSTANT c_sdp_ram_fil_coefs_addr_w : NATURAL := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
@@ -325,14 +327,12 @@ PACKAGE sdp_pkg is
init_sl => '0');
CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w;
- CONSTANT c_sdp_xst_nof_blk_per_sync_max : NATURAL := 200000;
- CONSTANT c_sdp_xst_nof_blk_per_sync_min : NATURAL := 19530;
+ CONSTANT c_sdp_xst_nof_clk_per_sync_min : NATURAL := (c_sdp_f_adc_MHz *10**6) / 10; -- 0.1 second
-- XSUB MM address widths
- CONSTANT c_sdp_reg_dp_sync_insert_v2_addr_w : NATURAL := 1;
- CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
- CONSTANT c_sdp_reg_bsn_scheduler_xsub_addr_w : NATURAL := 1;
- CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
+ CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
+ CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
END PACKAGE sdp_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 15b936c1d5495941c4748df81b6ab6e6d649c810..26714361d8e8392a1f5244f777916a0ee2e5704e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -134,6 +134,10 @@ ENTITY sdp_station IS
reg_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
+ -- ST Histogram
+ ram_st_histogram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_histogram_miso : OUT t_mem_miso := c_mem_miso_rst;
+
-- Aduh statistics monitor
reg_aduh_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_aduh_monitor_miso : OUT t_mem_miso := c_mem_miso_rst;
@@ -170,21 +174,17 @@ ENTITY sdp_station IS
----------------------------------------------
-- XSUB
----------------------------------------------
- -- dp_sync_insert_v2
- reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_sync_insert_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
-
-- crosslets_info
- reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
- reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
-- st_xsq
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
----------------------------------------------
-- BF
@@ -432,6 +432,8 @@ BEGIN
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_st_histogram_mosi => ram_st_histogram_mosi,
+ ram_st_histogram_miso => ram_st_histogram_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
@@ -506,36 +508,34 @@ BEGIN
g_P_sq => g_P_sq
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
-
- xst_udp_sosi => udp_tx_sosi_arr(1),
- xst_udp_siso => udp_tx_siso_arr(1),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
-
- reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
- sdp_info => sdp_info,
- gn_id => gn_id,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => xst_udp_src_port
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
);
END GENERATE;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 7e465cae371242282dfd24f3f5ad544062e55dd1..e190d901f21e8bb499875a41aeb1e2399061735d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -134,7 +134,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS
nof_cycles_dly : NATURAL;
payload_err : STD_LOGIC;
interval_cnt : NATURAL;
- integration_interval : NATURAL;
+ integration_interval : NATURAL;
END RECORD;
CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0, 0);
@@ -207,7 +207,7 @@ BEGIN
-- Count number of sop's in a sync interval and get payload errors and keep them till next sync.
IF in_sosi.sync = '1' THEN
- v.integration_interval := r.interval_cnt;
+ v.integration_interval := r.interval_cnt + 1; -- count = index + 1
v.interval_cnt := 0;
v.payload_err := '0';
ELSE
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 127f1499fa098add9f4dadca0f90ce6c0071c054..7c77ebee3ecb18b9bede4a495e1fa4540781b9e6 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -65,7 +65,9 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
CONSTANT c_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval
CONSTANT c_nof_ch_sel : NATURAL := c_N_crosslets*c_nof_ch_sel_col*c_nof_ch_sel_row;
- CONSTANT scheduled_bsn : NATURAL := 11;
+ CONSTANT c_ctrl_interval_size : NATURAL := c_nof_block_per_sync * c_nof_ch_in;
+ CONSTANT c_scheduled_bsn : NATURAL := 11;
+ CONSTANT c_nof_block_dly : NATURAL := c_nof_block_per_sync;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
@@ -83,7 +85,7 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL exp_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL bsn : NATURAL := scheduled_bsn-1;
+ SIGNAL bsn : NATURAL := c_scheduled_bsn - c_nof_block_dly;
SIGNAL in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
@@ -105,8 +107,11 @@ BEGIN
proc_common_wait_until_low(mm_clk, rst);
proc_common_wait_some_cycles(mm_clk, 50); -- Give dut some time to start
-- BSN Scheduler
- proc_mem_mm_bus_wr(0, scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
- proc_mem_mm_bus_wr(1, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(1, c_ctrl_interval_size, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(2, c_scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(3, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(0, 1, mm_clk, mm_trigger_miso, mm_trigger_mosi); --enable
+
-- crosslet info
FOR I IN 0 TO c_N_crosslets-1 LOOP
@@ -198,8 +203,8 @@ BEGIN
exp_sosi.eop <= '1';
END IF;
- exp_sosi.re <= TO_DP_DSP_DATA( I * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
- exp_sosi.im <= TO_DP_DSP_DATA(1+ I * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ exp_sosi.re <= TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ exp_sosi.im <= TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
proc_common_wait_some_cycles(clk, 1);
END LOOP;
@@ -225,7 +230,8 @@ BEGIN
u_dut : ENTITY work.sdp_crosslets_subband_select
GENERIC MAP (
- g_N_crosslets => c_N_crosslets
+ g_N_crosslets => c_N_crosslets,
+ g_ctrl_interval_size_min => 1
)
PORT MAP (
dp_rst => rst,
@@ -237,8 +243,8 @@ BEGIN
reg_crosslets_info_mosi => mm_mosi,
reg_crosslets_info_miso => mm_miso,
- reg_bsn_scheduler_xsub_mosi => mm_trigger_mosi,
- reg_bsn_scheduler_xsub_miso => mm_trigger_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
-- Streaming
in_sosi_arr => in_sosi_arr,
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index db5a0922e739a0ff5d873df54fe946cb85492438..dff32a18f324eb118a03045fbe521734ffbacdbf 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -48,10 +48,10 @@ USE work.sdp_pkg.ALL;
ENTITY tb_sdp_statistics_offload IS
GENERIC (
- g_statistics_type : STRING := "SST";
+ g_statistics_type : STRING := "XST";
g_offload_time : NATURAL := 500;
g_beamset_id : NATURAL := 0;
- g_P_sq : NATURAL := c_sdp_P_sq
+ g_P_sq : NATURAL := 1 --c_sdp_P_sq
);
END tb_sdp_statistics_offload;
@@ -326,12 +326,15 @@ BEGIN
REPORT "wrong sdp_block_period" SEVERITY ERROR;
-- Check variable header info.
+ ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_integration_interval") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_integration_interval")) = TO_UVEC(c_nof_block_per_sync, 24)
+ REPORT "wrong sdp_integration_interval" SEVERITY ERROR;
+
IF g_statistics_type = "SST" THEN
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(rx_block_cnt + c_sdp_S_pn * gn_index, 32)
- REPORT "wront SST sdp_data_id" SEVERITY ERROR;
+ REPORT "wrong SST sdp_data_id" SEVERITY ERROR;
ELSIF g_statistics_type = "BST" THEN
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(c_beamlet_id, 32)
- REPORT "wront BST sdp_data_id" SEVERITY ERROR;
+ REPORT "wrong BST sdp_data_id" SEVERITY ERROR;
--ELSIF g_statistics_type = "XST" THEN --TODO: RW define check
END IF;
END IF;
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index 444e5c915cda27579b56c56520f7378cec7c3069..27fcd79466c332fc6ece560e5c5cc34b616407ca 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -18,6 +18,34 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra, D. vd Schuur
+-- Purpose: Simple memory access (for MM control interface)
+-- Description:
+--
+-- Assume the MM bus is for a 32 bit processor, therefore on the processor
+-- side of a memory peripheral typcially use c_word_w = 32 for the address
+-- and data fields in the MM bus records. However the MM bus can also be used
+-- on the user side of a memory peripheral and there the data width should
+-- not be limited by the processor type but rather by the maximum user data
+-- width on the streaming interface.
+--
+-- The std_logic_vector widths in the record need to be defined, because in
+-- a record they can not be unconstrained. A signal that needs less address
+-- or data width simply leaves the unused MSbits at 'X'. The actually used
+-- width of a memory gets set via a generic record type t_c_mem.
+--
+-- The alternative is to not put the std_logic_vector elements in the record,
+-- and declare them seperately, however then the compact representation that
+-- records provide gets lost, because the record then only contains wr_en and
+-- rd_en. Another alternative is to define the address as a integer and the
+-- data as an integer. However this limits their range to 32 bit numbers,
+-- which can be too few for data.
+
+-- Do not change these widths, because c_word_w just fits in a VHDL INTEGER
+-- Should wider address range or data width be needed, then define a new
+-- record type eg. t_mem_ctlr or t_mem_bus for that with
+-- sufficient widths.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -25,34 +53,6 @@ USE IEEE.NUMERIC_STD.ALL;
USE work.common_pkg.ALL;
PACKAGE common_mem_pkg IS
-
- ------------------------------------------------------------------------------
- -- Simple memory access (for MM control interface)
- ------------------------------------------------------------------------------
-
- -- Assume the MM bus is for a 32 bit processor, therefore on the processor
- -- side of a memory peripheral typcially use c_word_w = 32 for the address
- -- and data fields in the MM bus records. However the MM bus can also be used
- -- on the user side of a memory peripheral and there the data width should
- -- not be limited by the processor type but rather by the maximum user data
- -- width on the streaming interface.
- --
- -- The std_logic_vector widths in the record need to be defined, because in
- -- a record they can not be unconstrained. A signal that needs less address
- -- or data width simply leaves the unused MSbits at 'X'. The actually used
- -- width of a memory gets set via a generic record type t_c_mem.
- --
- -- The alternative is to not put the std_logic_vector elements in the record,
- -- and declare them seperately, however then the compact representation that
- -- records provide gets lost, because the record then only contains wr_en and
- -- rd_en. Another alternative is to define the address as a integer and the
- -- data as an integer. However this limits their range to 32 bit numbers,
- -- which can be too few for data.
-
- -- Do not change these widths, because c_word_w just fits in a VHDL INTEGER
- -- Should wider address range or data width be needed, then define a new
- -- record type eg. t_mem_ctlr or t_mem_bus for that with
- -- sufficient widths.
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
CONSTANT c_mem_address_w : NATURAL := 32; -- address range (suits 32-bit processor)
@@ -80,9 +80,24 @@ PACKAGE common_mem_pkg IS
TYPE t_mem_miso_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_miso;
TYPE t_mem_mosi_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_mosi;
+ -- MOSI/MISO subtypes
+ SUBTYPE t_mem_copi IS t_mem_mosi; -- Controller Out Peripheral In
+ SUBTYPE t_mem_cipo IS t_mem_miso; -- Peripheral In Controller Out
+
+ CONSTANT c_mem_cipo_rst : t_mem_cipo := c_mem_miso_rst;
+ CONSTANT c_mem_copi_rst : t_mem_copi := c_mem_mosi_rst;
+
+ SUBTYPE t_mem_cipo_arr IS t_mem_miso_arr;
+ SUBTYPE t_mem_copi_arr IS t_mem_mosi_arr;
+
-- Reset only the control fields of the MM record
- FUNCTION RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) RETURN t_mem_mosi;
- FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso;
+ FUNCTION RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) RETURN t_mem_mosi; -- deprecated, use RESET_MEM_COPI_CTRL() instead
+ FUNCTION RESET_MEM_COPI_CTRL(copi : t_mem_copi) RETURN t_mem_copi;
+ FUNCTION RESET_MEM_COPI_CTRL(copi_arr : t_mem_copi_arr) RETURN t_mem_copi_arr;
+
+ FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso; -- deprecated, use RESET_MEM_CIPO_CTRL() instead
+ FUNCTION RESET_MEM_CIPO_CTRL(cipo : t_mem_cipo) RETURN t_mem_cipo;
+ FUNCTION RESET_MEM_CIPO_CTRL(cipo_arr : t_mem_cipo_arr) RETURN t_mem_cipo_arr;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
@@ -94,17 +109,6 @@ PACKAGE common_mem_pkg IS
FUNCTION RESIZE_MEM_UDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_SDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- sign extended
FUNCTION RESIZE_MEM_XDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- set unused MSBits to 'X'
-
- -- MOSI/MISO subtypes
- SUBTYPE t_mem_copi IS t_mem_mosi; -- Controller Out Peripheral In
- SUBTYPE t_mem_cipo IS t_mem_miso; -- Peripheral In Controller Out
-
- CONSTANT c_mem_cipo_rst : t_mem_cipo := c_mem_miso_rst;
- CONSTANT c_mem_copi_rst : t_mem_copi := c_mem_mosi_rst;
-
- SUBTYPE t_mem_cipo_arr IS t_mem_miso_arr;
- SUBTYPE t_mem_copi_arr IS t_mem_mosi_arr;
-
------------------------------------------------------------------------------
-- Burst memory access (for DDR access interface)
@@ -191,7 +195,21 @@ PACKAGE BODY common_mem_pkg IS
v_mosi.wr := '0';
RETURN v_mosi;
END RESET_MEM_MOSI_CTRL;
-
+
+ FUNCTION RESET_MEM_COPI_CTRL(copi : t_mem_copi) RETURN t_mem_copi IS
+ BEGIN
+ RETURN RESET_MEM_MOSI_CTRL(copi);
+ END;
+
+ FUNCTION RESET_MEM_COPI_CTRL(copi_arr : t_mem_copi_arr) RETURN t_mem_copi_arr IS
+ VARIABLE v_copi_arr : t_mem_copi_arr(copi_arr'RANGE) := copi_arr;
+ BEGIN
+ FOR I IN copi_arr'RANGE LOOP
+ v_copi_arr(I) := RESET_MEM_COPI_CTRL(copi_arr(I));
+ END LOOP;
+ RETURN v_copi_arr;
+ END;
+
FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso IS
VARIABLE v_miso : t_mem_miso := miso;
BEGIN
@@ -200,6 +218,20 @@ PACKAGE BODY common_mem_pkg IS
RETURN v_miso;
END RESET_MEM_MISO_CTRL;
+ FUNCTION RESET_MEM_CIPO_CTRL(cipo : t_mem_cipo) RETURN t_mem_cipo IS
+ BEGIN
+ RETURN RESET_MEM_MISO_CTRL(cipo);
+ END RESET_MEM_CIPO_CTRL;
+
+ FUNCTION RESET_MEM_CIPO_CTRL(cipo_arr : t_mem_cipo_arr) RETURN t_mem_cipo_arr IS
+ VARIABLE v_cipo_arr : t_mem_cipo_arr(cipo_arr'RANGE) := cipo_arr;
+ BEGIN
+ FOR I IN cipo_arr'RANGE LOOP
+ v_cipo_arr(I) := RESET_MEM_CIPO_CTRL(cipo_arr(I));
+ END LOOP;
+ RETURN v_cipo_arr;
+ END RESET_MEM_CIPO_CTRL;
+
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index b0d8e97ffabb25bf26f6f12596f688048f94ca6f..e5093bd08e56674e7712ca98d0794a8636bfff1c 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -18,13 +18,10 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-
-- Author:
-- . Eric Kooistra
-- Purpose:
-- . Collection of commonly used base funtions
--- Interface:
--- . [n/a]
-- Description:
-- . This is a package containing generic constants and functions.
-- . More information can be found in the comments near the code.
@@ -415,7 +412,10 @@ PACKAGE common_pkg IS
FUNCTION SUB_SVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
FUNCTION ADD_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
FUNCTION SUB_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
+
+ FUNCTION MULT_SVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec * r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH + r_vec'LENGTH
+ FUNCTION MULT_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec * r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH + r_vec'LENGTH
+
FUNCTION COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
FUNCTION COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
@@ -2019,6 +2019,22 @@ PACKAGE BODY common_pkg IS
BEGIN
RETURN SUB_UVEC(l_vec, r_vec, l_vec'LENGTH);
END;
+
+ FUNCTION MULT_SVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ CONSTANT c_product_w : NATURAL := l_vec'LENGTH + r_vec'LENGTH;
+ VARIABLE v_product : STD_LOGIC_VECTOR(c_product_w-1 DOWNTO 0);
+ BEGIN
+ v_product := STD_LOGIC_VECTOR(SIGNED(l_vec) * SIGNED(r_vec));
+ RETURN v_product;
+ END;
+
+ FUNCTION MULT_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ CONSTANT c_product_w : NATURAL := l_vec'LENGTH + r_vec'LENGTH;
+ VARIABLE v_product : STD_LOGIC_VECTOR(c_product_w-1 DOWNTO 0);
+ BEGIN
+ v_product := STD_LOGIC_VECTOR(UNSIGNED(l_vec) * UNSIGNED(r_vec));
+ RETURN v_product;
+ END;
FUNCTION COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER IS
BEGIN
diff --git a/libraries/base/common_mult/hdllib.cfg b/libraries/base/common_mult/hdllib.cfg
index 1f94ac98d096cf3ff0dc7537f500e77628de5037..4062dec5ce556028e20217049f3018482ddedc5d 100644
--- a/libraries/base/common_mult/hdllib.cfg
+++ b/libraries/base/common_mult/hdllib.cfg
@@ -18,10 +18,11 @@ test_bench_files =
tb/vhdl/tb_common_complex_mult.vhd
tb/vhdl/tb_tb_common_mult.vhd
+ tb/vhdl/tb_tb_common_complex_mult.vhd
regression_test_vhdl =
tb/vhdl/tb_common_mult_add2.vhd
- tb/vhdl/tb_common_complex_mult.vhd
+ tb/vhdl/tb_tb_common_complex_mult.vhd
tb/vhdl/tb_tb_common_mult.vhd
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
index 3d505da97f18d4754bcc9f9a4e5a1be91fb944db..6216cc238200fb9299f40479e4cb71aea268e95d 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
@@ -47,8 +47,6 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY common_complex_mult IS
GENERIC (
- g_sim : BOOLEAN := FALSE;
- g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
g_technology : NATURAL := c_tech_select_default;
g_variant : STRING := "IP";
g_in_a_w : POSITIVE;
@@ -111,8 +109,6 @@ BEGIN
u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
GENERIC MAP(
- g_sim => g_sim,
- g_sim_level => g_sim_level,
g_technology => g_technology,
g_variant => g_variant,
g_in_a_w => g_in_a_w,
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index c835646c8781ec6f4e7619c8ce0f173bd06e3ed7..bc21287b0794936d6ff42dc500e099e8bbefa78a 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -23,7 +23,7 @@
-- p_verify verifies that the instances of common_complex_mult all yield the
-- expected results and ASSERTs an ERROR in case they differ.
-- Usage:
--- > as 10
+-- > as 12
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
LIBRARY IEEE, common_lib, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
@@ -32,14 +32,15 @@ USE IEEE.numeric_std.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_common_complex_mult IS
GENERIC (
- g_in_dat_w : NATURAL := 4;
- g_out_dat_w : NATURAL := 8; -- g_in_dat_w*2 for multiply and +1 for adder
- g_conjugate_b : BOOLEAN := FALSE; -- When FALSE p = a * b, else p = a * conj(b)
+ g_variant : STRING := "IP"; -- "RTL" or "IP"
+ g_in_dat_w : NATURAL := 18;
+ g_conjugate_b : BOOLEAN := TRUE; -- When FALSE p = a * b, else p = a * conj(b)
g_pipeline_input : NATURAL := 1;
g_pipeline_product : NATURAL := 0;
g_pipeline_adder : NATURAL := 1;
@@ -53,9 +54,14 @@ ARCHITECTURE tb OF tb_common_complex_mult IS
CONSTANT clk_period : TIME := 10 ns;
CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
+ -- g_in_dat_w*2 for multiply and +1 for adder to fit largest im product value
+ CONSTANT c_out_dat_w : NATURAL := g_in_dat_w * 2 + 1;
+
CONSTANT c_max : INTEGER := 2**(g_in_dat_w-1)-1;
CONSTANT c_min : INTEGER := -2**(g_in_dat_w-1);
+ CONSTANT c_small : INTEGER := smallest(5, c_max);
+
CONSTANT c_technology : NATURAL := c_tech_select_default;
SIGNAL tb_end : STD_LOGIC := '0';
@@ -64,25 +70,32 @@ ARCHITECTURE tb OF tb_common_complex_mult IS
SIGNAL random : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
+ -- Input
SIGNAL in_ar : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_ai : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_br : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_bi : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
- SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val
- SIGNAL result_val_expected : STD_LOGIC;
- SIGNAL result_val_rtl : STD_LOGIC;
- SIGNAL result_val_ip : STD_LOGIC;
-
- SIGNAL out_result_re : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- combinatorial result
- SIGNAL out_result_im : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined results
- SIGNAL result_re_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
+ SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val, not used by multiplier itself
+ -- Results
+ -- . expected valid and DUT valid, only depends on in_val and c_pipeline
+ SIGNAL result_val_expected : STD_LOGIC;
+ SIGNAL result_val_dut : STD_LOGIC;
+
+ -- . product result
+ SIGNAL ref_result_re : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0); -- combinatorial result
+ SIGNAL ref_result_im : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_re_expected : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0); -- pipelined results
+ SIGNAL result_re_dut : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_im_expected : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
+ SIGNAL result_im_dut : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
+
+ -- Debug signals to view constant values in wave window
+ SIGNAL dbg_variant : STRING(g_variant'RANGE) := g_variant;
+ SIGNAL dbg_in_dat_w : NATURAL := g_in_dat_w;
+ SIGNAL dbg_conjugate_b : BOOLEAN := g_conjugate_b;
+ SIGNAL dbg_pipeline : NATURAL := c_pipeline;
BEGIN
@@ -101,34 +114,36 @@ BEGIN
in_ai <= TO_SVEC(0, g_in_dat_w);
in_bi <= TO_SVEC(0, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
- FOR I IN 0 TO 9 LOOP
- WAIT UNTIL rising_edge(clk);
- END LOOP;
+ proc_common_wait_some_cycles(clk, 10);
rst <= '0';
- FOR I IN 0 TO 9 LOOP
- WAIT UNTIL rising_edge(clk);
- END LOOP;
+ proc_common_wait_some_cycles(clk, 10);
- -- Some special combinations
- in_ar <= TO_SVEC(2, g_in_dat_w);
- in_ai <= TO_SVEC(4, g_in_dat_w);
- in_br <= TO_SVEC(3, g_in_dat_w);
- in_bi <= TO_SVEC(5, g_in_dat_w);
- WAIT UNTIL rising_edge(clk);
+ -- Some more special combinations with max and min
in_ar <= TO_SVEC( c_max, g_in_dat_w); -- p*p - p*p + j ( p*p + p*p) = 0 + j 2pp or p*p + p*p + j (-p*p + p*p) = 2pp + j 0
in_ai <= TO_SVEC( c_max, g_in_dat_w);
in_br <= TO_SVEC( c_max, g_in_dat_w);
in_bi <= TO_SVEC( c_max, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
- in_ar <= TO_SVEC( c_min, g_in_dat_w);
- in_ai <= TO_SVEC( c_min, g_in_dat_w);
- in_br <= TO_SVEC( c_min, g_in_dat_w);
- in_bi <= TO_SVEC( c_min, g_in_dat_w);
- WAIT UNTIL rising_edge(clk);
- in_ar <= TO_SVEC( c_max, g_in_dat_w);
- in_ai <= TO_SVEC( c_max, g_in_dat_w);
- in_br <= TO_SVEC( c_min, g_in_dat_w);
- in_bi <= TO_SVEC( c_min, g_in_dat_w);
+
+ -- Skip (c_min + j*c_min) * (c_min + j*c_min), because that just does not fit in 2*g_in_dat_w bits of complex multiplier
+ --in_ar <= TO_SVEC( c_min, g_in_dat_w);
+ --in_ai <= TO_SVEC( c_min, g_in_dat_w);
+ --in_br <= TO_SVEC( c_min, g_in_dat_w);
+ --in_bi <= TO_SVEC( c_min, g_in_dat_w);
+ --WAIT UNTIL rising_edge(clk);
+
+ IF dbg_conjugate_b = FALSE THEN
+ in_ar <= TO_SVEC( c_max, g_in_dat_w);
+ in_ai <= TO_SVEC( c_max, g_in_dat_w);
+ in_br <= TO_SVEC( c_min, g_in_dat_w);
+ in_bi <= TO_SVEC( c_min, g_in_dat_w);
+ ELSE
+ in_ar <= TO_SVEC( c_min, g_in_dat_w);
+ in_ai <= TO_SVEC( c_min, g_in_dat_w);
+ in_br <= TO_SVEC( c_max, g_in_dat_w);
+ in_bi <= TO_SVEC( c_max, g_in_dat_w);
+ END IF;
+
WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_max, g_in_dat_w);
in_ai <= TO_SVEC( c_max, g_in_dat_w);
@@ -140,51 +155,85 @@ BEGIN
in_br <= TO_SVEC(-c_max, g_in_dat_w);
in_bi <= TO_SVEC(-c_max, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
+ in_ar <= TO_SVEC(0, g_in_dat_w);
+ in_br <= TO_SVEC(0, g_in_dat_w);
+ in_ai <= TO_SVEC(0, g_in_dat_w);
+ in_bi <= TO_SVEC(0, g_in_dat_w);
+ WAIT UNTIL rising_edge(clk);
+ proc_common_wait_some_cycles(clk, 10);
- FOR I IN 0 TO 49 LOOP
- WAIT UNTIL rising_edge(clk);
- END LOOP;
+ -- Some special combinations close to max, min
+ in_ar <= TO_SVEC( c_max, g_in_dat_w);
+ in_ai <= TO_SVEC( c_max-1, g_in_dat_w);
+ in_br <= TO_SVEC( c_max-2, g_in_dat_w);
+ in_bi <= TO_SVEC( c_max-3, g_in_dat_w);
+ WAIT UNTIL rising_edge(clk);
+ in_ar <= TO_SVEC( c_min, g_in_dat_w);
+ in_ai <= TO_SVEC( c_min+1, g_in_dat_w);
+ in_br <= TO_SVEC( c_min+2, g_in_dat_w);
+ in_bi <= TO_SVEC( c_min+3, g_in_dat_w);
+ WAIT UNTIL rising_edge(clk);
+ in_ar <= TO_SVEC( c_max, g_in_dat_w);
+ in_ai <= TO_SVEC( c_max-1, g_in_dat_w);
+ in_br <= TO_SVEC( c_min+2, g_in_dat_w);
+ in_bi <= TO_SVEC( c_min+3, g_in_dat_w);
+ WAIT UNTIL rising_edge(clk);
+ in_ar <= TO_SVEC( c_max, g_in_dat_w);
+ in_ai <= TO_SVEC( c_max-1, g_in_dat_w);
+ in_br <= TO_SVEC(-c_max+2, g_in_dat_w);
+ in_bi <= TO_SVEC(-c_max+3, g_in_dat_w);
+ WAIT UNTIL rising_edge(clk);
+ in_ar <= TO_SVEC( c_min, g_in_dat_w);
+ in_ai <= TO_SVEC( c_min+1, g_in_dat_w);
+ in_br <= TO_SVEC(-c_max+2, g_in_dat_w);
+ in_bi <= TO_SVEC(-c_max+3, g_in_dat_w);
+ WAIT UNTIL rising_edge(clk);
+ in_ar <= TO_SVEC(0, g_in_dat_w);
+ in_br <= TO_SVEC(0, g_in_dat_w);
+ in_ai <= TO_SVEC(0, g_in_dat_w);
+ in_bi <= TO_SVEC(0, g_in_dat_w);
+ WAIT UNTIL rising_edge(clk);
+ proc_common_wait_some_cycles(clk, 100);
- -- All combinations
- FOR I IN -c_max TO c_max LOOP
- FOR J IN -c_max TO c_max LOOP
- FOR K IN -c_max TO c_max LOOP
- FOR L IN -c_max TO c_max LOOP
+ -- Try all small combinations
+ FOR I IN -c_small TO c_small LOOP
+ FOR J IN -c_small TO c_small LOOP
+ FOR K IN -c_small TO c_small LOOP
+ FOR L IN -c_small TO c_small LOOP
in_ar <= TO_SVEC(I, g_in_dat_w);
in_ai <= TO_SVEC(K, g_in_dat_w);
in_br <= TO_SVEC(J, g_in_dat_w);
in_bi <= TO_SVEC(L, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
END LOOP;
+ proc_common_wait_some_cycles(clk, 10);
END LOOP;
+ proc_common_wait_some_cycles(clk, 100);
END LOOP;
- END LOOP;
-
- FOR I IN 0 TO 49 LOOP
- WAIT UNTIL rising_edge(clk);
+ proc_common_wait_some_cycles(clk, 1000);
END LOOP;
tb_end <= '1';
WAIT;
END PROCESS;
- -- Expected combinatorial complex multiply out_result
- out_result_re <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "RE", g_out_dat_w);
- out_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", g_out_dat_w);
+ -- Expected combinatorial complex multiply ref_result
+ ref_result_re <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "RE", c_out_dat_w);
+ ref_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", c_out_dat_w);
u_result_re : ENTITY common_lib.common_pipeline
GENERIC MAP (
g_representation => "SIGNED",
g_pipeline => c_pipeline,
g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
)
PORT MAP (
rst => rst,
clk => clk,
clken => '1',
- in_dat => out_result_re,
+ in_dat => ref_result_re,
out_dat => result_re_expected
);
@@ -193,14 +242,14 @@ BEGIN
g_representation => "SIGNED",
g_pipeline => c_pipeline,
g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
)
PORT MAP (
rst => rst,
clk => clk,
clken => '1',
- in_dat => out_result_im,
+ in_dat => ref_result_im,
out_dat => result_im_expected
);
@@ -217,40 +266,13 @@ BEGIN
out_dat => result_val_expected
);
- u_dut_rtl : ENTITY work.common_complex_mult
- GENERIC MAP (
- g_technology => c_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- PORT MAP (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => result_re_rtl,
- out_pi => result_im_rtl,
- out_val => result_val_rtl
- );
-
- u_dut_ip : ENTITY work.common_complex_mult
+ u_dut : ENTITY work.common_complex_mult
GENERIC MAP (
g_technology => c_technology,
- g_variant => "IP",
+ g_variant => g_variant,
g_in_a_w => g_in_dat_w,
g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
+ g_out_p_w => c_out_dat_w,
g_conjugate_b => g_conjugate_b,
g_pipeline_input => g_pipeline_input,
g_pipeline_product => g_pipeline_product,
@@ -266,23 +288,18 @@ BEGIN
in_br => in_br,
in_bi => in_bi,
in_val => in_val,
- out_pr => result_re_ip,
- out_pi => result_im_ip,
- out_val => result_val_ip
+ out_pr => result_re_dut,
+ out_pi => result_im_dut,
+ out_val => result_val_dut
);
p_verify : PROCESS(rst, clk)
BEGIN
IF rst='0' THEN
IF rising_edge(clk) THEN
- ASSERT result_re_rtl = result_re_expected REPORT "Error: RE wrong RTL result" SEVERITY ERROR;
- ASSERT result_im_rtl = result_im_expected REPORT "Error: IM wrong RTL result" SEVERITY ERROR;
- ASSERT result_val_rtl = result_val_expected REPORT "Error: VAL wrong RTL result" SEVERITY ERROR;
-
- ASSERT result_re_ip = result_re_expected REPORT "Error: RE wrong IP result" SEVERITY ERROR;
- ASSERT result_im_ip = result_im_expected REPORT "Error: IM wrong IP result" SEVERITY ERROR;
- ASSERT result_val_ip = result_val_expected REPORT "Error: VAL wrong IP result" SEVERITY ERROR;
-
+ ASSERT result_re_dut = result_re_expected REPORT "Error: RE wrong result, " & slv_to_str(result_re_dut) & " /= " & slv_to_str(result_re_expected) SEVERITY ERROR;
+ ASSERT result_im_dut = result_im_expected REPORT "Error: IM wrong result, " & slv_to_str(result_im_dut) & " /= " & slv_to_str(result_im_expected) SEVERITY ERROR;
+ ASSERT result_val_dut = result_val_expected REPORT "Error: VAL wrong result" SEVERITY ERROR;
END IF;
END IF;
END PROCESS;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..03a8459fc6ff1f9b0cc36f656f026ac8be7c087a
--- /dev/null
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
@@ -0,0 +1,63 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author: E. Kooistra
+-- Purpose: Multi tb for variants of common_complex_mult
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY tb_tb_common_complex_mult IS
+END tb_tb_common_complex_mult;
+
+ARCHITECTURE tb OF tb_tb_common_complex_mult IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+ -- g_variant : STRING := "IP";
+ -- g_in_dat_w : NATURAL := 4;
+ -- g_conjugate_b : BOOLEAN := FALSE; -- When FALSE p = a * b, else p = a * conj(b)
+ -- g_pipeline_input : NATURAL := 1;
+ -- g_pipeline_product : NATURAL := 0;
+ -- g_pipeline_adder : NATURAL := 1;
+ -- g_pipeline_output : NATURAL := 1
+
+
+ -- IP variants
+ u_ip_18b : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18, FALSE, 1, 0, 1, 1);
+ u_ip_18b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18, TRUE, 1, 0, 1, 1);
+
+ gen_27b : IF c_tech_select_default /= c_tech_stratixiv GENERATE
+ u_ip_27b : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, FALSE, 1, 0, 1, 1);
+ u_ip_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, TRUE, 1, 0, 1, 1);
+ END GENERATE;
+
+ -- RTL variants
+ u_rtl_18b : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 18, FALSE, 1, 0, 1, 1);
+ u_rtl_27b : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 27, FALSE, 1, 0, 1, 1);
+ u_rtl_18b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 18, TRUE, 1, 0, 1, 1);
+ u_rtl_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 27, TRUE, 1, 0, 1, 1);
+
+END tb;
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index ba8ee5a641a7a9e761ad82207b562a499697639c..d8d9608200d771b0c21ab97fe5e6be2860649253 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -216,26 +216,37 @@ peripherals:
mm_port_description: ""
fields:
- - field_name: ctrl_enable
- field_description: "Enable the output when 1, disable the output when 0. To first disable output to re-enable output."
- address_offset: 0 * MM_BUS_SIZE # = 0x0
+ field_description:
+ "Enable the output when 1, disable the output when 0. First disable output to re-enable output."
+ address_offset: 0 * MM_BUS_SIZE
mm_width: 1
access_mode: RW
- - field_name: ctrl_interval_size
- field_description: "Number of samples in output sync interval"
- address_offset: 1 * MM_BUS_SIZE # = 0x4
+ field_description:
+ "Number of samples in output sync interval. For example, for sample rate 200 MHz
+ this implies a maximum sync interval period of 2**31 * 5 ns = 10.7 s (because
+ VHDL NATURAL range is 0 - 2**31-1)"
+ address_offset: 1 * MM_BUS_SIZE
+ mm_width: 31
access_mode: RW
- - field_name: ctrl_start_bsn
field_description:
"Schedule start BSN for the output. The start BSN needs to be in the future,
if the start BSN is in the past or if the input stream is not active, then
ctrl_enable = '1' will have no effect."
- address_offset: 2 * MM_BUS_SIZE # = 0x8
+ address_offset: 2 * MM_BUS_SIZE
user_width: 64
radix: uint64
access_mode: RW
- - field_name: mon_current_input_bsn
field_description: "Current input BSN. This can be read to determine a start BSN in the future."
- address_offset: 4 * MM_BUS_SIZE # = 0x10
+ address_offset: 4 * MM_BUS_SIZE
+ user_width: 64
+ radix: uint64
+ access_mode: RO
+ - - field_name: mon_input_bsn_at_sync
+ field_description: "Input BSN at input sync. This can be read to compare with mon_output_sync_bsn."
+ address_offset: 6 * MM_BUS_SIZE
user_width: 64
radix: uint64
access_mode: RO
@@ -244,21 +255,20 @@ peripherals:
"Is 1 when output is enabled, 0 when output is disabled. The output stream gets
enabled when ctrl_enable is set '1' and when the BSN of the input stream has
reached the ctrl_start_bsn."
- address_offset: 6 * MM_BUS_SIZE # = 0x18
+ address_offset: 8 * MM_BUS_SIZE
mm_width: 1
access_mode: RO
- - field_name: mon_output_sync_bsn
field_description: "Output BSN at sync. This yields the number of blocks per output sync interval."
- address_offset: 7 * MM_BUS_SIZE # = 0x1C
+ address_offset: 9 * MM_BUS_SIZE
user_width: 64
radix: uint64
access_mode: RO
- - field_name: block_size
field_description: "Number of samples per BSN block, same for input stream and output stream."
- address_offset: 9 * MM_BUS_SIZE # = 0x24
+ address_offset: 11 * MM_BUS_SIZE
access_mode: RO
-
- peripheral_name: dp_bsn_monitor # pi_dp_bsn_monitor.py
peripheral_description: "Monitor the Block Sequence Number (BSN) status of streaming data."
parameters:
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 9cc984efdde5e083ce57a73815e6cb4d062c570b..c33690558424837b122beee5e306d9266d1a86ad 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -82,6 +82,12 @@ synth_files =
src/vhdl/dp_block_from_mm.vhd
src/vhdl/dp_block_from_mm_dc.vhd
src/vhdl/dp_block_to_mm.vhd
+ src/vhdl/dp_bsn_monitor.vhd
+ src/vhdl/dp_bsn_monitor_reg.vhd
+ src/vhdl/mms_dp_bsn_monitor.vhd
+ src/vhdl/dp_bsn_monitor_v2.vhd
+ src/vhdl/dp_bsn_monitor_reg_v2.vhd
+ src/vhdl/mms_dp_bsn_monitor_v2.vhd
src/vhdl/dp_bsn_source.vhd
src/vhdl/dp_bsn_source_v2.vhd
src/vhdl/dp_bsn_source_reg.vhd
@@ -93,6 +99,7 @@ synth_files =
src/vhdl/mms_dp_bsn_scheduler.vhd
src/vhdl/dp_bsn_sync_scheduler.vhd
src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+ src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
src/vhdl/dp_bsn_delay.vhd
src/vhdl/dp_bsn_align.vhd
src/vhdl/dp_bsn_align_reg.vhd
@@ -114,12 +121,6 @@ synth_files =
src/vhdl/dp_packet_dec_channel_lo.vhd
src/vhdl/dp_gap.vhd
src/vhdl/dp_mon.vhd
- src/vhdl/dp_bsn_monitor.vhd
- src/vhdl/dp_bsn_monitor_reg.vhd
- src/vhdl/mms_dp_bsn_monitor.vhd
- src/vhdl/dp_bsn_monitor_v2.vhd
- src/vhdl/dp_bsn_monitor_reg_v2.vhd
- src/vhdl/mms_dp_bsn_monitor_v2.vhd
src/vhdl/dp_distribute.vhd
src/vhdl/dp_ram_from_mm.vhd
src/vhdl/dp_ram_from_mm_reg.vhd
@@ -363,7 +364,6 @@ regression_test_vhdl =
tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
tb/vhdl/tb_tb_dp_block_from_mm.vhd
tb/vhdl/tb_tb_dp_block_validate_channel.vhd
- tb/vhdl/tb_tb_dp_bsn_align.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index c926592c910e2f72b5b86e55acfc1294f3b27835..4b88f228595ecc68035b9fa574b36064ebe8b91e 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -37,6 +37,8 @@ ENTITY dp_block_from_mm IS
g_data_size : NATURAL;
g_step_size : NATURAL;
g_nof_data : NATURAL;
+ g_data_w : NATURAL := c_word_w;
+ g_mm_rd_latency : NATURAL := 1; -- default 1 from rd_en to rd_val, use 2 to ease timing closure
g_reverse_word_order : BOOLEAN := FALSE
);
PORT (
@@ -70,8 +72,15 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
+
SIGNAL mm_address : NATURAL := 0;
SIGNAL last_mm_address : NATURAL := 0;
+
+ SIGNAL r_sop_p : STD_LOGIC;
+ SIGNAL r_eop_p : STD_LOGIC;
+ SIGNAL out_sop : STD_LOGIC;
+ SIGNAL out_eop : STD_LOGIC;
+
BEGIN
last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address - 1;
@@ -79,15 +88,21 @@ BEGIN
mm_mosi.address <= TO_MEM_ADDRESS(mm_address);
- u_sosi : PROCESS(r, mm_miso)
+ -- Take care of g_mm_rd_latency for out_sosi.sop and out_sosi.eop
+ r_sop_p <= r.sop WHEN rising_edge(clk);
+ r_eop_p <= r.eop WHEN rising_edge(clk);
+ out_sop <= r.sop WHEN g_mm_rd_latency = 1 ELSE r_sop_p;
+ out_eop <= r.eop WHEN g_mm_rd_latency = 1 ELSE r_eop_p;
+
+ u_sosi : PROCESS(r, mm_miso, out_sop, out_eop)
BEGIN
out_sosi <= c_dp_sosi_rst; -- To avoid Modelsim warnings on conversion to integer from unused fields.
- out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(g_data_w-1 DOWNTO 0));
out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
- out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
- out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+ out_sosi.sop <= out_sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
+ out_sosi.eop <= out_eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
END PROCESS;
-
+
mm_done <= r.eop;
p_reg : PROCESS(rst, clk)
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index 9c888558625dbd66a51de1eb75c8cb7ca028d70b..0d5b21ea615ec19a28357937cc811b4c43b23ddc 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -38,7 +38,7 @@
-- * ctrl_enable:
-- The output is enabled at the ctrl_start_bsn when ctrl_enable = '1' and the
-- output is disable after an in_sosi.eop when ctrl_enable = '0'. If the
--- output is diabled, then the sosai control fields are forced to '0', the
+-- output is diabled, then the sosi control fields are forced to '0', the
-- other sosi fields of the in_sosi are passed on to the out_sosi.
-- * mon_current_input_bsn:
-- The user can read mon_current_input_bsn to determine a suitable
@@ -195,13 +195,19 @@ BEGIN
output_start <= '0';
output_sync <= '0';
+ ---------------------------------------------------------------------------
-- Detect ctrl_enable rising event
+ ---------------------------------------------------------------------------
IF ctrl_enable = '1' AND ctrl_enable_evt = '1' THEN
v.enable_init := '1';
END IF;
- -- Initialization: calculate number of blocks per output sync interval
- -- . use r.enable_init instead of v.enable_init to easy timing closure and
+ ---------------------------------------------------------------------------
+ -- Initialization:
+ -- calculate number of blocks per output sync interval, start with
+ -- nof_blk_max in first sync interval
+ ---------------------------------------------------------------------------
+ -- . use r.enable_init instead of v.enable_init to ease timing closure and
-- because functionally it makes no difference.
IF r.enable_init = '1' THEN
-- Assume ctrl_start_bsn is scheduled more than nof_blk block clk cycles
@@ -239,7 +245,9 @@ BEGIN
v.blk_cnt := 0;
END IF;
- -- Enable / disable control
+ ---------------------------------------------------------------------------
+ -- Enable / re-enable / disable control
+ ---------------------------------------------------------------------------
IF ctrl_enable = '0' THEN
-- Disable output when ctrl_enable requests disable.
v.enable := '0';
@@ -260,6 +268,12 @@ BEGIN
END IF;
END IF;
+ ---------------------------------------------------------------------------
+ -- Output enable / disable
+ -- . enable at start_bsn and issue output_start pulse for first output
+ -- sync interval
+ -- . disable after input block has finished.
+ ---------------------------------------------------------------------------
-- Hold input eop to detect when input has finished a block and to detect
-- gaps between in_sosi.eop and in_sosi.sop
IF in_sosi.sop = '1' THEN
@@ -269,7 +283,9 @@ BEGIN
v.hold_eop := '1';
END IF;
- IF v.enable = '1' THEN
+ -- . use r.enable instead of v.enable to ease timing closure and because
+ -- functionally it makes no difference.
+ IF r.enable = '1' THEN
-- Output enable at in_sosi.sop start_bsn
IF in_sosi.sop = '1' THEN
IF UNSIGNED(in_sosi.bsn) = UNSIGNED(r.start_bsn) THEN
@@ -285,6 +301,9 @@ BEGIN
END IF;
END IF;
+ ---------------------------------------------------------------------------
+ -- Issue output_sync at output_sync_bsn and request next output_sync_bsn
+ ---------------------------------------------------------------------------
-- Generate output sync interval based on input BSN and ctrl_interval_size
IF v.output_enable = '1' THEN
IF in_sosi.sop = '1' THEN
@@ -300,7 +319,9 @@ BEGIN
END IF;
END IF;
- -- Determine BSN for next output sync
+ ---------------------------------------------------------------------------
+ -- Determine BSN for next output_sync (= output_sync_bsn)
+ ---------------------------------------------------------------------------
IF r.update_bsn = '1' THEN
-- Similar code as in proc_dp_verify_sync(), the difference is that:
-- . Here r.extra is number of extra samples in nof_blk_max compared to
@@ -321,8 +342,9 @@ BEGIN
-- Assume output_sync_bsn is in future
v.update_bsn := '0';
- -- else: last r.input_bsn will be used to keep update_bsn active for
- -- more clk cycles to catch up for lost input blocks.
+ -- If output_sync_bsn is still in past, due to lost input blocks, then
+ -- last r.input_bsn will be used to keep update_bsn active for more clk
+ -- cycles to catch up for lost input blocks.
END IF;
-- Hold input bsn
@@ -346,7 +368,10 @@ BEGIN
nxt_r <= v;
END PROCESS;
+ -----------------------------------------------------------------------------
-- Output in_sosi with programmed sync interval or disable the output
+ -----------------------------------------------------------------------------
+ -- . note this is part of p_comb, but using a separate process is fine too.
p_output_sosi : PROCESS(in_sosi, nxt_r, output_sync)
BEGIN
output_sosi <= in_sosi;
@@ -360,7 +385,9 @@ BEGIN
END IF;
END PROCESS;
+ -----------------------------------------------------------------------------
-- Pipeline output to avoid timing closure problems due to use of nxt_r.output_enable
+ -----------------------------------------------------------------------------
u_out_sosi : ENTITY work.dp_pipeline
GENERIC MAP (
g_pipeline => g_pipeline
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 842fa3175e688d1c4048b4417abd2a526e9e6579..75b42316d077b32591da03f6a12aff7ee6da26d9 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -62,8 +62,9 @@ USE work.dp_stream_pkg.ALL;
ENTITY mmp_dp_bsn_sync_scheduler IS
GENERIC (
- g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256 -- = number of data valid per BSN block, must be >= 2
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
);
PORT (
-- Clocks and reset
@@ -126,7 +127,8 @@ BEGIN
-- Register mapping
-- . Write
wr_ctrl_enable <= reg_wr( 0);
- ctrl_interval_size <= TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w));
+ ctrl_interval_size <= TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w)) WHEN
+ g_ctrl_interval_size_min < TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w)) ELSE g_ctrl_interval_size_min;
wr_start_bsn_64( c_word_w-1 DOWNTO 0) <= reg_wr( 3*c_word_w-1 DOWNTO 2*c_word_w); -- low word
wr_start_bsn_64(2*c_word_w-1 DOWNTO 1*c_word_w) <= reg_wr( 4*c_word_w-1 DOWNTO 3*c_word_w); -- high word
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..38a473d061ab50d2a974dc5bc071b5a8d8f9225f
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
@@ -0,0 +1,117 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+--
+-- Author : R. vd Walle
+-- Purpose : Array wrapper for mmp_dp_bsn_sync_scheduler.vhd
+-- Description: This component is wrapper that uses mmp_dp_bsn_sync_scheduler.vhd
+-- with input 0 to determine the streaming control (sync, sop, eop, valid). So
+-- it is assumed that all inputs in in_sosi_arr have identical control signals.
+--
+-- Remarks: See mmp_dp_bsn_sync_scheduler.vhd
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+
+ENTITY mmp_dp_bsn_sync_scheduler_arr IS
+ GENERIC (
+ g_nof_streams : POSITIVE := 1;
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- MM control
+ reg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_miso : OUT t_mem_miso;
+
+ -- Streaming
+ in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_start : OUT STD_LOGIC;
+ out_enable : OUT STD_LOGIC
+ );
+END mmp_dp_bsn_sync_scheduler_arr;
+
+ARCHITECTURE str OF mmp_dp_bsn_sync_scheduler_arr IS
+ CONSTANT c_pipeline : NATURAL := 1;
+
+ SIGNAL single_src_out : t_dp_sosi;
+
+ SIGNAL in_sosi_arr_piped : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+BEGIN
+
+ -- dp_bsn_sync_scheduler
+ u_mmp_dp_bsn_sync_scheduler : ENTITY work.mmp_dp_bsn_sync_scheduler
+ GENERIC MAP (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ in_sosi => in_sosi_arr(0),
+ out_sosi => single_src_out,
+
+ out_start => out_start,
+ out_enable => out_enable
+ );
+
+ -- Pipeline in_sosi_arr to compensate for the latency in mmp_dp_bsn_sync_scheduler
+ u_dp_pipeline_arr : ENTITY work.dp_pipeline_arr
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_piped
+ );
+
+ p_streams : PROCESS(in_sosi_arr_piped, single_src_out)
+ BEGIN
+ out_sosi_arr <= in_sosi_arr_piped;
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ out_sosi_arr(I).sop <= single_src_out.sop;
+ out_sosi_arr(I).eop <= single_src_out.eop;
+ out_sosi_arr(I).valid <= single_src_out.valid;
+ out_sosi_arr(I).sync <= single_src_out.sync;
+ END LOOP;
+ END PROCESS;
+
+END str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index a78e4374514164982b36225ced0865b76fbaecfa..98e3f7259797e72173bfb19b2b4d7baf6fd1a01c 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -240,8 +240,6 @@ BEGIN
gen_nof_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
u_common_complex_mult : ENTITY common_mult_lib.common_complex_mult
GENERIC MAP (
- g_sim => FALSE,
- g_sim_level => 0, -- 0: Simulate variant passed via g_variant for given g_technology
g_technology => g_technology,
g_variant => "IP",
g_in_a_w => g_gain_w,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
index a94570c92e294b528d12f0d07819f6dad441fb7e..67939303a128f1791853c3c7ea1314f5296d2f48 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
@@ -78,8 +78,8 @@ ENTITY tb_dp_bsn_sync_scheduler IS
-- Input sync period and sosi ctrl
g_nof_input_sync : NATURAL := 10;
g_nof_block_per_input_sync : NATURAL := 17;
- g_block_size : NATURAL := 10;
- g_input_gap_size : NATURAL := 3;
+ g_block_size : NATURAL := 2;
+ g_input_gap_size : NATURAL := 0;
-- Output sync period
g_nof_samples_per_output_sync : NATURAL := 45 -- 45 / g_block_size = 4.5
@@ -161,6 +161,8 @@ ARCHITECTURE tb OF tb_dp_bsn_sync_scheduler IS
SIGNAL prev_out_enable : STD_LOGIC := '0';
SIGNAL pending_out_disable : STD_LOGIC := '0';
SIGNAL expected_out_enable : STD_LOGIC := '0';
+ SIGNAL expected_out_enable1 : STD_LOGIC := '0';
+ SIGNAL expected_out_enable2 : STD_LOGIC := '0';
SIGNAL expecting_out_start : STD_LOGIC := '0';
SIGNAL hold_out_eop : STD_LOGIC := '0';
SIGNAL hold_out_sop : STD_LOGIC := '0';
@@ -388,6 +390,9 @@ BEGIN
END IF;
END PROCESS;
+ expected_out_enable1 <= expected_out_enable WHEN rising_edge(clk);
+ expected_out_enable2 <= expected_out_enable1 WHEN rising_edge(clk);
+
p_verify_out_enable : PROCESS(clk)
BEGIN
-- Use registered values to compare, to avoid combinatorial differences
@@ -397,7 +402,16 @@ BEGIN
IF rising_edge(clk) THEN
IF out_enable /= expected_out_enable THEN
IF out_enable = '1' THEN
- REPORT "Unexpected enabled out_enable" SEVERITY ERROR;
+ IF g_block_size > 2 THEN
+ REPORT "Unexpected enabled out_enable" SEVERITY ERROR;
+ ELSIF out_enable /= expected_out_enable2 THEN
+ -- For g_block_size = 2 the use of r.enable (instead of v.enable)
+ -- in dp_bsn_sync_scheduler.vhd causes that the output can stay
+ -- enabled 2 cycles longer, which is ok. Using v.enable does
+ -- avoid this need to use expected_out_enable2, but for timing
+ -- closure it is preferred to use r.enable.
+ REPORT "Unexpected enabled out_enable2" SEVERITY ERROR;
+ END IF;
ELSE
REPORT "Unexpected disabled out_enable" SEVERITY ERROR;
END IF;
diff --git a/libraries/dsp/iquv/src/vhdl/iquv.vhd b/libraries/dsp/iquv/src/vhdl/iquv.vhd
index 9de178c0212ed0fda7899c873db2f446e169ff65..aa48e6f422e2c036f52c1aee47a8e34a94bad0ef 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv.vhd
@@ -181,7 +181,6 @@ BEGIN
------------------------------------------------------------------------------
-- u_CmplxMul_xx : ENTITY common_mult_lib.common_complex_mult
-- GENERIC MAP (
--- g_sim => g_sim,
-- g_technology => g_technology,
-- g_in_a_w => g_in_data_w,
-- g_in_b_w => g_in_data_w,
@@ -203,7 +202,6 @@ BEGIN
u_CmplxMul_xy : ENTITY common_mult_lib.common_complex_mult
GENERIC MAP (
- g_sim => g_sim,
g_technology => g_technology,
g_variant => g_variant,
g_in_a_w => g_in_data_w,
@@ -226,7 +224,6 @@ BEGIN
u_CmplxMul_xxyy : ENTITY common_mult_lib.common_complex_mult
GENERIC MAP (
- g_sim => g_sim,
g_technology => g_technology,
g_variant => g_variant,
g_in_a_w => g_in_data_w,
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index 805b806ab85e5b5e6d6798883148f55d1d553814..a663665879e5e6e7d3ec68c1938e2e46b7100a95 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -6,6 +6,32 @@ hdl_library_name: st
hdl_library_description: "Statistics (ST)"
peripherals:
+ - peripheral_name: st_histogram # pi_st_histogram.py
+ peripheral_description: |
+ "Count per sample value how often it occurs. The sample values are distributed over g_nof_bins = 512 bins per SI.
+ The bins are 32 bit to be able to fit a maximum count of 200M in case the signal input is DC."
+ parameters:
+ # Parameters of mmp_st_histogram.vhd
+ - { name: g_nof_instances, value: 12 }
+ - { name: g_nof_bins, value: 512 }
+ - { name: g_nof_data_per_sync, value: 200000000 }
+ mm_ports:
+ # MM port for mmp_st_histogram.vhd
+ - mm_port_name: RAM_ST_HISTOGRAM
+ mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_nof_bins) * MM_BUS_SIZE
+ mm_port_description: |
+ "The bins are 32 bit to be able to fit a maximum count of 200M in case the signal input is DC."
+ number_of_mm_ports: g_nof_instances
+ fields:
+ - - field_name: histogram
+ field_description: ""
+ number_of_fields: g_nof_bins
+ address_offset: 0x0
+ mm_width: 32
+ user_width: ceil_log2(g_nof_data_per_sync + 1 )
+
+
- peripheral_name: st_sst # pi_st_sst.py
peripheral_description: |
"Accumulate the signal power values during a sync interval:
@@ -125,7 +151,7 @@ peripherals:
# from sdp_pkg.vhd:
# . c_sdp_ram_st_xsq_addr_w = ceil_log2(P_sq) + ceil_log2(N_crosslets * X_sq * c_nof_complex * (c_longword_sz/c_word_sz)
# . c_sdp_X_sq = S_pn**2 = g_nof_signal_inputs**2
- mm_port_span: ceil_pow2(g_nof_streams) + ceil_pow2(g_nof_crosslets * g_nof_signal_inputs**2 * c_nof_complex * g_stat_data_sz) * MM_BUS_SIZE
+ mm_port_span: ceil_pow2(g_nof_crosslets * g_nof_signal_inputs**2 * c_nof_complex * g_stat_data_sz) * MM_BUS_SIZE
mm_port_description: |
"The crosslets statistics per PN are stored in g_nof_streams blocks
of each nof_stat values per block (= per X_sq correlator cell). The
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
index 3b75820430c4f769e6438c811c850a948802943f..ec2dcbbcdf6a8a6288914d8cf48694a1eab0760b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
@@ -34,3 +34,6 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vmap altmult_complex_180 ./work/
vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.vhd"
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
+ vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_27b_altmult_complex_180_ylvsosy.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index abb9b5970ab17e3160c2f6ff5894a185aae6c8c7..45d5f65a6e8e781a09c623d0ec324bdd6f429e17 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -31,3 +31,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd"
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
+ vcom "$IP_DIR/ip_arria10_e1sg_complex_mult_27b.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index 79378af3c98ef6fbb3b1175d5523fb44a2676aff..6debfcd8fea764673a7c664cb7da54ab1a96bac5 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -17,8 +17,10 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult_27b/ip_arria10_e1sg_complex_mult_27b.qip
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e1sg_complex_mult.qsys
+ ip_arria10_e1sg_complex_mult_27b.ip
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult_27b.ip b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult_27b.ip
new file mode 100644
index 0000000000000000000000000000000000000000..7cdcbf9411d70282e84dfbc5363c38d4d76c7d32
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult_27b.ip
@@ -0,0 +1,431 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e1sg_complex_mult_27b</spirit:library>
+ <spirit:name>altmult_complex_0</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>complex_input</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>dataa_real</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>dataa_real</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>dataa_imag</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>dataa_imag</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>datab_real</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>datab_real</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>datab_imag</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>datab_imag</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>clock</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>aclr</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>aclr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ena</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ena</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>complex_output</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>result_real</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>result_real</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>result_imag</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>result_imag</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>altmult_complex</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>dataa_real</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>26</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>dataa_imag</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>26</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>datab_real</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>26</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>datab_imag</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>26</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>clock</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>aclr</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ena</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>result_real</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>53</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>result_imag</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>53</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e1sg_complex_mult_27b</spirit:library>
+ <spirit:name>altmult_complex</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>DEVICE_FAMILY</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="DEVICE_FAMILY">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CBX_AUTO_BLACKBOX</spirit:name>
+ <spirit:displayName>CBX_AUTO_BLACKBOX</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="CBX_AUTO_BLACKBOX">ALL</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIDTH_A</spirit:name>
+ <spirit:displayName>How wide should the A input buses be?</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="WIDTH_A">27</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIDTH_B</spirit:name>
+ <spirit:displayName>How wide should the B input buses be?</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="WIDTH_B">27</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIDTH_RESULT</spirit:name>
+ <spirit:displayName>How wide should the 'result' output bus be?</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="WIDTH_RESULT">54</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REPRESENTATION_A</spirit:name>
+ <spirit:displayName>What is the representation format for A inputs?</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="REPRESENTATION_A">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REPRESENTATION_B</spirit:name>
+ <spirit:displayName>What is the representation format for B inputs?</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="REPRESENTATION_B">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>GUI_DYNAMIC_COMPLEX</spirit:name>
+ <spirit:displayName>Dynamic Complex Mode</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="GUI_DYNAMIC_COMPLEX">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IMPLEMENTATION_STYLE</spirit:name>
+ <spirit:displayName>Which implementation style should be used?</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="IMPLEMENTATION_STYLE">AUTO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PIPELINE</spirit:name>
+ <spirit:displayName>Output latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="PIPELINE">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>GUI_CLEAR_TYPE</spirit:name>
+ <spirit:displayName>Clear Signal Type</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="GUI_CLEAR_TYPE">ACLR</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>GUI_USE_CLKEN</spirit:name>
+ <spirit:displayName>Create a Clock Enable input?</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="GUI_USE_CLKEN">true</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115S2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="complex_input" altera:internal="altmult_complex_0.complex_input" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ <altera:port_mapping altera:name="dataa_imag" altera:internal="dataa_imag"></altera:port_mapping>
+ <altera:port_mapping altera:name="dataa_real" altera:internal="dataa_real"></altera:port_mapping>
+ <altera:port_mapping altera:name="datab_imag" altera:internal="datab_imag"></altera:port_mapping>
+ <altera:port_mapping altera:name="datab_real" altera:internal="datab_real"></altera:port_mapping>
+ <altera:port_mapping altera:name="ena" altera:internal="ena"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="complex_output" altera:internal="altmult_complex_0.complex_output" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_imag" altera:internal="result_imag"></altera:port_mapping>
+ <altera:port_mapping altera:name="result_real" altera:internal="result_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
index 0864beac27c53a6e12511305e60e87de325c4274..39828d81ea79a18a8433195dd133b677b5b3737e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
@@ -34,3 +34,7 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vmap altmult_complex_1910 ./work/
vcom "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_27b_altmult_complex_1910_ecifj3y.vhd" -work altmult_complex_1910
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
index 24d21235f925d508c769aba950bffafd55444092..cc565f44e87cb7f58bd2efde48a9b764ca3da5d2 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
@@ -30,7 +30,8 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
-vmap altmult_complex_1910 ./work/
- vcom "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
- vcom "$IP_DIR/ip_arria10_e2sg_complex_mult.vhd" -work altmult_complex_1910
+ vcom "$IP_DIR/ip_arria10_e2sg_complex_mult.vhd"
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+ vcom "$IP_DIR/ip_arria10_e2sg_complex_mult_27b.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
index a7582656cbbce3505ed6625bd38fdca6948fe08d..c2162613d96f940cea3d3be82cd5713a76a5eda9 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
@@ -17,8 +17,10 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult/ip_arria10_e2sg_complex_mult.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult_27b/ip_arria10_e2sg_complex_mult_27b.qip
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_complex_mult.ip
+ ip_arria10_e2sg_complex_mult_27b.ip
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/ip_arria10_e2sg_complex_mult_27b.ip b/libraries/technology/ip_arria10_e2sg/complex_mult/ip_arria10_e2sg_complex_mult_27b.ip
new file mode 100644
index 0000000000000000000000000000000000000000..cdd533123b7b51a1e4717f47d204ed724291edf4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/ip_arria10_e2sg_complex_mult_27b.ip
@@ -0,0 +1,751 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_arria10_e2sg_complex_mult_27b</ipxact:library>
+ <ipxact:name>altmult_complex_0</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>clock</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altmult_complex</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>53</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>53</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_arria10_e2sg_complex_mult_27b</ipxact:library>
+ <ipxact:name>altmult_complex</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="CBX_AUTO_BLACKBOX" type="string">
+ <ipxact:name>CBX_AUTO_BLACKBOX</ipxact:name>
+ <ipxact:displayName>CBX_AUTO_BLACKBOX</ipxact:displayName>
+ <ipxact:value>ALL</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_A" type="int">
+ <ipxact:name>WIDTH_A</ipxact:name>
+ <ipxact:displayName>How wide should the A input buses be?</ipxact:displayName>
+ <ipxact:value>27</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_B" type="int">
+ <ipxact:name>WIDTH_B</ipxact:name>
+ <ipxact:displayName>How wide should the B input buses be?</ipxact:displayName>
+ <ipxact:value>27</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_RESULT" type="int">
+ <ipxact:name>WIDTH_RESULT</ipxact:name>
+ <ipxact:displayName>How wide should the 'result' output bus be?</ipxact:displayName>
+ <ipxact:value>54</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_A" type="int">
+ <ipxact:name>REPRESENTATION_A</ipxact:name>
+ <ipxact:displayName>What is the representation format for A inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_B" type="int">
+ <ipxact:name>REPRESENTATION_B</ipxact:name>
+ <ipxact:displayName>What is the representation format for B inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DYNAMIC_COMPLEX" type="bit">
+ <ipxact:name>GUI_DYNAMIC_COMPLEX</ipxact:name>
+ <ipxact:displayName>Dynamic Complex Mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="IMPLEMENTATION_STYLE" type="string">
+ <ipxact:name>IMPLEMENTATION_STYLE</ipxact:name>
+ <ipxact:displayName>Which implementation style should be used?</ipxact:displayName>
+ <ipxact:value>AUTO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="PIPELINE" type="int">
+ <ipxact:name>PIPELINE</ipxact:name>
+ <ipxact:displayName>Output latency</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLEAR_TYPE" type="string">
+ <ipxact:name>GUI_CLEAR_TYPE</ipxact:name>
+ <ipxact:displayName>Clear Signal Type</ipxact:displayName>
+ <ipxact:value>ACLR</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_USE_CLKEN" type="bit">
+ <ipxact:name>GUI_USE_CLKEN</ipxact:name>
+ <ipxact:displayName>Create a Clock Enable input?</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="aclr" altera:internal="altmult_complex_0.aclr" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="altmult_complex_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_imag" altera:internal="altmult_complex_0.dataa_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_imag" altera:internal="dataa_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_real" altera:internal="altmult_complex_0.dataa_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_real" altera:internal="dataa_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_imag" altera:internal="altmult_complex_0.datab_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_imag" altera:internal="datab_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_real" altera:internal="altmult_complex_0.datab_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_real" altera:internal="datab_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="ena" altera:internal="altmult_complex_0.ena" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ena" altera:internal="ena"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_imag" altera:internal="altmult_complex_0.result_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_imag" altera:internal="result_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_real" altera:internal="altmult_complex_0.result_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_real" altera:internal="result_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index bdaa07ad2df9bde03f94a4dd6c555db47fbe33fd..228c1ee4a79b2c0c20664a98a2794ddf4464f208 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -18,6 +18,41 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
+--
+-- Author : E. Kooistra
+-- Purpose : Wrapper for complex multiplier IP
+-- Decription :
+--
+-- Calculate complex product:
+--
+-- (ar + j*ai) * (br + j*bi) = (ar*br - ai*bi) + j *(ar*bi + ai*br)
+-- = pr + j * pi
+--
+-- Assume IP is generated for complex product width for pr, pi of:
+--
+-- c_dsp_prod_w = 2*c_dsp_dat_w.
+--
+-- It is not necessary to support product width 2*c_dsp_dat_w + 1,
+-- because this +1 bit is only needed for pi in case ar = ai = br = bi
+-- = min, where
+--
+-- min = -2**(c_dsp_dat_w-1)
+-- max = 2**(c_dsp_dat_w-1) - 1.
+--
+-- The largest value for pi = min**2 + min**2.
+-- The largest value for pr = min**2 - min*max < largest pi.
+--
+-- The largest pi = 2 * min**2 = 2**(c_dsp_dat_w-1), so it just does not
+-- fit in c_dsp_prod_w, but largest pi - 1 = 2**(c_dsp_dat_w-1) - 1 does
+-- fit, so all other input values fit. In DSP systems the input value
+-- (min + j*min) typically never occurs.
+--
+-- Example: g_in_a_w = 3 bit:
+-- --> min = -4
+-- c_dsp_prod_w = 6
+-- --> largest pi = 32
+-- --> largest pi - 1 = 31 = 2**(c_dsp_prod_w-1) - 1
+--
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
@@ -38,8 +73,6 @@ LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
ENTITY tech_complex_mult IS
GENERIC (
- g_sim : BOOLEAN := TRUE;
- g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
g_technology : NATURAL := c_tech_select_default;
g_variant : STRING := "IP";
g_in_a_w : POSITIVE;
@@ -66,14 +99,8 @@ END tech_complex_mult;
ARCHITECTURE str of tech_complex_mult is
- -- Force to maximum 18 bit width, because:
- -- . the ip_stratixiv_complex_mult is generated for 18b inputs and 36b output and then uses 4 real multipliers and no additional registers
- -- . if one input > 18b then another IP needs to be regenerated and that will use 8 real multipliers and some extra LUTs and registers
- -- . if both inputs > 18b then another IP needs to be regenerated and that will use 16 real multipliers and some extra LUTs and registers
- -- . if the output is set to 18b+18b + 1b =37b to account for the sum then another IP needs to be regenerated and that will use some extra registers
- -- ==> for inputs <= 18b this ip_stratixiv_complex_mult is appropriate and it can not be made parametrisable to fit also inputs > 18b.
- CONSTANT c_dsp_dat_w : NATURAL := 18;
- CONSTANT c_dsp_prod_w : NATURAL := 2*c_dsp_dat_w;
+ CONSTANT c_dsp_dat_w : NATURAL := sel_a_b(g_in_a_w <= c_dsp_mult_18_w, c_dsp_mult_18_w, c_dsp_mult_27_w); -- g_in_a_w = g_in_b_w
+ CONSTANT c_dsp_prod_w : NATURAL := 2*c_dsp_dat_w;
SIGNAL ar : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
SIGNAL ai : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
@@ -82,244 +109,253 @@ ARCHITECTURE str of tech_complex_mult is
SIGNAL mult_re : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
SIGNAL mult_im : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
- -- sim_model=1
- SIGNAL result_re_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
- SIGNAL result_im_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
-
-begin
+BEGIN
- gen_ip_stratixiv_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
+ -----------------------------------------------------------------------------
+ -- IP variants for <= 18 bit
+ -----------------------------------------------------------------------------
+ gen_ip_stratixiv_ip : IF g_variant="IP" AND g_technology=c_tech_stratixiv AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
- ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
- ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
- br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
- bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
u0 : ip_stratixiv_complex_mult
PORT MAP (
- aclr => rst,
- clock => clk,
- dataa_imag => ai,
- dataa_real => ar,
- datab_imag => bi,
- datab_real => br,
- ena => clken,
- result_imag => mult_im,
- result_real => mult_re
- );
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
-
END GENERATE;
- gen_ip_stratixiv_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
- u0 : ip_stratixiv_complex_mult_rtl
- GENERIC MAP(
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- PORT MAP(
- rst => rst,
- clk => clk,
- clken => clken,
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- result_re => result_re,
- result_im => result_im
- );
- END GENERATE;
-
- gen_ip_arria10_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10 AND g_variant="IP") GENERATE
-
+ gen_ip_arria10_ip : IF g_variant="IP" AND g_technology=c_tech_arria10 AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
- ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
- ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
- br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
- bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
u0 : ip_arria10_complex_mult
PORT MAP (
- aclr => rst,
- clock => clk,
- dataa_imag => ai,
- dataa_real => ar,
- datab_imag => bi,
- datab_real => br,
- ena => clken,
- result_imag => mult_im,
- result_real => mult_re
- );
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
-
END GENERATE;
- -- RTL variant is the same for unb2, unb2a and unb2b
- gen_ip_arria10_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND
- ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg) AND g_variant="RTL") GENERATE
- u0 : ip_arria10_complex_mult_rtl
- GENERIC MAP(
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- PORT MAP(
- rst => rst,
- clk => clk,
- clken => clken,
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- result_re => result_re,
- result_im => result_im
+ gen_ip_arria10_e1sg_ip : IF g_variant="IP" AND g_technology=c_tech_arria10_e1sg AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
+ -- Adapt DSP input widths
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
+
+ u0 : ip_arria10_e1sg_complex_mult
+ PORT MAP (
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
);
+
+ -- Back to true input widths and then resize for output width
+ result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+ result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
- gen_ip_arria10_rtl_canonical : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND
- ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg) AND g_variant="RTL_C") GENERATE
- u0 : ip_arria10_complex_mult_rtl_canonical
- GENERIC MAP(
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
--- g_conjugate_b => g_conjugate_b, -- NOT SUPPORTED
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- PORT MAP(
- rst => rst,
- clk => clk,
- clken => clken,
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- result_re => result_re,
- result_im => result_im
+ gen_ip_arria10_e2sg_ip : IF g_variant="IP" AND g_technology=c_tech_arria10_e2sg AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
+ -- Adapt DSP input widths
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
+
+ u0 : ip_arria10_e2sg_complex_mult
+ PORT MAP (
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
);
+
+ -- Back to true input widths and then resize for output width
+ result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+ result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
- gen_ip_arria10_e1sg_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10_e1sg AND g_variant="IP") GENERATE
+ -----------------------------------------------------------------------------
+ -- IP variants for > 18 bit and <= 27 bit
+ -----------------------------------------------------------------------------
+ gen_ip_arria10_e1sg_ip_27b : IF g_variant="IP" AND g_technology=c_tech_arria10_e1sg AND c_dsp_dat_w > c_dsp_mult_18_w AND c_dsp_dat_w <= c_dsp_mult_27_w GENERATE
-- Adapt DSP input widths
- ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
- ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
- br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
- bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
-
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
- u0 : ip_arria10_e1sg_complex_mult
+ u0 : ip_arria10_e1sg_complex_mult_27b
PORT MAP (
- aclr => rst,
- clock => clk,
- dataa_imag => ai,
- dataa_real => ar,
- datab_imag => bi,
- datab_real => br,
- ena => clken,
- result_imag => mult_im,
- result_real => mult_re
- );
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
-
END GENERATE;
- gen_ip_arria10_e2sg_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10_e2sg AND g_variant="IP") GENERATE
-
+ gen_ip_arria10_e2sg_ip_27b : IF g_variant="IP" AND g_technology=c_tech_arria10_e2sg AND c_dsp_dat_w > c_dsp_mult_18_w AND c_dsp_dat_w <= c_dsp_mult_27_w GENERATE
-- Adapt DSP input widths
- ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
- ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
- br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
- bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
-
- u0 : ip_arria10_e2sg_complex_mult
+ u0 : ip_arria10_e2sg_complex_mult_27b
PORT MAP (
- aclr => rst,
- clock => clk,
- dataa_imag => ai,
- dataa_real => ar,
- datab_imag => bi,
- datab_real => br,
- ena => clken,
- result_imag => mult_im,
- result_real => mult_re
- );
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
-
END GENERATE;
- -------------------------------------------------------------------------------
- -- Model: forward concatenated inputs to the 'result' output
- --
- -- Example:
- -- ______
- -- Input B.real (in_br) = 0x1111 --> | |
- -- .imag (in_bi) = 0xBBBB --> | |
- -- | mult | --> Output result.real = 0x00000000
- -- Input A.real (in_ar) = 0x0000 --> | | .imag = 0xBBBBAAAA
- -- .imag (in_ai) = 0xAAAA --> |______|
- --
- -- Note: this model is synthsizable as well.
- --
- -------------------------------------------------------------------------------
- gen_sim_level_1 : IF g_sim=TRUE AND g_sim_level=1 GENERATE --FIXME: g_sim required? This is synthesizable.
-
- result_re_undelayed <= in_br & in_ar;
- result_im_undelayed <= in_bi & in_ai;
-
- u_common_pipeline_re : entity common_lib.common_pipeline
- generic map (
- g_pipeline => 3,
- g_in_dat_w => g_in_b_w+g_in_a_w,
- g_out_dat_w => g_out_p_w
+ -----------------------------------------------------------------------------
+ -- RTL variants that can infer multipliers for a technology, fits all widths
+ -----------------------------------------------------------------------------
+ gen_ip_stratixiv_rtl : IF g_variant="RTL" AND g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_complex_mult_rtl
+ GENERIC MAP (
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
)
- port map (
- clk => clk,
- in_dat => result_re_undelayed,
- out_dat => result_re
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ result_re => result_re,
+ result_im => result_im
);
+ END GENERATE;
- u_common_pipeline_im : entity common_lib.common_pipeline
- generic map (
- g_pipeline => 3,
- g_in_dat_w => g_in_b_w+g_in_a_w,
- g_out_dat_w => g_out_p_w
+ -- RTL variant is the same for unb2, unb2a and unb2b
+ gen_ip_arria10_rtl : IF g_variant="RTL" AND (g_technology=c_tech_arria10 OR
+ g_technology=c_tech_arria10_e3sge3 OR
+ g_technology=c_tech_arria10_e1sg OR
+ g_technology=c_tech_arria10_e2sg) GENERATE
+ u0 : ip_arria10_complex_mult_rtl
+ GENERIC MAP (
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
)
- port map (
- clk => clk,
- in_dat => result_im_undelayed,
- out_dat => result_im
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ result_re => result_re,
+ result_im => result_im
);
+ END GENERATE;
+
+ -- RTL variant is the same for unb2, unb2a and unb2b
+ gen_ip_arria10_rtl_canonical : IF g_variant="RTL_C" AND (g_technology=c_tech_arria10 OR
+ g_technology=c_tech_arria10_e3sge3 OR
+ g_technology=c_tech_arria10_e1sg OR
+ g_technology=c_tech_arria10_e2sg) GENERATE
+ -- support g_conjugate_b
+ bi <= in_bi WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
+ u0 : ip_arria10_complex_mult_rtl_canonical
+ GENERIC MAP (
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => bi,
+ result_re => result_re,
+ result_im => result_im
+ );
END GENERATE;
end str;
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 912d3ea189adbb09aa243f42717e6c01d2ebd9dc..a83f4e1221207fbd885f5772806aa9ab314ef34a 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -361,6 +361,19 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e1sg_complex_mult_27b is
+ PORT (
+ dataa_real : in std_logic_vector(26 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(53 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(53 downto 0) -- .result_imag
+ );
+ END COMPONENT;
-----------------------------------------------------------------------------
-- Arria 10 e2sg components
-----------------------------------------------------------------------------
@@ -426,4 +439,17 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e2sg_complex_mult_27b is
+ PORT (
+ dataa_real : in std_logic_vector(26 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(53 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(53 downto 0) -- .result_imag
+ );
+ END COMPONENT;
END tech_mult_component_pkg;