diff --git a/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold
index cf11530f03b11841fe27976ab2c48add046d1660..676867fd878df8e3736ca9b0adbfb1c53b9a4b79 100644
--- a/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold
+++ b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold
@@ -500,12 +500,16 @@ number_of_columns = 13
REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00c00000 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00c00000 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00c00000 1 RO uint32 b[3:2] - - -
- REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00c80000 1 WO uint32 b[0:0] - - -
- - - - - wr_not_rd 0x00c80001 1 WO uint32 b[0:0] - - -
- - - - - done 0x00c80002 1 RO uint32 b[0:0] - - -
- - - - - address 0x00c80005 1 WO uint32 b[31:0] - - -
- - - - - burstsize 0x00c80006 1 WO uint32 b[31:0] - - -
- - - - - flush 0x00c80007 1 RW uint32 b[0:0] - - -
+ REG_IO_DDR_MB_I 1 1 REG reg_io_ddr 0x00c80000 1 RO uint32 b[31:0] - - -
+ - - - - reg_rd_fifo_used 0x00c80001 1 RO uint32 b[31:0] - - -
+ - - - - reg_wr_fifo_used 0x00c80002 1 RO uint32 b[31:0] - - -
+ - - - - reg_fifo_full 0x00c80003 1 RO uint32 b[31:0] - - -
+ - - - - reg_burstbegin 0x00c80008 1 WO uint32 b[31:0] - - -
+ - - - - reg_wr_not_rd 0x00c80009 1 WO uint32 b[31:0] - - -
+ - - - - reg_done 0x00c8000a 1 RO uint32 b[31:0] - - -
+ - - - - reg_address 0x00c8000d 1 WO uint32 b[31:0] - - -
+ - - - - reg_burstsize 0x00c8000e 1 WO uint32 b[31:0] - - -
+ - - - - reg_flush 0x00c8000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00d00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00d00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00d00002 1 RO uint32 b[31:0] - - -
@@ -521,12 +525,16 @@ number_of_columns = 13
REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00e00000 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00e00001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00e00400 1024 RW uint32 b[31:0] - - -
- REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00e80000 1 WO uint32 b[0:0] - - -
- - - - - wr_not_rd 0x00e80001 1 WO uint32 b[0:0] - - -
- - - - - done 0x00e80002 1 RO uint32 b[0:0] - - -
- - - - - address 0x00e80005 1 WO uint32 b[31:0] - - -
- - - - - burstsize 0x00e80006 1 WO uint32 b[31:0] - - -
- - - - - flush 0x00e80007 1 RW uint32 b[0:0] - - -
+ REG_IO_DDR_MB_II 1 1 REG reg_io_ddr 0x00e80000 1 RO uint32 b[31:0] - - -
+ - - - - reg_rd_fifo_used 0x00e80001 1 RO uint32 b[31:0] - - -
+ - - - - reg_wr_fifo_used 0x00e80002 1 RO uint32 b[31:0] - - -
+ - - - - reg_fifo_full 0x00e80003 1 RO uint32 b[31:0] - - -
+ - - - - reg_burstbegin 0x00e80008 1 WO uint32 b[31:0] - - -
+ - - - - reg_wr_not_rd 0x00e80009 1 WO uint32 b[31:0] - - -
+ - - - - reg_done 0x00e8000a 1 RO uint32 b[31:0] - - -
+ - - - - reg_address 0x00e8000d 1 WO uint32 b[31:0] - - -
+ - - - - reg_burstsize 0x00e8000e 1 WO uint32 b[31:0] - - -
+ - - - - reg_flush 0x00e8000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00f00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00f00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00f00002 1 RO uint32 b[31:0] - - -
@@ -544,7 +552,16 @@ number_of_columns = 13
RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x01000400 1024 RW uint32 b[31:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x01080000 1 RW uint32 b[30:0] - - -
- - - - reset 0x01080000 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_dll_ctrl 0x01100014 1 RW uint32 b[16:0] - - 256
+ JESD204B 1 12 REG rx_lane_ctrl_common 0x01100000 1 RW uint32 b[2:0] - - 256
+ - - - - rx_lane_ctrl_0 0x01100001 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_1 0x01100002 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_2 0x01100003 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_3 0x01100004 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_4 0x01100005 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_5 0x01100006 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_6 0x01100007 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_7 0x01100008 1 RW uint32 b[2:0] - - -
+ - - - - rx_dll_ctrl 0x01100014 1 RW uint32 b[16:0] - - -
- - - - rx_syncn_sysref_ctrl 0x01100015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x01100015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x01100015 1 RW uint32 b[10:3] - - -
@@ -590,4 +607,4 @@ number_of_columns = 13
- - - - bsn_first_cycle_cnt 0x01200008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x01280000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x01280001 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x01400000 131072 RW uint32 b[31:0] b[15:0] - 131072
\ No newline at end of file
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x01400000 131072 RW uint32 b[31:0] b[15:0] - 131072
diff --git a/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold
index 1a6fd7ca8c6dc6885306579da9b11ec7756b27ae..e1b784484e26d99f042c2d9a709e052b8f3ae5ee 100644
--- a/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold
+++ b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold
@@ -500,12 +500,16 @@ number_of_columns = 13
REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00000c80 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00000c80 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00000c80 1 RO uint32 b[3:2] - - -
- REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00160000 1 WO uint32 b[0:0] - - -
- - - - - wr_not_rd 0x00160001 1 WO uint32 b[0:0] - - -
- - - - - done 0x00160002 1 RO uint32 b[0:0] - - -
- - - - - address 0x00160005 1 WO uint32 b[31:0] - - -
- - - - - burstsize 0x00160006 1 WO uint32 b[31:0] - - -
- - - - - flush 0x00160007 1 RW uint32 b[0:0] - - -
+ REG_IO_DDR_MB_I 1 1 REG reg_io_ddr 0x00160000 1 RO uint32 b[31:0] - - -
+ - - - - reg_rd_fifo_used 0x00160001 1 RO uint32 b[31:0] - - -
+ - - - - reg_wr_fifo_used 0x00160002 1 RO uint32 b[31:0] - - -
+ - - - - reg_fifo_full 0x00160003 1 RO uint32 b[31:0] - - -
+ - - - - reg_burstbegin 0x00160008 1 WO uint32 b[31:0] - - -
+ - - - - reg_wr_not_rd 0x00160009 1 WO uint32 b[31:0] - - -
+ - - - - reg_done 0x0016000a 1 RO uint32 b[31:0] - - -
+ - - - - reg_address 0x0016000d 1 WO uint32 b[31:0] - - -
+ - - - - reg_burstsize 0x0016000e 1 WO uint32 b[31:0] - - -
+ - - - - reg_flush 0x0016000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00000db8 1 RW uint32 b[2:0] - - -
- - - - init 0x00000db9 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000dba 1 RO uint32 b[31:0] - - -
@@ -521,12 +525,16 @@ number_of_columns = 13
REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00000cc0 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00000cc1 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00003800 1024 RW uint32 b[31:0] - - -
- REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00010000 1 WO uint32 b[0:0] - - -
- - - - - wr_not_rd 0x00010001 1 WO uint32 b[0:0] - - -
- - - - - done 0x00010002 1 RO uint32 b[0:0] - - -
- - - - - address 0x00010005 1 WO uint32 b[31:0] - - -
- - - - - burstsize 0x00010006 1 WO uint32 b[31:0] - - -
- - - - - flush 0x00010007 1 RW uint32 b[0:0] - - -
+ REG_IO_DDR_MB_II 1 1 REG reg_io_ddr 0x00010000 1 RO uint32 b[31:0] - - -
+ - - - - reg_rd_fifo_used 0x00010001 1 RO uint32 b[31:0] - - -
+ - - - - reg_wr_fifo_used 0x00010002 1 RO uint32 b[31:0] - - -
+ - - - - reg_fifo_full 0x00010003 1 RO uint32 b[31:0] - - -
+ - - - - reg_burstbegin 0x00010008 1 WO uint32 b[31:0] - - -
+ - - - - reg_wr_not_rd 0x00010009 1 WO uint32 b[31:0] - - -
+ - - - - reg_done 0x0001000a 1 RO uint32 b[31:0] - - -
+ - - - - reg_address 0x0001000d 1 WO uint32 b[31:0] - - -
+ - - - - reg_burstsize 0x0001000e 1 WO uint32 b[31:0] - - -
+ - - - - reg_flush 0x0001000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00000db4 1 RW uint32 b[2:0] - - -
- - - - init 0x00000db5 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000db6 1 RO uint32 b[31:0] - - -
@@ -544,7 +552,16 @@ number_of_columns = 13
RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x00003000 1024 RW uint32 b[31:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x00000c02 1 RW uint32 b[30:0] - - -
- - - - reset 0x00000c02 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_dll_ctrl 0x00002014 1 RW uint32 b[16:0] - - 256
+ JESD204B 1 12 REG rx_lane_ctrl_common 0x00002000 1 RW uint32 b[2:0] - - 256
+ - - - - rx_lane_ctrl_0 0x00002001 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_1 0x00002002 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_2 0x00002003 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_3 0x00002004 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_4 0x00002005 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_5 0x00002006 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_6 0x00002007 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_7 0x00002008 1 RW uint32 b[2:0] - - -
+ - - - - rx_dll_ctrl 0x00002014 1 RW uint32 b[16:0] - - -
- - - - rx_syncn_sysref_ctrl 0x00002015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x00002015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x00002015 1 RW uint32 b[10:3] - - -
@@ -590,4 +607,4 @@ number_of_columns = 13
- - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00001000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00001001 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 131072 RW uint32 b[31:0] b[15:0] - 131072
\ No newline at end of file
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 131072 RW uint32 b[31:0] b[15:0] - 131072
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index c6099df21d64af3a6afc9cd105e9e5bb8d1dda26..2313b1f23bf3155653da5728c03d0de13e930238 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -78,7 +78,7 @@ peripherals:
field_description: |
"When enable_stream = 0 the data stream is stopped, else when 1 then the data stream is passed on.
Toggling the data stream on or off happens at block or packet boundaries."
- number_of_fields: 1 #g_nof_streams #sel_a_b(g_combine_streams, 1, g_nof_streams)
+ number_of_fields: g_nof_streams # sel_a_b(g_combine_streams, 1, g_nof_streams)
address_offset: 0x0
mm_width: 1
access_mode: RW
@@ -431,20 +431,20 @@ peripherals:
fields:
- - field_name: err_count_index
field_description: "The total amount of discarded DP blocks per bit in the in_sosi.err field (g_nof_err_counts-1 DOWNTO 0)."
- number_of_fields: 8 #g_nof_err_counts
+ number_of_fields: g_nof_err_counts
address_offset: 0
access_mode: RO
- - field_name: total_discarded_blocks
field_description: "The total amount of discarded DP blocks."
- address_offset: 8 * MM_BUS_SIZE #g_nof_err_counts * MM_BUS_SIZE
+ address_offset: g_nof_err_counts * MM_BUS_SIZE # 8 * MM_BUS_SIZE
access_mode: RO
- - field_name: total_block_count
field_description: "The total amount of DP blocks that streamed in this dp_block_validate_err."
- address_offset: 9 * MM_BUS_SIZE #(g_nof_err_counts + 1) * MM_BUS_SIZE
+ address_offset: (g_nof_err_counts + 1) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
access_mode: RO
- - field_name: clear
field_description: "Read or write this register to clear all counters."
- address_offset: 10 * MM_BUS_SIZE #(g_nof_err_counts + 2) * MM_BUS_SIZE
+ address_offset: (g_nof_err_counts + 2) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
access_mode: RW
diff --git a/libraries/base/util/util.peripheral.yaml b/libraries/base/util/util.peripheral.yaml
index 2a4a75357795c7a3fcef7f98b31b720e96ad0776..8406cf5175742bd55b9094fdb9cd6441d6af3712 100644
--- a/libraries/base/util/util.peripheral.yaml
+++ b/libraries/base/util/util.peripheral.yaml
@@ -9,21 +9,21 @@ peripherals:
peripheral_description: "Heater component, see util_heater.vhd"
parameters:
- { name: c_nof_mac4_max, value: 800 }
- - { name: c_reg_nof_words, value: c_nof_mac4_max // 32 } # = 25
+ - { name: c_reg_nof_words, value: c_nof_mac4_max // 32 } # = 25 for c_nof_mac4_max=800
mm_ports:
# MM port for util_heater.vhd
- mm_port_name: REG_HEATER
mm_port_type: REG
- mm_port_span: ceil_pow2(25) * MM_BUS_SIZE #ceil_pow2(c_reg_nof_words) * MM_BUS_SIZE
+ mm_port_span: ceil_pow2(25) * MM_BUS_SIZE # ceil_pow2(c_reg_nof_words) * MM_BUS_SIZE
mm_port_description: "Heater control."
fields:
- - field_name: enable
field_description: |
"The heater elements can be enabled or disabled via this MM register.
Each heater element consists of a MAC4. A MAC4 uses 4 18x18 multipliers.
- The MM register allows enabling 0, 1, more or all MAC4 under SW control.
+ The MM register allows enabling 0, 1, more or all MAC4 under SW control.
In this way it is possible to vary the power consumption during run time."
- number_of_fields: 25 #c_reg_nof_words
+ number_of_fields: c_reg_nof_words
address_offset: 0x0