diff --git a/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd b/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
index a4e98b94f6a839f600c5450590d58cb8216b79ef..2bf0862857e84c76b552dce24023cfa5478bb0dc 100644
--- a/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
+++ b/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, io_ddr_lib, technology_lib, tech_ddr_lib, reorder_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, reorder_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -73,17 +73,15 @@ PORT (
ram_ss_ss_transp_miso : OUT t_mem_miso;
-- SO-DIMM Memory Bank I
- MB_I_IN : IN t_tech_ddr_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
- MB_I_IO : INOUT t_tech_ddr_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
- MB_I_OU : OUT t_tech_ddr_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0)
- );
+ MB_I_IN : IN t_tech_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
+ MB_I_IO : INOUT t_tech_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
+ MB_I_OU : OUT t_tech_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0)
+ );
END node_unb1_reorder;
ARCHITECTURE str OF node_unb1_reorder IS
- CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-
CONSTANT g_tech_select_default : NATURAL := c_tech_select_default;
CONSTANT c_cross_domain_dvr_ctlr : BOOLEAN := TRUE;
@@ -95,8 +93,18 @@ ARCHITECTURE str OF node_unb1_reorder IS
CONSTANT c_wr_data_w : NATURAL := c_data_w;
CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
- CONSTANT c_rd_data_w : NATURAL := c_data_w;
-
+ CONSTANT c_rd_data_w : NATURAL := c_data_w;
+
+-- CONSTANT c_mts : NATURAL := 800;--1066; --800
+-- CONSTANT c_phy : NATURAL := 1;
+-- CONSTANT c_nof_blk_per_sync : POSITIVE := 1600000;
+-- CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_reorder_seq.wr_chunksize,
+-- 1,
+-- g_reorder_seq.rd_chunksize,
+-- g_reorder_seq.rd_nof_chunks,
+-- g_reorder_seq.gapsize,
+-- g_reorder_seq.nof_blocks);
+--
-- Signals to interface with the DDR conroller and memory model.
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
@@ -106,19 +114,69 @@ ARCHITECTURE str OF node_unb1_reorder IS
SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi : t_dp_sosi;
- SIGNAL phy_in : t_tech_ddr_phy_in;
- SIGNAL phy_io : t_tech_ddr_phy_io;
- SIGNAL phy_ou : t_tech_ddr_phy_ou;
-
SIGNAL ctlr_clk : STD_LOGIC;
SIGNAL ctlr_rst : STD_LOGIC;
BEGIN
+ ------------------------------------------------------------------------------
+ -- OLD DDR3 TRANSPOSE
+ ------------------------------------------------------------------------------
+-- u_ddr3_T: ENTITY ddr3_lib.ddr3_transpose
+-- GENERIC MAP(
+-- g_sim => g_sim,
+-- g_nof_streams => g_nof_streams,
+-- g_in_dat_w => g_in_dat_w,
+-- g_frame_size_in => g_reorder_seq.wr_chunksize,
+-- g_frame_size_out => g_reorder_seq.wr_chunksize,
+-- g_nof_blk_per_sync => c_nof_blk_per_sync,
+-- g_use_complex => TRUE,
+-- g_ena_pre_transp => g_ena_pre_transp,
+-- g_phy => c_phy,
+-- g_mts => c_mts,
+-- g_ddr3_seq => c_ddr3_seq_conf
+-- )
+-- PORT MAP (
+-- mm_rst => mm_rst,
+-- mm_clk => mm_clk,
+--
+-- dp_ref_clk => ddr_ref_clk,
+-- dp_ref_rst => ddr_ref_rst,
+--
+-- dp_clk => dp_clk,
+-- dp_rst => dp_rst,
+--
+-- dp_out_clk => ddr_out_clk,
+-- dp_out_rst => ddr_out_rst,
+--
+-- snk_out_arr => in_siso_arr,
+-- snk_in_arr => in_sosi_arr,
+--
+-- reg_io_ddr_mosi => reg_io_ddr_mosi,
+-- reg_io_ddr_miso => reg_io_ddr_miso,
+--
+-- -- ST source
+-- src_in_arr => out_siso_arr,
+-- src_out_arr => out_sosi_arr,
+--
+-- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+-- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+--
+-- ser_term_ctrl_out => OPEN,
+-- par_term_ctrl_out => OPEN,
+--
+-- ser_term_ctrl_in => OPEN,
+-- par_term_ctrl_in => OPEN,
+--
+-- phy_in => MB_I_in(0),
+-- phy_io => MB_I_io(0),
+-- phy_ou => MB_I_ou(0)
+-- );
+
+
------------------------------------------------------------------------------
-- TRANSPOSE UNIT
------------------------------------------------------------------------------
-
u_transpose: ENTITY reorder_lib.reorder_transpose
GENERIC MAP(
g_sim => g_sim,
@@ -168,8 +226,7 @@ BEGIN
u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
g_technology => g_tech_select_default,
- g_tech_ddr => c_tech_ddr,
- g_use_ddr_memory_model => FALSE,
+ g_tech_ddr => g_tech_ddr,
g_cross_domain_dvr_ctlr => FALSE,
g_wr_data_w => c_wr_data_w,
g_wr_fifo_depth => c_wr_fifo_depth,
@@ -227,9 +284,9 @@ BEGIN
term_ctrl_out => OPEN,
term_ctrl_in => OPEN,
- phy_in => MB_I_IN(0),
- phy_io => MB_I_IO(0),
- phy_ou => MB_I_OU(0)
+ phy3_in => MB_I_IN(0),
+ phy3_io => MB_I_IO(0),
+ phy3_ou => MB_I_OU(0)
);
END str;