diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
index 29d982b2f023daf9d0cfc422431d8cb6bfa8f59a..07077df7765b9724d10719937d178a27c82c5969 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
@@ -53,7 +53,7 @@ ENTITY arts_unb1_sc4 IS
g_sim : BOOLEAN := FALSE; -- Overridden by simulation test bench
g_omit_proc : BOOLEAN := FALSE; -- Overridden by simulation test bench
g_use_10GbE : BOOLEAN := TRUE; -- Overridden by simulation test bench, change to TRUE to synthesise full design
- g_use_db : BOOLEAN := FALSE; -- TRUE to include data buffers in the processing module
+ g_use_db : BOOLEAN := TRUE; --FALSE; -- TRUE to include data buffers in the processing module
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
@@ -186,6 +186,9 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
SIGNAL reg_diag_data_buf_wpfbout_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_wpfbout_miso : t_mem_miso;
+ SIGNAL ram_arts_tab_beamformer_mosi : t_mem_mosi;
+ SIGNAL ram_arts_tab_beamformer_miso : t_mem_miso;
+
-------------------------------------------------------------------------------
-- Output
-------------------------------------------------------------------------------
@@ -395,8 +398,8 @@ BEGIN
reg_diag_data_buf_wpfbout_mosi => reg_diag_data_buf_wpfbout_mosi,
reg_diag_data_buf_wpfbout_miso => reg_diag_data_buf_wpfbout_miso,
- ram_arts_tab_beamformer_mosi => c_mem_mosi_rst,
- ram_arts_tab_beamformer_miso => OPEN,
+ ram_arts_tab_beamformer_mosi => ram_arts_tab_beamformer_mosi,
+ ram_arts_tab_beamformer_miso => ram_arts_tab_beamformer_miso,
snk_in_arr => arts_unb1_sc4_input_src_out_arr,
@@ -614,6 +617,9 @@ BEGIN
reg_dp_gain_v_mosi => reg_dp_gain_v_mosi,
reg_dp_gain_v_miso => reg_dp_gain_v_miso,
+ ram_arts_tab_beamformer_mosi => ram_arts_tab_beamformer_mosi,
+ ram_arts_tab_beamformer_miso => ram_arts_tab_beamformer_miso,
+
ram_diag_data_buf_wpfbin_mosi => ram_diag_data_buf_wpfbin_mosi,
ram_diag_data_buf_wpfbin_miso => ram_diag_data_buf_wpfbin_miso,
reg_diag_data_buf_wpfbin_mosi => reg_diag_data_buf_wpfbin_mosi,
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_packetizer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_packetizer.vhd
index 485395341599d11bd6922154af6662edfc345b27..311d50312c99e6e45a16504642665f5fe7e34f8d 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_packetizer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_packetizer.vhd
@@ -422,6 +422,7 @@ BEGIN
GENERIC MAP (
g_nof_streams => 1,
g_data_w => 8,
+ g_symbol_w => c_byte_w,
g_hdr_field_arr => c_hdr_field_arr,
g_hdr_field_sel => c_hdr_field_sel
)
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
index 8247e3b4a191f283264785d98fd3c941b406f913..ebf939b448e5b40b6a12e72613473ec7bc9fe2a7 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
@@ -163,7 +163,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS
CONSTANT c_nof_bytes_per_header : NATURAL := 90;
CONSTANT c_dp_fifo_sc_large_size : NATURAL := 4096;--16384;
CONSTANT c_fifo_fill_fill : NATURAL := ceil_div((g_nof_bytes_per_packet + c_nof_bytes_per_header), 8);
- CONSTANT c_fifo_fill_size : NATURAL := 1024;
+ CONSTANT c_fifo_fill_size : NATURAL := 2048;
SIGNAL hdr_fields_in_arr : t_slv_1024_arr(0 DOWNTO 0);
@@ -187,6 +187,8 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS
SIGNAL dp_counter_snk_out : t_dp_siso;
SIGNAL dp_counter_src_out : t_dp_sosi;
SIGNAL dp_counter_src_in : t_dp_siso;
+ SIGNAL count_offset_in_arr : t_nat_natural_arr(4 DOWNTO 0) := (OTHERS=>0);
+
SIGNAL dp_counter_count_src_out_arr : t_dp_sosi_arr(4 DOWNTO 0);
SIGNAL dp_counter_src_out_cb : STD_LOGIC_VECTOR( 2 DOWNTO 0);
@@ -251,7 +253,10 @@ BEGIN
-- . c2 = range(0,12,1) TAB
-- . c3 = range(0,4,1) SEQ
-- . c4 = range(0,88,1) CB x SB, then extract the CB and SB
+ -- The cb_rotation_offset implements per-uniboard cb rotation
-----------------------------------------------------------------------------
+ --count_offset_in_arr <= (sel_n(TO_UINT(id_band(1 DOWNTO 0)) , 0, 24, 48, 72) , 0, 0, 0, 0);
+
u_dp_counter : ENTITY dp_lib.dp_counter
GENERIC MAP (
g_nof_counters => 5, -- c3,c2,c1, c0
@@ -269,7 +274,8 @@ BEGIN
src_out => dp_counter_src_out,
src_in => c_dp_siso_rdy, --dp_counter_src_in,
- count_src_out_arr => dp_counter_count_src_out_arr
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => dp_counter_count_src_out_arr
);
-- Process to extract the CB and SB components
@@ -514,10 +520,9 @@ BEGIN
GENERIC MAP (
g_nof_streams => 1,
g_data_w => c_data_w,
+ g_symbol_w => c_byte_w,
g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_sel,
- g_in_symbol_w => c_byte_w,
- g_out_symbol_w => c_byte_w
+ g_hdr_field_sel => c_hdr_field_sel
)
PORT MAP (
mm_rst => mm_rst,
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
index 6e3c1fc27b2aa2edb1921adda599cd05073fe9a5..2be5b58af2bb5a82283e3675013bbc0f34c99a33 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
@@ -188,6 +188,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_iquv_packetizer IS
SIGNAL dp_counter_snk_out : t_dp_siso;
SIGNAL dp_counter_src_out : t_dp_sosi;
SIGNAL dp_counter_src_in : t_dp_siso;
+ SIGNAL count_offset_in_arr : t_nat_natural_arr(3 DOWNTO 0) := (OTHERS=>0);
SIGNAL dp_counter_count_src_out_arr : t_dp_sosi_arr(3 DOWNTO 0);
SIGNAL dp_counter_src_out_cb : STD_LOGIC_VECTOR( 2 DOWNTO 0);
@@ -268,7 +269,10 @@ BEGIN
-- . c1 = range(0,12,1) TAB
-- . c2 = range(0,50,1) SEQ
-- . c3 = range(0,88,1) CB x SB, then extract the CB and SB
+ -- The cb_rotation_offset implements per-uniboard cb rotation
-----------------------------------------------------------------------------
+ --count_offset_in_arr <= (sel_n(TO_UINT(id_band(1 DOWNTO 0)) , 0, 24, 48, 72) , 0, 0, 0);
+
u_dp_counter : ENTITY dp_lib.dp_counter
GENERIC MAP (
g_nof_counters => 4, -- c3,c2,c1, c0
@@ -286,7 +290,8 @@ BEGIN
src_out => dp_counter_src_out,
src_in => c_dp_siso_rdy, --dp_counter_src_in,
- count_src_out_arr => dp_counter_count_src_out_arr
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => dp_counter_count_src_out_arr
);
-- Process to extract the CB and SB components
@@ -581,10 +586,9 @@ BEGIN
GENERIC MAP (
g_nof_streams => 1,
g_data_w => c_data_w,
+ g_symbol_w => c_byte_w,
g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_sel,
- g_in_symbol_w => c_byte_w,
- g_out_symbol_w => c_byte_w
+ g_hdr_field_sel => c_hdr_field_sel
)
PORT MAP (
mm_rst => mm_rst,
diff --git a/applications/arts/designs/arts_unb1_sc4/tb/data/wave_processing.do b/applications/arts/designs/arts_unb1_sc4/tb/data/wave_processing.do
index b0902bbc0020e0a5f5f544692676be6317a92f27..045c8b8474a36f78f24e5fe663b89eea9dae7db7 100644
--- a/applications/arts/designs/arts_unb1_sc4/tb/data/wave_processing.do
+++ b/applications/arts/designs/arts_unb1_sc4/tb/data/wave_processing.do
@@ -324,21 +324,6 @@ add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/dp_sync_checker_src_out_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/dp_sync_insert_snk_in_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/dp_sync_insert_src_out_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(11) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(10) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(9) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(8) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(7) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(6) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(5) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(4) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(3) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2) {-height 16 -radix unsigned -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).data {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).re {-format Analog-Step -height 84 -max 127.0 -min -126.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).im {-format Analog-Step -height 84 -max 126.0 -min -126.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(2).err {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1) {-height 16 -radix unsigned -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).data {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).re {-format Analog-Step -height 84 -max 80.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).im {-format Analog-Step -height 84 -max 80.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(1).err {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0) {-height 16 -radix unsigned -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).data {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).re {-format Analog-Step -height 84 -max 127.0 -min -126.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).im {-format Analog-Step -height 84 -max 126.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr(0).err {-height 16 -radix unsigned}} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_snk_in_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(11) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(10) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(9) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(8) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(7) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(6) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(5) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(4) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(3) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2) {-height 16 -radix unsigned -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).data {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).re {-format Analog-Step -height 84 -max 426.00000000000006 -min -467.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).im {-format Analog-Step -height 84 -max 692.0 -min -414.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(2).err {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1) {-height 16 -radix unsigned -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).data {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).re {-format Analog-Step -height 84 -max 680.00000000000011 -min -379.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).im {-format Analog-Step -height 84 -max 830.0 -min -430.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(1).err {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0) {-height 16 -radix unsigned -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).data {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).re {-format Analog-Step -height 84 -max 402.0 -min -423.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).im {-format Analog-Step -height 84 -max 512.99999999999989 -min -535.0 -radix decimal} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr(0).err {-height 16 -radix unsigned}} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_src_out_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/ram_bf_ss_ss_wide_mosi
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/ram_bf_ss_ss_wide_miso
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/ram_bf_weights_mosi
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/ram_bf_weights_miso
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/ram_bf_st_sst_mosi
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/ram_bf_st_sst_miso
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/reg_bf_st_sst_mosi
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/reg_bf_st_sst_miso
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/bf_snk_in_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/bf_snk_out_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/bf_raw_src_out_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/bf_bst_src_out_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/bf_qua_src_out_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/iquv_i_out_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/iquv_q_out_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -height 15 -group u_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/iquv_u_out_arr
@@ -383,7 +368,15 @@ add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_art
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/expected_result_eof
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/out_val
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/out_data
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -divider {diag data buffer}
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -divider {tabs bf internal}
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/dp_counter_count_src_out_arr
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/weight_addr
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/beamformer_src_out_arr(0) -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/beamformer_src_out_arr
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/src_out_arr(0) -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/src_out_arr
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -divider {tabs beamformer unit}
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -expand /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/gen_beamformer(0)/u_beamformer/common_ram_crw_crw_rd_dat_b_arr
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/gen_beamformer(0)/u_beamformer/dp_complex_mult_snk_in_2arr_2(0) -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/gen_beamformer(0)/u_beamformer/dp_complex_mult_snk_in_2arr_2
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_arts_tab_beamformer/gen_beamformer(0)/u_beamformer/dp_complex_mult_src_out_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -divider {IAB Internal}
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/g_sim
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/g_technology
@@ -420,15 +413,20 @@ add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_art
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/dp_gain_u_snk_in
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/dp_gain_v_snk_in
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/in_complex_arr
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(0) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(1) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2) {-height 16 -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(11) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(10) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(9) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(8) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(7) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(6) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(5) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(4) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(3) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(2) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(1) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(2)(0) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(3) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(4) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(5) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(6) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(7) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(8) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(9) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(10) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(11) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(12) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(13) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(14) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(15) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(16) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(17) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(18) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(19) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(20) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21) {-height 16 -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(11) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(10) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(9) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(8) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(7) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(6) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(5) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(4) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(3) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(2) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(1) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(21)(0) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22) {-height 16 -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(11) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(10) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(9) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(8) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(7) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(6) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(5) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(4) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(3) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(2) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(1) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(22)(0) {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr(23) {-height 16}} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_in_complex_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.valid_in {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.data_in_arr {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.data_sum_out {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.data_accum_out {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.valid_accum_out {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.data_gain_in {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.valid_gain_in {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.mm_gain_ctrl {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.data_gain_out {-height 16} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i.valid_gain_out {-height 16}} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/u_iquv_iab/diag_i
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -divider {Top level signals}
-add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -radix unsigned -expand -subitemconfig {/tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(11) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(10) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(9) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(8) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(7) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(6) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(5) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(4) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(3) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(2) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(1) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0) {-height 16 -radix unsigned}} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -divider {Top level signals - tb}
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -radix unsigned -expand -subitemconfig {/tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(11) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(10) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(9) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(8) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(7) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(6) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(5) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(4) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(3) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(2) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(1) {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0) {-height 16 -radix unsigned -expand} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).data {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).re {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).im {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr(0).err {-height 16 -radix unsigned}} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_snk_in_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -radix unsigned /tb_arts_unb1_sc4_processing/dp_offload_rx_restored_src_out_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -radix unsigned -expand -subitemconfig {/tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_src_out_arr(0) {-height 16 -radix unsigned}} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_src_out_arr
add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -radix unsigned -expand -subitemconfig {/tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.sync {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.bsn {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.data {-height 16 -radix hexadecimal} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.re {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.im {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.valid {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.sop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.eop {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.empty {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.channel {-height 16 -radix unsigned} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out.err {-height 16 -radix unsigned}} /tb_arts_unb1_sc4_processing/arts_unb1_sc4_processing_iab_src_out
+add wave -noupdate -height 15 -expand -group tb_arts_unb1_sc4_processing -divider {Top level signals - dut}
+add wave -noupdate -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/dp_sync_insert_src_out_arr(0) -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/dp_sync_insert_src_out_arr
+add wave -noupdate -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_unit_dev_snk_in_arr(0) -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_unit_dev_snk_in_arr
+add wave -noupdate -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_unit_dev_src_out_arr(0) -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/wpfb_unit_dev_src_out_arr
+add wave -noupdate -expand -subitemconfig {/tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/arts_tab_beamformer_src_out_arr(0) -expand /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/arts_tab_beamformer_src_out_arr(0).re -expand} /tb_arts_unb1_sc4_processing/u_arts_unb1_sc4_processing/arts_tab_beamformer_src_out_arr
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {10837500000 fs} 0}
+WaveRestoreCursors {{Cursor 1} {16668636432 fs} 0}
configure wave -namecolwidth 300
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -443,4 +441,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits fs
update
-WaveRestoreZoom {0 fs} {5812409797 fs}
+WaveRestoreZoom {14010012500 fs} {20315262500 fs}
diff --git a/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4.vhd b/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4.vhd
index e95e53b451f7cabdc05ae193879f6479273fe83b..5cf7d0031847c39f54ea836103c621c16defc105 100644
--- a/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4.vhd
@@ -96,7 +96,7 @@ ARCHITECTURE tb OF tb_arts_unb1_sc4 IS
-- Ethernet stats
CONSTANT c_eth_check_nof_packets : NATURAL := 3;
- CONSTANT c_eth_packet_size_bytes : NATURAL := 100;
+ CONSTANT c_eth_packet_size_bytes : NATURAL := 200;
CONSTANT c_eth_packet_size_words : NATURAL := c_eth_packet_size_bytes/4+23; --23 header words TODO: formalize this
SIGNAL eth_statistics_serial_in_arr : STD_LOGIC_VECTOR(c_nof_nodes-1 DOWNTO 0);
diff --git a/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd b/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd
index f6ca0dcb338c0bad274d6ff2c9d32e5509d5a688..c326e1401032fe1c8b8faf0e8a4aa9f1f46b3669 100644
--- a/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd
@@ -82,6 +82,7 @@ ARCHITECTURE tb OF tb_arts_unb1_sc4_output IS
SIGNAL arts_unb1_sc4_output_iab_src_in : t_dp_siso := c_dp_siso_rdy;
SIGNAL arts_unb1_sc4_output_tab_snk_in_arr : t_dp_sosi_arr(c_nof_tabs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL tab_src_in : t_dp_siso := c_dp_siso_rdy;
SIGNAL reg_dp_offload_tx_iab_i_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_xonoff_iab_i_mosi : t_mem_mosi;
@@ -170,6 +171,29 @@ BEGIN
reg_dp_xonoff_iab_i_mosi.wr <= '0';
END PROCESS;
+
+ p_sink_ready : PROCESS
+ VARIABLE sink_ready_count : NATURAL := 0;
+ BEGIN
+ WAIT UNTIL dp_rst='0';
+ tab_src_in.ready <= '0';
+ tab_src_in.xon <= '0';
+ WAIT FOR 1 us;
+ WAIT UNTIL rising_edge(dp_clk);
+ tab_src_in.ready <= '1';
+ tab_src_in.xon <= '1';
+ WHILE TRUE LOOP
+ IF sink_ready_count = 3 THEN
+ sink_ready_count := 0;
+ tab_src_in.ready <= '0';
+ ELSE
+ sink_ready_count := sink_ready_count + 1;
+ tab_src_in.ready <= '1';
+ END IF;
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ END PROCESS;
+
arts_unb1_sc4_output_tab_snk_in_arr <= (others => arts_unb1_sc4_output_iab_snk_in);
------------------------------------------------------------------------------
@@ -197,7 +221,7 @@ BEGIN
tab_snk_in_arr => arts_unb1_sc4_output_tab_snk_in_arr, --(others => c_dp_sosi_rst),
tab_src_out => OPEN,
- tab_src_in => c_dp_siso_rdy,
+ tab_src_in => tab_src_in, --c_dp_siso_rdy,
reg_dp_offload_tx_tab_iquv_hdr_dat_mosi => c_mem_mosi_rst,
reg_dp_offload_tx_tab_iquv_hdr_dat_miso => OPEN,