diff --git a/applications/aartfaac/designs/aartfaac_bn_sdo/hdllib.cfg b/applications/aartfaac/designs/aartfaac_bn_sdo/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..41530f0da94e8192984706ac770704245c34b9eb
--- /dev/null
+++ b/applications/aartfaac/designs/aartfaac_bn_sdo/hdllib.cfg
@@ -0,0 +1,42 @@
+hdl_lib_name = aartfaac_bn_sdo
+hdl_library_clause_name = aartfaac_bn_sdo_lib
+hdl_lib_uses_synth = unb1_board rsp_terminal ss
+hdl_lib_uses_sim =
+
+hdl_lib_technology = ip_stratixiv
+
+synth_top_level_entity =
+
+quartus_copy_files =
+# quartus/sopc_aartfaac_bn_sdo.sopc .
+ src/quartus/sopc_aartfaac_bn_sdo.sopc .
+# src/hex/ hex
+# $UNB/Firmware/dsp/filter/build/data/ mif
+
+modelsim_copy_files =
+# src/hex hex
+# $UNB/Firmware/dsp/filter/build/data/ mif
+
+synth_files =
+ $HDL_BUILD_DIR/unb1/quartus/aartfaac_bn_sdo/sopc_aartfaac_bn_sdo.vhd
+ src/vhdl/mmm_aartfaac_bn_sdo.vhd
+ src/vhdl/aartfaac_bn_sdo_udp_sdo.vhd
+ src/vhdl/aartfaac_bn_sdo.vhd
+
+test_bench_files =
+# tb/vhdl/tb_aartfaac_bn_sdo.vhd
+ $SVN/Aartfaac/trunk/Firmware/designs/aartfaac_bn_sdo/tb/vhdl/tb_aartfaac_bn_sdo.vhd
+
+quartus_qsf_files =
+# $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+# quartus/aartfaac_bn_sdo_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+# $HDL_BUILD_DIR/unb1/quartus/aartfaac_bn_sdo/qsys_aartfaac_bn_sdo/synthesis/qsys_aartfaac_bn_sdo.qip
+
+quartus_sdc_files =
+# $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/applications/aartfaac/designs/aartfaac_bn_sdo/src/quartus/sopc_aartfaac_bn_sdo.sopc b/applications/aartfaac/designs/aartfaac_bn_sdo/src/quartus/sopc_aartfaac_bn_sdo.sopc
index d8abf9468135b33895e55f79aff995424e42380b..27a723751ac300a30d3f21692460b858bd5c5376 100644
--- a/applications/aartfaac/designs/aartfaac_bn_sdo/src/quartus/sopc_aartfaac_bn_sdo.sopc
+++ b/applications/aartfaac/designs/aartfaac_bn_sdo/src/quartus/sopc_aartfaac_bn_sdo.sopc
@@ -100,63 +100,71 @@
type = "String";
}
}
- element reg_diag_data_buffer.mem
+ element reg_stable_monitor.mem
{
datum baseAddress
{
- value = "128";
+ value = "12304";
type = "long";
}
}
- element ram_ss_reorder_out.mem
+ element reg_dp_offload_tx.mem
{
datum baseAddress
{
- value = "20480";
+ value = "12320";
type = "long";
}
}
- element reg_bsn_monitor_subband.mem
+ element reg_bsn_monitor_beamlet.mem
{
datum baseAddress
{
- value = "24576";
+ value = "1024";
type = "long";
}
}
- element reg_dp_offload_tx.mem
+ element ram_ss_reorder_out.mem
{
datum baseAddress
{
- value = "12320";
+ value = "20480";
type = "long";
}
}
- element reg_tr_nonbonded.mem
+ element ram_diag_data_buffer.mem
{
datum baseAddress
{
- value = "768";
+ value = "65536";
type = "long";
}
}
- element ram_ss_reorder_in.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "26624";
+ value = "25600";
type = "long";
}
}
- element reg_bsn_monitor_crosslet.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "13312";
+ value = "262144";
type = "long";
}
}
- element rom_system_info.mem
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "2048";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
{
datum _lockedAddress
{
@@ -165,19 +173,19 @@
}
datum baseAddress
{
- value = "4096";
+ value = "12288";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_tr_nonbonded.mem
{
datum baseAddress
{
- value = "25600";
+ value = "768";
type = "long";
}
}
- element reg_wdi.mem
+ element pio_system_info.mem
{
datum _lockedAddress
{
@@ -186,84 +194,76 @@
}
datum baseAddress
{
- value = "12288";
+ value = "0";
type = "long";
}
}
- element ram_diag_data_buffer.mem
+ element reg_diag_data_buffer.mem
{
datum baseAddress
{
- value = "65536";
+ value = "128";
type = "long";
}
}
- element reg_diagnostics.mem
+ element reg_bsn_monitor_subband.mem
{
datum baseAddress
{
- value = "256";
+ value = "24576";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element reg_diagnostics.mem
{
datum baseAddress
{
- value = "262144";
+ value = "256";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_bsn_monitor_crosslet.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "0";
+ value = "13312";
type = "long";
}
}
- element reg_unb_sens.mem
+ element ram_ss_reorder_in.mem
{
datum baseAddress
{
- value = "928";
+ value = "26624";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element rom_system_info.mem
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "512";
- type = "long";
+ value = "1";
+ type = "boolean";
}
- }
- element reg_bsn_monitor_beamlet.mem
- {
datum baseAddress
{
- value = "1024";
+ value = "4096";
type = "long";
}
}
- element reg_stable_monitor.mem
+ element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
- value = "12304";
+ value = "512";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_ovr.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "640";
+ value = "928";
type = "long";
}
}
@@ -316,7 +316,7 @@
{
datum _sortIndex
{
- value = "18";
+ value = "27";
type = "int";
}
}
@@ -358,7 +358,7 @@
{
datum _sortIndex
{
- value = "20";
+ value = "19";
type = "int";
}
}
@@ -366,7 +366,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "22";
type = "int";
}
}
@@ -374,7 +374,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "23";
type = "int";
}
}
@@ -382,7 +382,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "21";
type = "int";
}
}
@@ -390,7 +390,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "20";
type = "int";
}
}
@@ -422,7 +422,7 @@
{
datum _sortIndex
{
- value = "19";
+ value = "18";
type = "int";
}
}
@@ -435,14 +435,6 @@
}
}
element reg_dp_offload_tx
- {
- datum _sortIndex
- {
- value = "27";
- type = "int";
- }
- }
- element reg_dp_offload_tx_hdr_dat
{
datum _sortIndex
{
@@ -450,11 +442,11 @@
type = "int";
}
}
- element reg_dp_offload_tx_hdr_ovr
+ element reg_dp_offload_tx_hdr_dat
{
datum _sortIndex
{
- value = "28";
+ value = "25";
type = "int";
}
}
@@ -462,7 +454,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "24";
type = "int";
}
}
@@ -498,24 +490,19 @@
type = "int";
}
}
- element onchip_memory2_0.s1
+ element pio_debug_wave.s1
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "131072";
+ value = "976";
type = "long";
}
}
- element pio_debug_wave.s1
+ element timer_0.s1
{
datum baseAddress
{
- value = "976";
+ value = "896";
type = "long";
}
}
@@ -527,19 +514,16 @@
type = "long";
}
}
- element pio_pps.s1
+ element onchip_memory2_0.s1
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "1008";
- type = "long";
+ value = "1";
+ type = "boolean";
}
- }
- element timer_0.s1
- {
datum baseAddress
{
- value = "896";
+ value = "131072";
type = "long";
}
}
@@ -566,10 +550,10 @@
<parameter name="globalResetBus" value="true" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName">aartfaac_bn_sdo_lpbk.qpf</parameter>
+ <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-100444974251" />
- <parameter name="timeStamp" value="1395780220821" />
+ <parameter name="systemHash" value="-105761453609" />
+ <parameter name="timeStamp" value="1435833898909" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -670,7 +654,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_tr_nonbonded.mem' start='0x300' end='0x340' /><slave name='avs_eth_0.mms_reg' start='0x340' end='0x380' /><slave name='timer_0.s1' start='0x380' end='0x3A0' /><slave name='reg_unb_sens.mem' start='0x3A0' end='0x3C0' /><slave name='altpll_0.pll_slave' start='0x3C0' end='0x3D0' /><slave name='pio_debug_wave.s1' start='0x3D0' end='0x3E0' /><slave name='pio_wdi.s1' start='0x3E0' end='0x3F0' /><slave name='pio_pps.s1' start='0x3F0' end='0x400' /><slave name='reg_bsn_monitor_beamlet.mem' start='0x400' end='0x800' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x800' end='0x880' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='reg_stable_monitor.mem' start='0x3010' end='0x3020' /><slave name='reg_dp_offload_tx.mem' start='0x3020' end='0x3028' /><slave name='reg_bsn_monitor_crosslet.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_ss_reorder_out.mem' start='0x5000' end='0x6000' /><slave name='reg_bsn_monitor_subband.mem' start='0x6000' end='0x6400' /><slave name='reg_bsn_monitor.mem' start='0x6400' end='0x6800' /><slave name='ram_ss_reorder_in.mem' start='0x6800' end='0x6C00' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_ss_ss_wide.mem' start='0x40000' end='0x50000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_tr_nonbonded.mem' start='0x300' end='0x340' /><slave name='avs_eth_0.mms_reg' start='0x340' end='0x380' /><slave name='timer_0.s1' start='0x380' end='0x3A0' /><slave name='reg_unb_sens.mem' start='0x3A0' end='0x3C0' /><slave name='altpll_0.pll_slave' start='0x3C0' end='0x3D0' /><slave name='pio_debug_wave.s1' start='0x3D0' end='0x3E0' /><slave name='pio_wdi.s1' start='0x3E0' end='0x3F0' /><slave name='reg_bsn_monitor_beamlet.mem' start='0x400' end='0x800' /><slave name='pio_pps.mem' start='0x800' end='0x808' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='reg_stable_monitor.mem' start='0x3010' end='0x3020' /><slave name='reg_dp_offload_tx.mem' start='0x3020' end='0x3028' /><slave name='reg_bsn_monitor_crosslet.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_ss_reorder_out.mem' start='0x5000' end='0x6000' /><slave name='reg_bsn_monitor_subband.mem' start='0x6000' end='0x6400' /><slave name='reg_bsn_monitor.mem' start='0x6400' end='0x6800' /><slave name='ram_ss_reorder_in.mem' start='0x6800' end='0x6C00' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_ss_ss_wide.mem' start='0x40000' end='0x50000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="19" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
@@ -997,20 +981,6 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
- <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_pps">
- <parameter name="bitClearingEdgeCapReg" value="false" />
- <parameter name="bitModifyingOutReg" value="false" />
- <parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="125000000" />
- <parameter name="direction" value="Input" />
- <parameter name="edgeType" value="RISING" />
- <parameter name="generateIRQ" value="false" />
- <parameter name="irqType" value="LEVEL" />
- <parameter name="resetValue" value="0" />
- <parameter name="simDoTestBenchWiring" value="false" />
- <parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="32" />
- </module>
<module
kind="avs_common_mm"
version="1.0"
@@ -1084,12 +1054,8 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
- <module
- kind="avs_common_mm"
- version="1.0"
- enabled="1"
- name="reg_dp_offload_tx_hdr_ovr">
- <parameter name="g_adr_w" value="5" />
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -1339,15 +1305,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x6000" />
</connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.clk" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="pio_pps.s1">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03f0" />
- </connection>
<connection
kind="clock"
version="11.1"
@@ -1465,16 +1422,12 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3020" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_tx_hdr_ovr.system" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_dp_offload_tx_hdr_ovr.mem">
+ end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0800" />
</connection>
diff --git a/applications/aartfaac/designs/aartfaac_bn_sdo/tb/vhdl/tb_aartfaac_bn_sdo.vhd b/applications/aartfaac/designs/aartfaac_bn_sdo/tb/vhdl/tb_aartfaac_bn_sdo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4270c5e1d382b518e6c2861e7da1ba3fda31333b
--- /dev/null
+++ b/applications/aartfaac/designs/aartfaac_bn_sdo/tb/vhdl/tb_aartfaac_bn_sdo.vhd
@@ -0,0 +1,180 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.tb_unb1_board_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+
+ENTITY tb_aartfaac_bn_sdo IS
+GENERIC (
+ g_sim_play_udp_sdo_stream : BOOLEAN := FALSE
+ );
+END tb_aartfaac_bn_sdo;
+
+ARCHITECTURE tb OF tb_aartfaac_bn_sdo IS
+
+ CONSTANT c_nof_bn : NATURAL := 1; -- 1 BN = tx(0)->rx(0); 2 BN = TX(0) to RX(1)
+
+ CONSTANT c_nof_bn_max : NATURAL := 2;
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_unb_index : NATURAL := 0; -- Python can target this test bench @ UniBoard 0, BN 0 and 1.
+ CONSTANT c_id_arr : t_unb1_board_id_arr(c_nof_bn_max-1 DOWNTO 0) := ( (TO_UVEC(c_unb_index, c_unb1_board_nof_uniboard_w ) & TO_UVEC(5, c_unb1_board_nof_chip_w)),
+ (TO_UVEC(c_unb_index, c_unb1_board_nof_uniboard_w ) & TO_UVEC(4, c_unb1_board_nof_chip_w)) );
+
+ CONSTANT c_misalign_xcvrs : BOOLEAN := FALSE; -- TRUE misaligns back xcvr bus 0 to test BSN aligner in subband stream
+ ----------------------------------------------------------------------------
+ -- Clocks and resets
+ ----------------------------------------------------------------------------
+ CONSTANT c_mm_clk_period : TIME := 100 ps;
+ CONSTANT c_dp_pps_period : NATURAL := 8;
+ CONSTANT c_tr_clk_period : TIME := 6.4 ns;
+ CONSTANT c_eth_clk_period : TIME := 40 ns;
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_xcvr_misalign_dly : TIME := 0 ns;
+ CONSTANT c_xcvr_general_dly : TIME := 0 ns;
+
+ SIGNAL dp_pps : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC := '1';
+ SIGNAL dp_rst : STD_LOGIC := '0';
+
+ SIGNAL tr_clk : STD_LOGIC := '1';
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp_arr : STD_LOGIC_VECTOR(c_nof_bn-1 DOWNTO 0);
+ SIGNAL eth_rxp_arr : STD_LOGIC_VECTOR(c_nof_bn-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL mesh_tx_3arr : t_unb1_board_mesh_sl_3arr;
+ SIGNAL mesh_rx_3arr : t_unb1_board_mesh_sl_3arr;
+
+ SIGNAL back_tx_3arr : t_unb1_board_mesh_sl_3arr;
+ SIGNAL back_rx_3arr : t_unb1_board_mesh_sl_3arr;
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := "00";
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- Clocks
+ ----------------------------------------------------------------------------
+ dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
+ tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2;
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_rst, dp_clk, dp_pps);
+
+ ----------------------------------------------------------------------------
+ -- DUTs
+ ----------------------------------------------------------------------------
+ gen_bn: FOR BN IN 0 TO c_nof_bn-1 GENERATE
+ ----------------------------------------------------------------------------
+ -- aartfaac_bn_sdo
+ ----------------------------------------------------------------------------
+ u_aartfaac_bn_sdo : ENTITY work.aartfaac_bn_sdo
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_index,
+ g_sim_node_nr => 4+BN,
+ g_design_name => sel_a_b(c_nof_bn=2 , sel_a_b(BN=0, "aartfaac_bn_sdo_tx", "aartfaac_bn_sdo"), "aartfaac_bn_sdo_lpbk" ),
+ g_sim_play_udp_sdo_stream => g_sim_play_udp_sdo_stream
+ )
+ PORT MAP (
+ -- GENERAL
+ PPS => dp_pps,
+ WDI => WDI,
+
+ -- Others
+ VERSION => VERSION,
+ ID => c_id_arr(BN),
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp_arr(BN),
+ ETH_SGOUT => eth_txp_arr(BN),
+
+ SA_CLK => tr_clk,
+ SB_CLK => tr_clk,
+
+ FN_BN_0_TX => mesh_tx_3arr(BN)(0),
+ FN_BN_0_RX => mesh_rx_3arr(BN)(0),
+ FN_BN_1_TX => mesh_tx_3arr(BN)(1),
+ FN_BN_1_RX => mesh_rx_3arr(BN)(1),
+ FN_BN_2_TX => mesh_tx_3arr(BN)(2),
+ FN_BN_2_RX => mesh_rx_3arr(BN)(2),
+ FN_BN_3_TX => mesh_tx_3arr(BN)(3),
+ FN_BN_3_RX => mesh_rx_3arr(BN)(3),
+
+ BN_BI_0_TX => back_tx_3arr(BN)(0),
+ BN_BI_0_RX => back_rx_3arr(BN)(0),
+ BN_BI_1_TX => back_tx_3arr(BN)(1),
+ BN_BI_1_RX => back_rx_3arr(BN)(1),
+ BN_BI_2_TX => back_tx_3arr(BN)(2),
+ BN_BI_2_RX => back_rx_3arr(BN)(2),
+ BN_BI_3_TX => back_tx_3arr(BN)(3),
+ BN_BI_3_RX => back_rx_3arr(BN)(3)
+ );
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- BN xcvr interconnects / xcvr loopback
+ ----------------------------------------------------------------------------
+ gen_interconnect: IF c_nof_bn = 2 GENERATE
+ back_rx_3arr(1) <= back_tx_3arr(0);
+ END GENERATE;
+
+ gen_loopback: IF c_nof_bn = 1 GENERATE
+
+ gen_synced: IF c_misalign_xcvrs = FALSE GENERATE
+ back_rx_3arr(0) <= back_tx_3arr(0);
+ END GENERATE;
+
+ gen_misaligned: IF c_misalign_xcvrs = TRUE GENERATE
+ back_rx_3arr(0)(0) <= back_tx_3arr(0)(0) ; -- +c_xcvr_misalign_dly;
+ back_rx_3arr(0)(1) <= TRANSPORT back_tx_3arr(0)(1) AFTER 8 ns;
+ back_rx_3arr(0)(2) <= TRANSPORT back_tx_3arr(0)(2) AFTER 3 * 8 ns;
+ back_rx_3arr(0)(3) <= TRANSPORT back_tx_3arr(0)(3) AFTER 2 * 8 ns;
+ END GENERATE;
+
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- 1GbE Loopback model
+ ------------------------------------------------------------------------------
+ gen_eth_loopback: FOR i IN 0 TO c_nof_bn-1 GENERATE
+ eth_rxp_arr(i) <= TRANSPORT eth_txp_arr(i) AFTER c_cable_delay;
+ END GENERATE;
+
+END tb;