diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd index c631c171166c05abdd7e0684faf8a5b664fbf752..0d3098db8a33b893bc7627c2bea61301a2b751d6 100644 --- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd +++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd @@ -143,10 +143,10 @@ ARCHITECTURE str OF mms_diag_rx_seq IS ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2] ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3] - ( field_name_pad("step_0"), "RW", c_word_w, field_default(1) ), -- [4] = diag_steps_arr[0] - ( field_name_pad("step_1"), "RW", c_word_w, field_default(1) ), -- [5] = diag_steps_arr[1] - ( field_name_pad("step_2"), "RW", c_word_w, field_default(1) ), -- [6] = diag_steps_arr[2] - ( field_name_pad("step_3"), "RW", c_word_w, field_default(1) )); -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4 + ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0] + ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1] + ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2] + ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) )); -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4 CONSTANT c_reg_slv_w : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w; @@ -252,7 +252,7 @@ BEGIN diag_sel_arr(I) <= ctrl_reg_arr(I)(1); -- address 0, data bit [1] gen_diag_steps_2arr : FOR J IN 0 TO g_nof_steps-1 GENERATE - diag_steps_2arr(I)(J) <= TO_UINT(ctrl_reg_arr(I)(g_seq_dat_w-1 + (c_nof_steps_wi+J)*c_word_w DOWNTO (c_nof_steps_wi+J)*c_word_w)); -- address 4, 5, 6, 7 + diag_steps_2arr(I)(J) <= TO_SINT(ctrl_reg_arr(I)(g_seq_dat_w-1 + (c_nof_steps_wi+J)*c_word_w DOWNTO (c_nof_steps_wi+J)*c_word_w)); -- address 4, 5, 6, 7 END GENERATE; -- . read stat_reg_arr