From 9d67bc9d6da7c0e02926da5aedbf63dd6d2f8bed Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 24 Mar 2015 10:03:39 +0000
Subject: [PATCH] Added verify MM access for write and readback rx_steps.
---
.../base/diag/tb/vhdl/tb_mms_diag_seq.vhd | 25 ++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 2e35b186e7..2a193ebe38 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -23,7 +23,7 @@
-- Purpose: Test bench for mms_diag_tx_seq --> mms_diag_rx_seq
-- The tb is self-stopping and self-checking.
-- Usage:
--- > as 5
+-- > as 10
-- > run -all
@@ -43,12 +43,13 @@ USE work.tb_diag_pkg.ALL;
ENTITY tb_mms_diag_seq IS
GENERIC (
-- general
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_random; -- always active or random flow control
-- specific
g_nof_streams : NATURAL := 1;
+ g_use_steps : BOOLEAN := FALSE; -- when TRUE this tb can only verify +1 increment (ie. using c_rx_steps_arr_ones)
g_mm_broadcast_tx : BOOLEAN := FALSE;
g_data_w : NATURAL := 40; -- >= g_seq_dat_w
- g_seq_dat_w : NATURAL := 32
+ g_seq_dat_w : NATURAL := 16
);
END ENTITY tb_mms_diag_seq;
@@ -57,6 +58,8 @@ ARCHITECTURE str of tb_mms_diag_seq IS
CONSTANT mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_random_w : NATURAL := 16;
+ CONSTANT c_rx_steps_arr_ones : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0) := (1, 1, 1, 1);
+ CONSTANT c_rx_steps_arr_access : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0) := (1, -2, -3, 4);
SIGNAL random : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL ready : STD_LOGIC;
@@ -124,6 +127,21 @@ BEGIN
proc_common_wait_until_low(mm_clk, mm_rst);
proc_common_wait_some_cycles(mm_clk, 10);
+ -------------------------------------------------------------------------
+ -- Verify MM access for write and readback rx_steps
+ -------------------------------------------------------------------------
+ -- . write some arbitrary integer values
+ proc_diag_seq_rx_write_steps(c_st_0, c_rx_steps_arr_access, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
+ FOR I IN 0 TO c_diag_seq_rx_reg_nof_steps-1 LOOP
+ ASSERT rd_reg_arr(c_st_0).rx_steps(I)=c_rx_steps_arr_access(I) REPORT "Wrong diag rx_steps read back." SEVERITY ERROR;
+ END LOOP;
+
+ -- . write default increment +1 to have same behaviour as with g_use_steps=FALSE and diag_sel = "CNTR"
+ proc_diag_seq_rx_write_steps(c_st_0, c_rx_steps_arr_ones, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
+ FOR I IN 0 TO c_diag_seq_rx_reg_nof_steps-1 LOOP
+ ASSERT rd_reg_arr(c_st_0).rx_steps(I)=c_rx_steps_arr_ones(I) REPORT "Wrong diag rx_steps read back." SEVERITY ERROR;
+ END LOOP;
+
-------------------------------------------------------------------------
-- Verify s_off
-------------------------------------------------------------------------
@@ -293,6 +311,7 @@ BEGIN
u_mms_diag_rx_seq: ENTITY WORK.mms_diag_rx_seq
GENERIC MAP(
g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
g_seq_dat_w => g_seq_dat_w,
g_data_w => g_data_w
)
--
GitLab