diff --git a/libraries/base/dp/src/vhdl/dp_switch.vhd b/libraries/base/dp/src/vhdl/dp_switch.vhd
index 1ddb92f94a76d9b73f5cc1dbf3ff7844f3d99bd2..b8d911cb6444176f33313e348faa5dff911075d5 100644
--- a/libraries/base/dp/src/vhdl/dp_switch.vhd
+++ b/libraries/base/dp/src/vhdl/dp_switch.vhd
@@ -66,7 +66,10 @@ ENTITY dp_switch IS
mm_rst : IN STD_LOGIC;
snk_in_arr : IN t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_inputs-1 DOWNTO 0);
+
src_out : OUT t_dp_sosi;
+ src_in : IN t_dp_siso := c_dp_siso_rdy;
reg_mosi : IN t_mem_mosi;
reg_miso : OUT t_mem_miso
@@ -82,8 +85,8 @@ ARCHITECTURE str OF dp_switch IS
SIGNAL dp_mux_sel_ctrl_req : NATURAL;
SIGNAL dp_mux_sel_ctrl : NATURAL;
- SIGNAL xonoff_snk_in_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
- SIGNAL xonoff_snk_out_arr : t_dp_siso_arr(g_nof_inputs-1 DOWNTO 0);
+ SIGNAL xonoff_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+ SIGNAL xonoff_src_in_arr : t_dp_siso_arr(g_nof_inputs-1 DOWNTO 0);
SIGNAL inverted_snk_in_arr : t_dp_sosi_arr(0 TO g_nof_inputs-1);
SIGNAL inverted_snk_out_arr: t_dp_siso_arr(0 TO g_nof_inputs-1);
@@ -120,9 +123,10 @@ BEGIN
rst => dp_rst,
-- Frame in
in_sosi => snk_in_arr(i),
+ in_siso => snk_out_arr(i),
-- Frame out
- out_siso => xonoff_snk_out_arr(i), -- flush control done by dp_mux.snk_out_arr
- out_sosi => xonoff_snk_in_arr(i)
+ out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
+ out_sosi => xonoff_src_out_arr(i)
);
END GENERATE;
@@ -130,8 +134,8 @@ BEGIN
-- invert snk_in_arr, dp_mux uses a TO array.
------------------------------------------------------------------------------
gen_dp_switch_snk_in_arr : FOR i IN 0 TO g_nof_inputs-1 GENERATE
- inverted_snk_in_arr(i) <= xonoff_snk_in_arr(i);
- xonoff_snk_out_arr(i) <= inverted_snk_out_arr(i);
+ inverted_snk_in_arr(i) <= xonoff_src_out_arr(i);
+ xonoff_src_in_arr(i) <= inverted_snk_out_arr(i);
END GENERATE;
------------------------------------------------------------------------------
@@ -174,7 +178,7 @@ BEGIN
snk_out_arr => inverted_snk_out_arr,
src_out => src_out,
- src_in => c_dp_siso_rdy
+ src_in => src_in
);
END str;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
index 1a7ca6ad141e08a5b7c5ef847dbae8377e2600d0..3270695e9b8be573d57334b0429ce1f339cd9d37 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
@@ -29,6 +29,7 @@ LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
@@ -61,12 +62,15 @@ ARCHITECTURE tb OF tb_dp_switch IS
SIGNAL mm_rst : STD_LOGIC;
SIGNAL dp_gen_block_data_in_en : STD_LOGIC := '1';
- SIGNAL dp_gen_block_data_src_in : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL dp_gen_block_data_src_in_arr : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0);
SIGNAL dp_gen_block_data_src_out_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
SIGNAL dp_switch_snk_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+ SIGNAL dp_switch_snk_out_arr : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0);
+
SIGNAL dp_switch_src_out : t_dp_sosi;
+ SIGNAL dp_switch_src_in : t_dp_siso := c_dp_siso_rdy;
SIGNAL reg_dp_switch_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_switch_miso : t_mem_miso;
@@ -82,41 +86,72 @@ BEGIN
mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*7;
+
-----------------------------------------------------------------------------
- -- Generate packet streams
+ -- Generate continuous packet streams, with and without gaps
-----------------------------------------------------------------------------
+ dp_gen_block_data_src_in_arr <= dp_switch_snk_out_arr;
+
gen_generate_packets : FOR i IN 0 TO c_nof_inputs-1 GENERATE
p_generate_packets : PROCESS
BEGIN
dp_gen_block_data_src_out_arr(i) <= c_dp_sosi_rst;
+
proc_common_wait_until_low(dp_clk, dp_rst);
--proc_common_wait_some_cycles(dp_clk, 4);
-- Generate single packet
- proc_dp_gen_block_data(c_data_w, i*1000, c_packet_len, 0, 0, '0', "0", dp_clk, dp_gen_block_data_in_en, dp_gen_block_data_src_in, dp_gen_block_data_src_out_arr(i));
+ proc_dp_gen_block_data(c_data_w, i*1000, c_packet_len, 0, 0, '0', "0", dp_clk, dp_gen_block_data_in_en, dp_gen_block_data_src_in_arr(i), dp_gen_block_data_src_out_arr(i));
- -- Insert optional gap between the packets
+ -- Insert optional gap between the packets, (0 .. c_nof_inputs-1) gaps
proc_common_wait_some_cycles(dp_clk, i);
WAIT FOR 0 ns;
END PROCESS;
END GENERATE;
-----------------------------------------------------------------------------
- -- MM write different input selections
+ -- MM write different input selections and check output
-----------------------------------------------------------------------------
- p_switch_inputs : PROCESS
+ p_switch_input_stimulus : PROCESS
BEGIN
proc_common_wait_until_low(mm_clk, mm_rst);
reg_dp_switch_mosi <= c_mem_mosi_rst;
proc_common_wait_some_cycles(mm_clk, 1);
FOR I IN 0 TO c_nof_switch_runs-1 LOOP
FOR J IN 0 TO c_nof_inputs-1 LOOP
+ -- write new input selection to mm bus and wait some time
proc_mem_mm_bus_wr(0, J, mm_clk, reg_dp_switch_mosi);
- proc_common_wait_some_cycles(mm_clk, 100);
-
+ proc_common_wait_some_cycles(mm_clk, 50);
+
+ -- check if channel number in src_out is the same as requested (J)
+ ASSERT J = TO_UINT(dp_switch_src_out.channel)
+ REPORT "Wrong src_out channel" &
+ ", expected=" & int_to_str(J) &
+ ", readback=" & int_to_str(INTEGER(TO_UINT(dp_switch_src_out.channel)))
+ SEVERITY ERROR;
+
+ -- check if data value in src_out is in the expected value window (J*1000 <= data < (J+1)*1000))
+ ASSERT TO_UINT(dp_switch_src_out.data) >= J*1000 and TO_UINT(dp_switch_src_out.data) < (J+1)*1000
+ REPORT "Wrong src_out data" &
+ ", expected between=" & int_to_str(J*1000) & " and " & int_to_str((J+1)*1000) &
+ ", readback=" & int_to_str(INTEGER(TO_UINT(dp_switch_src_out.data)))
+ SEVERITY ERROR;
END LOOP;
END LOOP;
+
+ -- check if output data is stopped if output send hold signal
+ dp_switch_src_in <= c_dp_siso_hold;
+ proc_common_wait_some_cycles(mm_clk, 50);
+ ASSERT dp_switch_src_out.valid = '0'
+ REPORT "Still data on output after setting hold command" SEVERITY ERROR;
+
+ -- check if output data flows again if output send flush signal
+ dp_switch_src_in <= c_dp_siso_rdy;
+ proc_common_wait_some_cycles(mm_clk, 50);
+ ASSERT dp_switch_src_out.valid = '1'
+ REPORT "No data on output after setting flush command" SEVERITY ERROR;
+
tb_end <= '1';
WAIT;
END PROCESS;
@@ -142,7 +177,10 @@ BEGIN
mm_rst => mm_rst,
snk_in_arr => dp_switch_snk_in_arr,
+ snk_out_arr => dp_switch_snk_out_arr,
+
src_out => dp_switch_src_out,
+ src_in => dp_switch_src_in,
reg_mosi => reg_dp_switch_mosi,
reg_miso => reg_dp_switch_miso